Process Scheduling Part 2

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1 Operating Systems and Computer Networks Process Scheduling Part 2 pascal.klein@uni-due.de Alexander Maxeiner, M.Sc. Faculty of Engineering

2 Agenda Process Management Time Sharing Synchronization of Processes Scheduling Classification Scheduling Algorithms 2

3 Program Execution A program resides in local memory partially or entirely transferred to main memory upon execution The program can be comprised of: Programs, sub-routines Data Instruction pointers Stack pointers CPU states Register contents 3

4 Process Management Several processes on a single processor OS needs to monitor free resources to open tasks to allocate CPU time change between tasks What happens if another process waits for data (not uses processor power idle) 4

5 Process Management 5

6 Time Sharing Processes are split up into segments Each segment is given a specific amount of time at the CPU How much (amount of time) and when (it is given the time) depends on the implemented algorithm Multitasking: time-multiplexing, only one CPU (or Core) is occupied with several tasks Processor power is allocated within a certain time frame 6

7 Time Sharing Problem 1: How to change between processes? Problem 2: How to optimize efficiency in the use of CPU? 7

8 CPU Utilization Difficult to calculate depends on the situation E.g.: 5 processes need 20% of CPU perfect? Who waits, when? Probabilistic view of CPU Utilization: CPU utilization = 1 p n n number of processes p n probability that all processes wait for I/O (CPU idle time) Careful: independancy of processes assumed! 8

9 Time Sharing Time Wheel Model Context change T t P7 P6 P8 : Terminal IO (Keyboard or mouse) : Account : Print. User 1, 2, 3, 4. P7 9

10 Process change Time needed to switch can be between μs and ns Address range of an old process has to be saved and updated by complex memory management Process1 OS Process2 OS Process1 OS etc. t 10

11 Process change When a process/task changes: stack pointer, registers, etc. must be changed Two methods: 1. Complete set of user data / process data is stored in a private memory space 2. Context change by pointers only Program state Pointers point to start of memory slot 11

12 Process Control Block - PCB Entry in process table Data structure with information to manage scheduling Needed for correct and efficient process management Contains: Process identification data (unique identifier) o e.g.: process id, parent process, user identifier, etc. Process state data (status of a process) o e.g.: content of CPU general-purpose registers, CPU process status, stack and frame pointers, etc. Process control data (to manage process itself) o e.g.: process scheduling state, Process structuring information, Interprocess communication information, Process Privileges, Process Number (PID), Program Counter (PC), CPU Registers, Memory Management Information, etc. 12

13 Implementation of Time Sharing Scheduler I/O-readlines Task 1 Task 2 M1 PC1 M2 CPU PC2 Computer / OS Reentrant Code Peripheral memory Virtual Machine (virtual parallel) 13

14 Implementation of Time Sharing RUNNING Process 1 Scheduler or Interrupt Save PCB of process 1 Process 2 READY Load PCB of process 2 Save PCB of process 2 RUNNING SCHEDULER OR INTERRUPT RUNNING Load PCB of process 1 READY 14

15 A process queue example CPU-Queue Pointer in the Queue PCBi PCBk PCBa Start end Register, etc. Register, etc. Register, etc. NIL Disk Queue PCBb PCBx Start end Register, etc. Register, etc. NIL 15

16 Synchronization of Processes When to change between processes? a) by cyclic flow control (polling), i.e. processes call for data, program-controlled b) time-controlled in certain given intervals with a real-time clock c) by request (interrupt) via the technical process eventcontrolled. 16

17 Cyclic Flow Control (Polling) P A P B P x : Process looking for Data polling C/D 2 D C e.g.: 5 processes: 4 idle, 1 busy. Drawback: CPU is always busy with polling, though it is often idle due to I/O operations. 17

18 Time-controlled P A idle time? Time A P B Time A If time intervals too short number of data swapping increases until a process is finished decrease of overall efficiency If time intervals too long finished process will leave the CPU with idle time P x : Process execution 18

19 Request (Interrupt) Process requests (triggered by the technical process): can be announced at any time have high priority (importance) by o priority in execution and/or o blocking other requests also leads to context change Process Scheduling P A Interrupt? Execute Interrupt P x : Process execution 19

20 Request (Interrupt) Example A background process is interrupted by two interrupts Priority IRS2 Interrupt BGP: Backgroundprocess IRSi: Interrupt Subroutine i Ii: Interrupt i IRS1 IRS1 BGP BGP Time I1 I2 20

21 Why Scheduling? Problem: Multiple processes or threads need CPU resources at the same time OS chooses the next steps for the upcoming queued processes (to be processed) Three different types of environments Batch Interactive Real time 21

22 Planning Criteria The scheduler needs to be planned with respect to the following criteria: Use/efficiency of CPU-Utilization (40 % - 90 %) Throughput (completed processes / time unit) Cycle time (time from input to output of the results) Waiting time (Waiting in the CPU Waiting Queue) Response time (In interactive systems: Time to reaction) Turnaround time (The time until a job is finished) 22

23 Non-Preemptive vs preemptive Scheduling Non-Preemptive scheduling: process is picked and started until it blocks (either on I/O or waiting state) or voluntarily releases the CPU process will not be forcibly suspended until a higher priority interrupt occurs Preemptive scheduling: process starts and runs for a fixed amount of time If process still runs at end of time cycle, it is suspended requires a clock interrupt occuring at the end of every time interval to give control of CPU back to scheduler 23

24 Planning in batch systems Big systems working on steady bulky jobs Non-preemptive is fine no users waiting for quick results Long processing acceptable Reducing of process switches Throughput Turnaround Time CPU Utilization Main Memory Disk CPU 24

25 Planning in Interactive Systems PC, Webserver, ATM... Preemptive is needed More than one process running all the time All users are in big hurry... Response Time Proportionality meets users expectations 25

26 Real Time Systems Systems which keep in real time constraints immediate action needed Preemptive handling not needed processes need to be securely finished processes will not block for long Only specialized software used Application runs well-known and specialized programmes strongly compatible with the application Meeting Deadlines Predictability 26

27 Scheduling Goals Throughput Turnaround Time CPU Utilization Response Time Proportionality meets users expectations Meeting Deadlines Predictability Fairness (fair amount of share Policy enforcement (strategy enforcement) Balance (all parts of system should be busy) 27

28 Scheduler Depend on certain events: scheduler selects next process queue of ready processes from the OS 4 When? Blocked Existent 6 5 Scheduling decisions can be made: 1 Running 3 2 Ready in transition from running to blocked state (waiting for I/O 4) in transition from running to ready state (Interrupt 2) in transition from blocked to ready state (I/O end 5) Upon termination of a process 28

29 Requirements of Scheduling Algorithms Fairness Each process needs fair share of CPU time comparable processes should get comparable service Utilization of resources keep all parts of the system busy Algorithm must be executed efficiently No wasting of resources Minimized overhead 29

30 Classsifications of Scheduling Algorithms Static (a priori) Scheduling Algorithms Scheduling decisions take place at a fixed time interval Process coordination: Scheduling is planned before the programs run Input of a scheduling algorithm is a set of processes which will be considered for scheduling Processes arriving the scheduler during the runtime of a process, stored for next cycle Scheduled processes run until all of them are done and/or until the given time is over. Conditions for static algorithms: No dynamic process creation during the program Event-driven processes can be incorporated only if the time conditions are schedulable 30

31 Classsifications of Scheduling Algorithms Dynamic Scheduling Algorithms Coordination of processes takes place while the processes are running Times of updates: at fixed time intervals as soon as a new process is created as soon as a process ends Advantages and disadvantages event-driven processes must be coordinated decision making during scheduler operation costs time Lack of efficiency: heuristics are required! 31

32 Classsifications of Scheduling Algorithms Algorithms for complex process models Complex process models: Interruptible, non-interruptible processes interruptible process at any or only at certain times? Cyclic, non-cyclic processes Switching to another processor 32

33 Scheduler Algorithms 33

34 0 Scheduler: First Come, First Serve First process that arrives the scheduler will be the next in line no Interrupts Example: (32ms) : τ1 = 300 ms waiting period 0 ms : τ2 = 40 ms waiting period 300 ms : τ3 = 32 ms waiting period 340 ms (40ms) (300ms) (300ms) (40ms) (32ms) Average Waiting Time: ( ) / 3 = 640 / 3 = ms Min Average Waiting Time:,, ( ) / 3 = 104 / 3 = ms 34

35 Scheduler: First Come, First Serve First process that arrives the scheduler will be the next in line no Interrupts Example: : τ1 = 300 ms waiting period 0 ms : τ2 = 40 ms waiting period 300 ms : τ3 = 32 ms waiting period 340 ms (300ms) (40ms) Min Average Turnaround Time:,, ( ) / 3 = 476 / 3 = ms (32ms) Average Turnaround Time: ( ) / 3 = 1012 / 3 = ms 0 0 (32ms) 32 (40ms) 72 (300ms)

36 Scheduler: Shortest Job First At Scheduler Decision (which process is next): Choose the job that needs the least amount of time Interruption possible when shorter job arrives Provides optimum in terms of waiting time! In Short-term planning: Not applicable, since next block computation time is not known! Critical process with a long runtime? Stalled until faster processes are computed 36

37 Scheduler: Shortest Job First Assumption: Time required for next block is known : τ1 = 8 ms, arrival time: 0ms : τ2 = 4 ms, arrival time: 1ms : τ3 = 9 ms, arrival time: 2ms : τ4 = 5 ms, arrival time: 3ms Average Waiting Time: [ (5-3) + (10-1) + (17-2)] / 4 = 26 / 4 = 6.5 ms Arrival: 0 (4) (8) 5 (9) (5) (1ms) (4ms) (5ms) (7ms) (9ms)

38 Scheduler: Shortest Job First 0 Assumption: Time required for next block is known : τ1 = 8 ms, arrival time: 0ms : τ2 = 4 ms, arrival time: 1ms : τ3 = 9 ms, arrival time: 2ms : τ4 = 5 ms, arrival time: 3ms Arrival: 1 2 (4) 3 (8) 5 (5) (9) (8ms) (4ms) (5ms) (9ms) (8ms) (4ms) (9ms) (5ms) Average Waiting Time: [ (5-3) + (10-1) + (17-2)] / 4 = 26 / 4 = 6.5 ms Without interruption: SJF: ( ) / 4 = 7.75 ms FCFS: ( ) / 4 = 8.75 ms SJF FCFS 38

39 Scheduler: Priority Scheduling Chooses process with highest priority If another process with higher priority arrives Sending Interrupt active task is replaced by the new one Problem: Low-priority processes will wait a long time Solution: Increasing priority of waiting task 39

40 Scheduler: Round-robin Scheduler (RR) Switches between tasks after fixed interval of time New processes are added complete ones are removed Guarantees fair amount of time Problems: time waste due to change of processes Completion time of long runtime processes (more active tasks, higher completion time) 0 Arrival: 1 2 (4) 3 (8) 5 (9) (5)

41 Scheduler: Combination of several allocation levels Time sharing as background job (RR) plus Interrupt on demand based on priorities Within a priority level, the allocation shall be made according to RR After an appropriate waiting time processes can move up in priority Aging 41

42 Example Two Processors: I & II 5 processes have to be handled Scheduling: Priority Scheduling A running process will be interrupted if another process with higher priority arrives If one of the CPUs is unoccupied and a higher priority task needs to be scheduled Free Core will be assigned to the task Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) 42

43 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) Processor I Processor II At t=0ms, arrive: Priority of is higher, both processors are available => Assign -> Processor I Assign -> Processor II

44 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) Processor I Processor II At t=0ms, arrive: Priority of is higher, both processors are available => Assign -> Processor I Assign -> Processor II At t=1ms arrives: Priority > will be interrupted by (on Processor II)

45 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) Processor I Processor II At t=0ms, arrive: Priority of is higher, both Processors are available => Assign -> Processor I Assign -> Processor II At t=1ms arrives: Priority > will be interrupted by (on Processor II)

46 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) Processor I Processor II At t=0ms, arrive: Priority of is higher, both Processors are available => Assign -> Processor I Assign -> Processor II At t=1ms arrives: Priority > will be interrupted by (on Processor II) continues (on Processor I) after finished

47 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) Processor I Processor II At t=0ms, arrive: Priority of is higher, both Processors are available => Assign -> Processor I Assign -> Processor II At t=1ms arrives: Priority > will be interrupted by (on Processor II) continues (on Processor I) after finished

48 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) At t=5ms arrives Priority > > Priority > will be interrupted by (on Processor I) Processor I Processor II

49 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) At t=6ms arrives, > > > will interrupted by (on Processor II) Processor I Processor II

50 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) At t=6ms arrives, > > > will interrupted by (on Processor II) Processor I Processor II

51 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) At t=6ms arrives, > > > will interrupted by (on Processor II) Processor I Processor II

52 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) At t=6ms arrives, > > > will interrupted by (on Processor II) Processor I Processor II

53 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) At t=6ms arrives, > > > will interrupted by (on Processor II) Processor I Processor II

54 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I Processor I Processor II

55 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I Processor I Processor II

56 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I Processor I Processor II

57 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I Processor I Processor II

58 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I After finished, will be continued on Processor II Processor I Processor II

59 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I After finished, will be continued on Processor II finished, Processor I unoccupied Processor I Processor II

60 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I After finished, will be continued on Processor II finished, Processor I unoccupied Processor I Processor II

61 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I After finished, will be continued on Processor II finished, Processor I unoccupied Processor I Processor II

62 Example Priorities and Arrival times for..: Priority 1: (t=0, τ = 7 ms) Priority 2: (t=0, τ = 3 ms), (t=1, τ = 10 ms) Priority 3: (t=5, τ = 6 ms), (t=6, τ = 9 ms) After finished, will be continued on Processor I After finished, will be continued on Processor II finished, Processor I unoccupied finished, Processor II unoccupied Processor I Processor II

63 Questions? 63

64 Resources Tanenbaum, Andrew S., Modern Operating Systems, 3rd edition, Pearson Education Inc, Amsterdam, Netherlands, Tanenbaum, Andrew S., Moderne Bertriebssysteme, 3rd edition, Pearson Education Inc, Amsterdam, Netherlands,

Announcements. Reading. Project #1 due in 1 week at 5:00 pm Scheduling Chapter 6 (6 th ed) or Chapter 5 (8 th ed) CMSC 412 S14 (lect 5)

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