IN2515. STAND-ALONE CAN CONTROLLER (Functional equivalent МCР2515 Microchip) TECHNICAL DATA FEATURES

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TECHNICAL DATA STAND-ALONE CAN CONTROLLER (Functional equivalent МCР255 Microchip) IN255 is a stand-alone Controller Area Network (CAN) controller that implements the CAN

FEATURES Supply voltage range V CC : - for IN255AN, IN255ADW 2.7 5.5 V, - for IN255BN, IN255BDW; 4.5 5.

High-speed SPI Interface (MHz): - SPI modes. and. Implements CAN V2.

1 TECHNICAL DATA STAND-ALONE CAN CONTROLLER (Functional equivalent МCР255 Microchip) IN255 is a stand-alone Controller Area Network (CAN) controller that implements the CAN specification, version 2.B The IC is designed to perform data receiving-transmitting in automotive and industrial applications. FEATURES Supply voltage range V CC : - for IN255AN, IN255ADW V, - for IN255BN, IN255BDW; V Three transmit buffers with prioritizaton and abort features of the transmittance Two receive buffers with prioritized message storage - Six 29-bit filters - Two 29-bit masks High-speed SPI Interface (MHz): - SPI modes. and. Implements CAN V2.B at Mb/s: - 8 byte length in the data field - Standard and extended data and remote frames Data byte filtering on the first two data bytes IN255 8-Lead PDIP 8-Lead IC 2-Lead TSP Fig. Package Types ORDERING INFORMATION Device Operating Temperature Range Package Packing IN255AN DIP-8 Tube IN255ADT T A = -4 to 85 C P-8 Tape & Reel IN255ATSDT TSSP-2 Tube & Reel IN255BN DIP-8 Tube T A = -4 to 25 C IN255BDT P-8 Tape & Reel 27 Nov, Rev.

2 IN255 PIN LAYOUT TXCAN 8 Vcc RXCAN 2 7 RESET CLKOUT/ F 3 6 TXRTS 4 5 TXRTS 5 4 TX2RTS 6 3 OSC2 7 2 INT OSC 8 RXBF GND 9 RXBF Fig. 2 IN255BN, IN255AN Pin Layout TXCAN 8 Vcc RXCAN 2 7 RESET CLKOUT/ F 3 6 TXRTS 4 5 TXRTS 5 4 TX2RTS 6 3 OSC2 7 2 INT OSC 8 RXBF GND 9 RXBF Fig 3 IN255BDW, IN255ADW Pin Layout 2 27, Nov, Rev.

3 IN255 Table. 8-Lead PDIP / IC Package Pin Description Pin Number Symbol Function TXCAN Transmit output pin to CAN bus 2 RXCAN Receive input pin from CAN bus 3 CLKOUT / F Clock output pin with programmable prescaler 4 TXRTS 5 TXRTS Transmit buffer TXB request-to-send. kω internal pull-up to VDD Transmit buffer TXB request-to-send. kω internal pull-up to VDD 6 TX2RTS Transmit buffer TXB2 request-to-send. kω internal pull-up to VDD 7 OSC2 Oscillator output (Quartz resonator connection) 8 OSC Oscillator input (Quartz resonator or external clock connection) 9 GND Common pin (Ground) RXBF Receive buffer RXB interrupt pin or general purpose digital output RXBF Receive buffer RXB interrupt pin or general purpose digital output 2 INT Interrupt output pin 3 SPI Clock input pin for SPI interface 4 Data input pin for SPI interface 5 Data output pin for SPI interface 6 7 RESET Chip select input pin for SPI interface Active low device reset input 8 V CC Positive supply for logic and I/O pins Notes CAN Controller Area Network 2 SPI Serial Peripheral Interface 3 27, Nov, Rev.

4 IN255 Fig 4 IN255ATSD Pin Layout Table 2. 2-Lead TSP Package Pin Description Pin Number Symbol Function TXCAN Transmit output pin to CAN bus 2 RXCAN Receive input pin from CAN bus 3 CLKOUT / F Clock output pin with programmable prescaler 4 TXRTS 5 TXRTS Transmit buffer TXB request-to-send. kω internal pull-up to VDD Transmit buffer TXB request-to-send. kω internal pull-up to VDD 6 NC 7 TX2RTS Transmit buffer TXB2 request-to-send. kω internal pull-up to VDD 8 OSC2 Oscillator output (Quartz resonator connection) 9 OSC Oscillator input (Quartz resonator or external clock connection) GND Common pin (Ground) RXBF Receive buffer RXB interrupt pin or general purpose digital output 2 RXBF Receive buffer RXB interrupt pin or general purpose digital output 3 INT Interrupt output pin 4 SPI Clock input pin for SPI interface 5 NC 6 Data input pin for SPI interface 7 Data output pin for SPI interface 8 9 RESET Chip select input pin for SPI interface Active low device reset input 2 V CC Positive supply for logic and I/O pins Notes CAN Controller Area Network 2 SPI Serial Peripheral Interface 4 27, Nov, Rev.

5 IN255 BLOCK DIAGRAM CAN-module (controller core) RXCAN TXCAN CANprotocole engine TX & RX buffers, masks & filters SPI Inteface logic SPI bus Control logic OSC OSC2 CLKOUT Clocking sig INT nal signal RXBF signal RXBF Control & interrupt registers signal TXRTS signal TXRTS signal TX2RTS signal RESET Fig 4 Block Diagram 5 27, Nov, Rev.

6 TXREQ ABTF MLOA TXERR MESSAGE TXREQ ABTF MLOA TXERR MESSAGE TXREQ ABTF MLOA TXERR MESSAGE IN255 BUFFERS Receive mask RXM TXB TXB TXB2 R E C E I V I N G Receive mask RXM Receive filter RXF Receive filter RXF Receive filter RXF2 Receive filter RXF3 Receiving filter RXF4 Receive filter RXF5 R E C E I V I N G Message queue control Transmit byte sequencer R X B Identifier M A B Identifier R X B Data field Data field CAN protocol engine Receive error counter REC TEC Transmit shift register Receive shift register Transmit error counter ErrPass BusOff CRC generator CRC check Protocol finite state machine F Transmit logic Bit clock logic Bit clock generator TX RX Configuration register Fig 5 CAN Module (Controller Core) Block Diagram 6 27, Nov, Rev.

7 IN255 ABLUTE MAXIMUM RATING Table 2 Symbol Parameter Value Unit Min Max V CC Supply voltage - for IN255AN, IN255ADW - for IN255BN, IN255BDW V I Input voltage (all pins) -.6 Vcc V V V I Input voltage for RXCAN,, TXnRTS,, pins at functional check mode -.6 Vcc+. V Тa Ambient (storage) temperature o C * Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATION MODE Table 3 Symbol Parameter Value Unit Min Max Supply voltage Vcc - for IN255AN, IN255ADW V - for IN255BN, IN255BDW Input voltage (all pins) Vcc V V I V I Тa Input voltage for RXCAN,, TXnRTS,, pins at functional check mode Ambient (operating) temperature - for IN255AN, IN255ADW - for IN255BN, IN255BDW -.3 Vcc+. V o C 7 27, Nov, Rev.

8 IN255 DC ELECTRICAL CHARACTERISTI Table 4. Parameter Symbol Value Min Max Test Conditions Unit Low level output voltage ТXCAN pin V OL -. I OL =.6 ma, V CC = 4.5 V RXnBF pin V OL2 -.6 I OL = 8.5 ma, V CC = 4.5 V, CLKOUT pins V OL3 -.6 I OL = 2. ma, V CC = 4.5 V INT pin V OL4 -.6 I OL =.6 ma, V CC = 4.5 V High level output voltage ТXCAN pin V OH 3,8 - RXnBF pin, CLKOUT pins V OH INT pin Low level input leakage current I OH = -3. ma, V CC = 4.5 V V OH I OH = -3. ma, V CC = 4.5V I OH = -4 A, V CC = 4.5 V V OH I OH = -. ma, V CC = 4.5V V V RXCAN,,,, RESET, CLKOUT, RXnBF, pins I ILL - - OSC pin I ILL High level input leakage current RXCAN,,,, RESET, CLKOUT, RXnBF, pins I ILH - OSC pin I ILH2-5 Operating consumption current I OCC - Standby consumption current IN255ADW, IN255AN I C - 5 IN255BDW, IN255BN 8 V IN = V V CC = 5.5 V V CC = 5.5 V V IN = 5.5 V V CC = 5.5 V F OSC =25 MHz V CC = 5.5 V V IN = 5.5 V A A ma A Note: - for IN255ADW, IN255AN Тa from 4 to + 85 C, - for IN255BDW, IN255BN Тa from 4 to + 25 C 8 27, Nov, Rev.

9 IN255 AC PARAMETERS Table5. Parameter Symbol Min Value Max Test Conditions Unit CAN- Interface Wake-up noise filter T WF - V CC = 5.5 V ns RESET pin low level duration IN255AN, IN255ADW IN255BN, IN255BDW t rl 2 - Vcc = 2.7 V s Vcc = 4.5 V SPI-interface Clock frequency F CLK - - MHz setup time T S ns hold time T H ns disable time T D ns Data setup time ( pin) T SU - - ns Data hold time ( pin) T HD - - ns Clock high time T HI ns Clock low time T LO ns Clock delay time T CLD ns Clock enable time T CLE ns Output valid from clock low T V ns Output hold time ( pin) T HO - - ns Output disable time ( pin) T DIS - - ns Note: - for IN255ADW, IN255AN Тa from 4 to + 85 C, - for IN255BDW, IN255BN Тa from 4 to + 25 C 9 27, Nov, Rev.

10 IN255 FUNCTIONALITY IN255AN, IN255ADW, IN255BN, IN255BDW (further IN255) are stand-alone Controller Area Network (CAN) controllers that implements the CAN specification, version 2.B. It is capable of transmitting and receiving both standard and extended data and remote frames. The IN255 has two acceptance masks and six acceptance filters that are used to filter out unwanted messages, thereby reducing the host MCUs overhead. The IN255 is designed to interface directly with the Serial Peripheral Interface (SPI) port available on many microcontrollers and supports Mode, and Mode,. Commands and data are sent to the device via the pin, with data being clocked in on the rising edge of. Data is driven out by the MCP255 (on the line) on the falling edge of. The pin must be held low while any operation is performed. The IN255 expects the first byte after lowered to be the instruction/command byte. This means that must be raised and then lowered again to input another command. Table 6 contains complete list of bytes of SPI instruction set. On detail output and input diagram of both operation modes (Mode. & Mode.) please refer to Fig 5 & 6. SPI Instruction Set Table 6 Instruction Name Instruction Format RESET Description Resets internal registers to default state, set Configuration mode. READ Read data from register beginning at selected address Read RX Buffer nm When reading a receive buffer, reduces the overhead of a normal read command by placing the address pointer at one of four locations, as indicated by n,m. Note: The associated RX flag bit (CANINTF.RXnIF) will be cleared after bringing high. WRITE Write data to register beginning at selected address. Load TX Buffer RTS abc When loading a transmit buffer, reduces the overhead of a normal Write command by placing the address pointer at one of six locations as indicated by a,b,c. (Message Request-To- Send) nnn Read Status RX Status Bit Modify Instructs controller to begin message transmission sequence for any of the transmit buffers. Quick polling command that reads several status bits for transmit and receive functions. Quick polling command that indicates filter match and message type (standard, extended and/or remote) of received message. Allows the user to set or clear individual bits in a particular register. Note: Not all registers can be bit-modified with this command. Executing this command on registers that are not bitmodifiable will force the mask to FFh. 27, Nov, Rev.

11 IN255 RESET The RESET instruction can be used to re-initialize the internal registers of the IN255 and set Configuration mode. This command provides the same functionality, via the SPI interface, as the RESET pin. The RESET instruction is a single-byte instruction that requires selecting the device by pulling low, sending the instruction byte and then raising. It is highly recommended that the reset command be sent (or the RESET pin be lowered) as part of the power-on initialization sequence. READ The READ instruction is started by lowering the pin. The READ instruction is then sent to the IN255 followed by the 8-bit address (A7 through A). Next, the data stored in the register at the selected address will be shifted out on the pin. The internal address pointer is automatically incremented to the next address once each byte of data is shifted out. Therefore, it is possible to read the next consecutive register address by continuing to provide clock pulses. Any number of consecutive register locations can be read sequentially using this method. The read operation is terminated by raising the pin (Figure 6) Instruction Address byte A A Don t care Data out Fig.6 READ Instruction Read RX Buffer The Read RX Buffer instruction (Figure 7) provides a means to quickly address a receive buffer for reading. This instruction reduces the SPI overhead by one byte, the address byte. The command byte actually has four possible values that determine the address pointer location. Once the command byte is sent, the controller clocks out the data at the address location the same as the READ instruction (i.e., sequential reads are possible). This instruction further reduces the SPI overhead by automatically clearing the associated receive flag (CANINTF.RXnIF) when is raised at the end of the command Instruction n m Don t care Data out n m Address pointer Address Receive buffer, Start at RXBDH Receive buffer, Start at RXBD Receive buffer, Start at RXBDH Receive buffer, Start at RXBD x6 x66 x7 x76 WRITE Fig. 7 READ RX BUFFER instruction 27, Nov, Rev.

12 IN255 The WRITE instruction is started by lowering the pin. Then the WRITE instruction is then sent to the IN255 followed by the address and at least one byte of data. It is possible to write to sequential registers by continuing to clock in data bytes, as long as is held low. Data will actually be written to the register on the rising edge of the line for the D bit. If the line is brought high before eight bits are loaded, the write will be aborted for that data byte and previous bytes in the command will have been written. Refer to the timing diagram in Figure 8 for a more detailed illustration of the byte write sequence Instruction Address byte Data byte A A Fig. 8 BYTE WRITE instruction Load TX Buffer The Load TX Buffer instruction (Figure 9) permits to operate without the eight-bit address required by a normal write command. The eight-bit instruction sets the address pointer to one of six addresses to quickly write to a transmit buffer that points to the ID or data address of any of the three transmit buffers Instruction a b c Data out a b c Address pointer Transmit buffer, Start at TXBDH Transmit buffer, Start at TXBD Transmit buffer, start at TXBDH Transmit buffer, Start at TXBD Transmit buffer 2, Start at TXB2DH Transmit buffer 2, Start at TXB2D Address x3 x36 x4 x46 x5 x56 Fig. 9 LOAD TX BUFFER instruction 2 27, Nov, Rev.

13 IN255 Request-To-Send (RTS) The RTS command can be used to initiate message transmission for one or more of the transmit buffers. The IN255 is selected by lowering the pin. The RTS command byte is then sent. Shown in Figure, the last 3 bits of this command indicate which transmit buffer(s) are enabled to send. This command will set the TxBnCTRL.TXREQ bit for the respective buffer(s). Any or all of the last three bits can be set in a single command. If the RTS command is sent with nnn =, the command will be ignored Instruction T2 T T Fig. REQUEST-TO-SEND instruction (RTS) Read Status Instruction The Read Status instruction allows single instruction access to some of the often used status bits for message reception and transmission. The IN255 is selected by lowering the pin and the read status command byte, shown in Figure, is sent to the IN255. Once the command byte is sent, the IN255 will return eight bits of data that contain the status. If additional clocks are sent after the first eight bits are transmitted, the IN255 will continue to output the status bits as long as the pin is held low and clocks are provided on. Each status bit returned in this command may also be read by using the standard read command with the appropriate register address Instruction Don t care Data out Repeat data out Fig READ STATUS instruction CANINTF.RXIF CANINTFL.RXIF TXBCNTRL.TXREQ CANINTF.TXIF TXBCNTRL.TXREQ CANINTF.TXIF TXB2CNTRL.TXREQ CANINTF.TX2IF 3 27, Nov, Rev.

14 IN255 RX Status The RX Status instruction (Figure 2) is used to quickly determine which filter matched the message and message type (standard, extended, remote). After the command byte is sent, the controller will return 8 bits of data that contain the status data. If more clocks are sent after the 8 bits are transmitted, the controller will continue to output the same status bits as long as the pin stays low and clocks are provided Instruction Don t care Data out Repeat data out Received msg No RX- message Message in RXB Message in RXB Message in both buffers* CANINTF.RXnIF are mapped in bits 7 & Received msg type. Standard data frame Standard remote frame Extended data frame Extended remote frame Extended ID bit mapped in bit 4. RTR bit mapped in bit 3. 2 Filter match * Buffer has higher priority, therefore bits, 4: display RXB.status Fig. 2 RX STATUS instruction RXF RXF RXF2 RXF3 RXF4 RXF5 RXF (rollover to RXB) RXF (rollover to RXB) Bit Modify Instruction The Bit Modify instruction provides a means for setting or clearing individual bits in specific status and control registers. This command is available for registers BFPCTRL, TXRTSCTRL, CANCTRL, CNF3, CNF2, CNF, CANINTE, CANINTF, EFLG, TXBCTRL, TXBCTRL, TXB2CTRL, RXBCTRL, RXBCTRL only. Mask byte Data byte X X X X Previous Register Content Result Register Content Fig. 3 Bit Modify instruction 4 27, Nov, Rev.

15 IN255 Note: Executing the Bit Modify command on registers that are not bit-modifiable will force the mask to FFh. This will allow bytewrites to the registers, not bit modify. The chip is selected by lowering the pin then the Bit Modify command is applied to the IN255. The command is followed by the address of the register, the mask byte and finally the data byte. The mask byte determines which bits in the register will be allowed to change. A in the mask byte will allow a bit in the register to change, while a will not. The data byte determines what value the modified bits in the register will be changed to. A in the data byte will set the bit and a will clear the bit, provided that the mask for that bit is set to a (see Figure 4) Instruction Address byte Mask byte Data byte A A Fig 4 - BIT MODIFY instruction 3 Mode, Mode, MSB in LSB in Fig. 5 SPI- interface input timing Mode, Mode, MSB out LSB out Don t care Fig. 6 SPI- interface output timing 5 27, Nov, Rev.

16 IN255 PACKAGE DIMENONS Fig. 7 8-Lead Plastic Small Outline (IC) pins Fig. 8-8-Lead Plastic Dual In-line (DIP) 6 27, Nov, Rev.

17 IN255 Fig. 9-2-Lead Plastic Thin Shrink Small Outline (TSP) 7 27, Nov, Rev.

MCP2510. Stand-Alone CAN Controller with SPI Interface FEATURES DESCRIPTION PACKAGE TYPES

MCP2510. Stand-Alone CAN Controller with SPI Interface FEATURES DESCRIPTION PACKAGE TYPES Stand-Alone CAN Controller with SPI Interface FEATURES Implements Full CAN V2.0A and V2.0B at 1 Mb/s - 0-8 byte message length - Standard and extended data frames - Programmable bit rate up to 1 Mb/s -