20uA at VDD=5.5V 5uA at VDD=3.6V. 1T up to 20 (1T~8T can change on fly) RC ( 24MHz) Program Flash ( byte) 4K 4K RAM( byte)

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Ashlyn Townsend
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1 SM SM39R4051 SM39R4051 SM39R4051 SM SM SM39R4051 MCU ( 1) Feature SM SM39R4051 (V) 3.0~ ~5.5 I DD (Power Down) 20uA at VDD=5.5V 5uA at VDD=3.6V 3.5uA at VDD=5.0V System clock(mhz) 12T up to 25 1T up to 20 (1T~8T can change on fly) RC ( 24MHz) Program Flash ( byte) 4K 4K RAM( byte) GPIO (When Use internal RC and Internal Reset) Interrupt 5 7 WDT (max msec) (max 33.5 sec) 16-bit Dual DPTR Timer 2 2 UART 1 1 EEPROM ICP/ISP/IAP IIC interface ( ) ISSFA-0xxx 1 Ver. A 2010/07

2 SM SM39R4051 SyncMOS SM39R4051ihhNP yymmv (20L PDIP Top View) RESET 1 20 VDD RXD/P P1.7 TXD/P P1.6 XTAL P1.5 XTAL P1.4 INT0/P P1.3 INT1/P P1.2 T0/P P1.1/AIN1 T1/P P1.0/AIN0 VSS P3.7 ISSFA-0xxx 2 Ver. A 2010/07

3 SM894051() Hex\Bin X000 X001 X010 X011 X100 X101 X110 X111 Bin/Hex F8 FF F0 B F7 E8 EF E0 ACC E7 D8 DF D0 PSW D7 C8 CF C0 C7 B8 IP SCONF BF B0 P3 B7 A8 IE AF A0 A7 98 SCON SBUF WDTC 9F 90 P1 LEDENP1 LEDENP3 WDTKEY TCON TMOD TL0 TL1 TH0 TH1 8F 80 SP DPL DPH PCON 87 SM39R4051( 3) Hex\Bin X000 X001 X010 X011 X100 X101 X110 X111 Bin/Hex F8 IICS IICCTL IICA1 IICA2 IICRWD IICEBT FF F0 B TAKEY F7 E8 P4 EF E0 ACC ISPFAH ISPFAL ISPFD ISPFC LVC SWRES E7 D8 P3M0 P3M1 P4M0 P4M1 DF D0 PSW P1M0 P1M1 D7 C8 CF C0 IRCON C7 B8 IEN1 IP1 S0RELH BF B0 P3 WDTC WDTK B7 A8 IEN0 IP0 S0RELL AF A0 P1WE P31WE REV REV REV A7 98 S0CON S0BUF 9F 90 P1 AUX TCON TMOD TL0 TL1 TH0 TH1 CKCON IFCON 8F 80 SP DPL DPH DPL1 DPH1 PCON 87 ISSFA-0xxx 3 Ver. A 2010/07

4 SM Addr. SM39R4051 Addr. - WDTKEY 97H TAKEY F7H WDTC 1. WDTC[2:0] 8 Period = m sec ~ m sec 9FH WDTC WDTK KHz 4. WDTC[3:0] B6H B7H 2. WDTKEY 1~ WDTC Period = 1.02 m sec ~ sec 5. KEY(TAKEY) WDTCWDT WDTK0x IE A8H IEN0 A8H IP B8H IEN1 B8H IP A9H IP1 B9H ISSFA-0xxx 4 Ver. A 2010/07

5 1. SM39R4051 SM SM39R4051 SM m sec ~ sec m sec~ m sec 2. SM39R4051 W77E58 SM39R4051 SM WDTC (0xB6H) WDTC (0x9FH) WDTK (0xB7H) WDTC (0x9FH) TAKEY (0xF7H) 0x55H 0xAAH 0x5AH WDTKEY (0x97H) 0x1EH 0xE1H WDTC 0xE1H 0x1EH WDTC 3. SM39R4051 SM a. SM39R4051 Mnemonic: WDTC Address: B6h WDTF - WDTE - WDTM [3:0] 04H WDTF: Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by software or external reset or power on reset. WDTE: Control bit used to enable Watchdog timer. The WDTE bit can be used only if WDTEN is 0. If the WDTEN bit is 0, then WDT can be disabled / enabled by the WDTE bit. 0: Disable WDT. 1: Enable WDT. The WDTE bit is not used if WDTEN is 1. That is, if the WDTEN bit is 1, WDT is always disabled no matter what the WDTE bit status is. The WDTE bit can be read and written. WDTM [3:0]: WDT clock source divider bit. Please see below table to reference the WDT time-out period. ISSFA-0xxx 5 Ver. A 2010/07

6 Mnemonic: WDTK Address: B7h WDTK[7:0] 00h WDTK: Watchdog timer refresh key. A programmer must write 0x55 into WDTK register, and then the watchdog timer will be cleared to zero. Mnemonic: TAKEY Address: F7h TAKEY [7:0] 00H ISP ICP MOV TAKEY, #55h MOV TAKEY, #0AAh MOV TAKEY, #5Ah ; WDTC. MOV WDTC, #28h ; MOV WDTK, #55h ;. WDTM [3:0] Divider (250 KHz RC oscillator in) Time 250KHz ms ms ms ms ms (default) ms ms ms ms ms s s s s s s ISSFA-0xxx 6 Ver. A 2010/07

7 b. SM Mnemonic: WDTKEY Address: 97h WDT KEY7 WDT KEY6 WDT KEY5 WDT KEY4 WDT KEY3 WDT KEY2 WDT KEY1 WDT KEY0 00H By default, the WDTC is read only. User needs to write values 1EH, 0E1H sequentially to the WDTKEY (97H) register to enable the WDTC write attribute, which is MOV WDTKEY, # 01EH MOV WDTKEY, # 0E1H When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY (97H) register to disable the WDTC write attribute, That is MOV WDTKEY, # 0E1H MOV WDTKEY, # 01EH Mnemonic: WDTC Address: 9Fh WDTE CLEAR PS2 PS1 PS0 04H WDTE: Watch Dog Timer enable bit CLEAR: Watch Dog Timer reset bit If CLEAR bit set to1, Watch Dog Timer will be reset. User don t reset value to 0 PS[2:0]: Overflow period select bits PS [2:0] Overflow Period (ms) ISSFA-0xxx 7 Ver. A 2010/07

8 1. SM39R4051 SM SM39R4051 7SM SM SM39R4051 SM IE0 External interrupt 0 0x03H 0x03H TF0 Timer 0 interrupt 0x0BH 0x0BH IE1 External interrupt 1 0x13H 0x13H TF1 Timer 1 interrupt 0x1BH 0x1BH RI0/TI0 Serial channel 0 interrupt 0x23H 0x23H LVIIF Low Voltage Interrupt 0x63H IICIF IIC interrupt 0x6BH 2. SM39R4051 SM SM39R4051 SM IEN0 (0xA8H) IE (0xA8H) 1 IEN1 (0xB8H) 0 IP0 (0xA9H) IP (0xB8H) 1 IP1 (0xB9H) 3. SM39R4051 SM a. SM39R4051 Mnemonic: IEN0 Address: A8h EA - - ES0 ET1 EX1 ET0 EX0 00h EA: EA=0 Disable all interrupt. EA=1 Enable all interrupt. ES0: ES0=0 Disable Serial channel 0 interrupt. ES0=1 Enable Serial channel 0 interrupt. ET1: ET1=0 Disable Timer 1 overflow interrupt. ET1=1 Enable Timer 1 overflow interrupt. EX1: EX1=0 Disable external interrupt 1. EX1=1 Enable external interrupt 1. ET0: ET0=0 Disable Timer 0 overflow interrupt. ET0=1 Enable Timer 0 overflow interrupt. EX0: EX0=0 Disable external interrupt 0. ISSFA-0xxx 8 Ver. A 2010/07

9 EX0=1 Enable external interrupt 0. Mnemonic: IEN1 Address: B8h EXEN2 - IEIIC IELVI h EXEN2: Timer 2 reload interrupt enable. EXEN2 = 0 Disable Timer 2 external reload interrupt. EXEN2 = 1 Enable Timer 2 external reload interrupt. IEIIC: IIC interrupt enable. IEIICS = 0 Disable IIC interrupt. IEIICS = 1 Enable IIC interrupt. IELVI: LVI interrupt enable. IELVI = 0 Disable LVI interrupt. IELVI = 1 Enable LVI interrupt. Mnemonic: IP0 Address: A9h - - IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 00h Mnemonic: IP1 Address: B9h - - IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 00h SM39R4051 Priority levels IP1.x IP0.x Priority Level 0 0 Level0 (lowest) 0 1 Level1 1 0 Level2 1 1 Level3 (highest) SM39R4051 Groups of priority Bit Group IP1.0, IP0.0 External interrupt 0 IP1.1, IP0.1 Timer 0 interrupt IP1.2, IP0.2 External interrupt 1 IP1.3, IP0.3 Timer 1 interrupt IP1.4, IP0.4 Serial channel 0 interrupt LVI interrupt IP1.5, IP0.5 IIC interrupt ISSFA-0xxx 9 Ver. A 2010/07

10 SM39R4051 Polling sequence Interrupt source External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt LVI interrupt IIC interrupt Sequence sequence Polling b. SM Mnemonic: IE Address: A8h EA - - ES0 ET1 EX1 ET0 EX0 00h EA: EA=0 Disable all interrupt. EA=1 Enable all interrupt. ES0: ES0=0 Disable Serial channel 0 interrupt. ES0=1 Enable Serial channel 0 interrupt. ET1: ET1=0 Disable Timer 1 overflow interrupt. ET1=1 Enable Timer 1 overflow interrupt. EX1: EX1=0 Disable external interrupt 1. EX1=1 Enable external interrupt 1. ET0: ET0=0 Disable Timer 0 overflow interrupt. ET0=1 Enable Timer 0 overflow interrupt. EX0: EX0=0 Disable external interrupt 0. EX0=1 Enable external interrupt 0. Mnemonic: IP Address: B8h PS0 PT1 PX1 PT0 PX0 00h PS0: This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level. PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level. ISSFA-0xxx 10 Ver. A 2010/07

11 SM Priority structure of interrupts Source Flag Priority Level External Interrupt 0 IE0 1(Highest) Timer 0 Overflow TF0 2 External Interrupt 1 IE1 3 Timer 1 Overflow TF1 4 Serial Port RI+TI 5 ISSFA-0xxx 11 Ver. A 2010/07

12 SM39R GPIO Mnemonic: AUX Address: 91h BRS - - PTS[1:0] PINTS[1:0] DPS 00H SM39R4051 INT0 and INT1 pins PINTS [1:0] INT0 INT1 0x00 P3.2 P3.3 0x01 P3.0 P3.1 0x10 P1.4 P1.5 0x11 P3.2 P3.3 SM39R4051 T0 and T1 pins PTS [1:0] T0 T1 0x00 P3.4 P3.5 0x01 P3.0 P3.1 0x10 P1.4 P1.5 0x11 P1.2 P1.3 ResetRESET Pin P3.6 RC XTAL2 XTAL1 pin P4.0 P4.1 GPIO 4quasi-bidirectional (standard 8051 port outputs) push-pull open drain and input-only 2. Reset a. Reset on-chip hardware RESET duration 25ms (default) 200ms 100ms 50ms 16ms 8ms 4ms 2ms ISSFA-0xxx 12 Ver. A 2010/07

13 b. Reset Mnemonic: TAKEY Address: F7H TAKEY [7:0] 00H Software reset register (SWRES) is read-only by default; software must write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the SWRES register write attribute. That is: MOV TAKEY, #55h MOV TAKEY, #0AAh MOV TAKEY, #5Ah Mnemonic: SWRES Address: E7H SWRES [7:0] 00H SWRES [7:0]: Software reset register bit. These 8-bit is self-reset at the end of the reset procedure. SWRES [7:0] = FFh, software reset. SWRES [7:0] = 00h ~ FEh, MCU no action. 3. Crystal RC Clock source external crystal (use XTAL1 and XTAL2 pins ) external crystal (only use XTAL1, the XTAL2 define as I/O) 24MHz from on-chip RC-Oscillator 20MHz from on-chip RC-Oscillator 16MHz from on-chip RC-Oscillator 12MHz from on-chip RC-Oscillator 8MHz from on-chip RC-Oscillator 4MHz from on-chip RC-Oscillator 2MHz from on-chip RC-Oscillator 1MHz from on-chip RC-Oscillator 4. Mnemonic: DPL1 Address: 84h DPL1 [7:0] 00h DPL1[7:0]: Data pointer Low 1 Mnemonic: DPH1 Address: 85h DPH1 [7:0] 00h ISSFA-0xxx 13 Ver. A 2010/07

14 DPH1[7:0]: Data pointer High 1 Mnemonic: AUX Address: 91h BRS - - PTS[1:0] PINTS[1:0] DPS 00H DPS: Data Pointer selects register. DPS = 1 is selected DPTR1. 5. ISP/IAP/ICP EEPROM Mnemonic: IFCON Address: 8FH - CDPR - F2K ISPE 00H Software must be set ISPE bit to 1 to enable Below 4 registers write attribute. Mnemonic: ISPFAH Address: E1H ISPFAH3 ISPFAH2 ISPFAH1 ISPFAH0 FFH Mnemonic: ISPFAL Address: E2H ISPFAL7 ISPFAL6 ISPFAL5 ISPFAL4 ISPFAL3 ISPFAL2 ISPFAL1 ISPFAL0 FFH Mnemonic: ISPFD Address: E3H ISPFD7 ISPFD6 ISPFD5 ISPFD4 ISPFD3 ISPFD2 ISPFD1 ISPFD0 FFH Mnemonic: ISPFC Address: E4H EMF1 EMF2 EMF3 EMF4 - ISPF[2] ISPF[1] ISPF[0] 00H 6. IIC ISSFA-0xxx 14 Ver. A 2010/07

8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT89S52

8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT89S52 Features Compatible with MCS -51 Products 8K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 10,000 Write/Erase Cycles 4.0V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz