Dynamic List-Scheduling with Finite Resources

Transcription

1 Dynamic List-Schduling with Finit Rsourcs R.ay A. Kamin I11 Gorg B. Adams I11 Pradp K. Duby Rockwll Intrnational Purdu Univrsity IBM, T.. Watson Rsarch Cntr Collins Commrcial Avionics 125 Elctrical Enginring P.O. Box 70 Cdar Rapids, IA 529 Wst Lafaytt, IN Yorktown Hights, NY com Abstract Whn th instruction lvl paralllism xcds th availabl machin paralllism, a dcision must b mad as to which instructions gt priority. This papr invstigat,s th prformanc potntial of fiv dynamic schduling algorithms to prioritiz instructions byond basic blocks, thrby incrasing procssor utilization and prformanc. Trac-drivn simulations for six bnchmarks ar usd to analyz schduling prformanc. A uniqu piplining approach is introducd to addrss implmntation 1imita.tions. Kywords: dynamic schduling, instruction window, list schduling, suprscalar. 1 Introduction Highr lvls of intgration provid procssor dsignrs with additional rsourcs to dvot to xploiting instruction-lvl paralllism (ILP). Th currnt trnd for utilization of ths rsourcs is from singl-issu procssors to multipl-issu or suprscalar procssors. In ordr to raliz an accptabl cost/prformanc ratio, th amount of machin paralllism sliould balanc with th amount of ILP. Tchniqus such as loop unrolling, rgistr rnaming, and softwar piplining can b usd to incras ILP. Howvr, whn th amount of ILP xcds th machin paralllism, prforinanc is limitd by th hardwar. In this cas, instructions availabl for xcution must b prioritizd. Existing machins with dynamic instruction schduling capability us th ordr from th static instruction stram [9,, 5, 11. This approach rlis on a good static schdul producd by th compilr. Lack of hard war configuration informat,ion and run-tim information can rsult in undrutilizd rsourcs. In this papr, w analyz altrnativ dynamic schduling policis and thir ffct on prformanc. Th following sction outlins prvious work in instruction schduling. Sction 2 dscribs th dynamic schduling algorithms analyzd. Sction 3 prsnts th rsults of th simulation runs for both largr scop of concurrncy dtction and comparing diffrnt dynamic schduling algorithms. An outlin of implmntation issus to considr is in Sction and Sction 5 provids concluding rmarks. 2 Schduling Algorithms Schduling is th task of rordring th original instruction squnc, without violating any data dpndnc constraints, to improv th instruction xcution rat. This schduling can ithr b don at compil tim, static schduling, at run tim, dyaamic schduling, or a combination of both. Static schduling rangs from simply filling branchdlay slots and avoiding piplin stalls within basic blocks to mor xtnsiv byond-basic-block t,chniqus such as trac schduling [] and hardwar assistd tchniqus such as boosting [7]. Dynamic schduling, which may significantly incras hardwar complxity and cost, utilizs additional information unavailabl at compil tim. For xampl, loop bounds and mmory addrsss can b dtrmind xactly at run-tim whras a compilr must mak consrvativ dcisions to nsur program corrctnss. Dynamic schduling also offrs binary compatibility with xisting softwar, fastr compil tim, and lss ffort ndd in compilr gnration. As a cavat, particular attntion must b paid to th complxity of th dsign so as not to lngthn th procssor cycl tim and potntially nullify th prformanc gains of dynamic schduling. In th absnc of rsourc conflicts, an optimal schdul can asily b producd by xcuting instructions as soon as th data dpndncs ar satisfid. Howvr, dtrmining th optimal schdul for a procssor with finit rsourcs is significantly mor complx. Tradoffs must b mad btwn th complxity of th schduling algorithm and th quality of th schdul producd. Th schduling algorithms undr considration in this work ar list schduling algorithms. In list schduling, all th instructions availabl for xcution in th nxt tim stp (i.., rady instructions) $ IEEE 10

2 a.r ordrd using a local priority function. Ths algorithms do not prform any backtracking, that is, onc an instruction is schduld th dcision is nvr rvrsd. W considr: FCFS - First-com-first-srvd xcuts instruction in th sam ordr as thy bcom rady. This rducs implmntation complxity, howvr, it rlis on th quality of th compilr-producd instruction squnc. RAND - Th random algorithm arbitrarily slcts rady instructions from th window. FAN - Th fanout algorithm givs priority to thos instructions in th window with th highst numbr of dirctly dpndnt instructions. ALAP - Th as-lat-as-possibl algorithm givs priority to instructions on th longst xcution path prsnt within th window (i.., th critical path). Eithr cycl counts or instruction counts may b usd to masur th critical path lngth. W usd cycl counts. Whn multipl inst,ructions ar on th critical path, ALAP chooss th oldst instruction bo schdul. Instructions off th critical path ar schduld FCFS. VDLS - Varianc-dirctd list schduling, introducd in this work, attmpts to balanc th utilization of t,h function units for ach tim stp by niiniinizing th varianc of th funct,ion unit utilization probabilitis. S [6] for a dtaild dscription. Th tim complxity of VDLS prohibits its us for dynamic schduling. It is includd t,o provid a rfrnc point for assssing th ffctivnss of othr algorithms. Simulation Rsults Bnchmarks To st,udy th ffct of incrasd window siz and sophist.icatd dynamic schduling mchanisms, w usd our instruction-lvl simulator, Spam [6], to analyz six bnchmarks: th Unix utilitis comprss, crypt, and nroff, th first pass of th GNU C compilr, a floating point quantum chmistry application, and a vctorizd msh-gnration application. Th bnchmarks wr compild with th GNU gcc compilr and th Sun bundld Fortran compilr, f77, undr SunOS Machin Configurations Th six bnchmarks wr simulatd with ach of th fiv schduling algorithms, a rang of window sizs, and svral machin configurations. Th machin configurations invstigatd rang from a singl-issu procssor, Bas, to an ovrly optimistic multipl issu procssor, Opt. Ths modls ar usd to stablish bounding prformanc masurs for valuating th othr thr machin modls, Mach-1, Mach-2, and Mach-3. Th configurations of all fiv modls ar listd in Tabl 1. Machin modls that prform branch prdiction allow xcution of instructions byond th currnt basic block (i.. spculativ xcution is usd). Thr ar fiv typs of xcution units and ach ar assumd to oprat in paralll with th othrs. Many of th Cyprss Smiconductor floating point latncis [3] ar consrvativ, givn th now currnt implmntations of this architctur such as th SuprSPARC chip from Txas Instrumnts [2]. 3.3 A Prformanc Baslin Th scop of concurrncy dtction is dfind by th numbr of instructions xamind simultanously for dpndnc dtction. Som suprscalar procssors issu instructions in-ordr. Thrfor, onc a dpndnc is dtctd, th issu piplin stalls. Consquntly, th scop of concurrncy dtction is vry limitd. With th hlp of optimizing compilrs, many applications contain nough paralllism to issu two instructions pr clock cycl. By maintaining a buffr, or window, of instructions btwn th issu and xcut stags of th piplin, data and rsourc dpndncs nd not stall th piplin. Instructions may b issud out-of-ordr from this window whn thir data dpndncs ar satisfid and an xcution unit is availabl. Th siz of th instruction window dtrmins th scop of concurrncy dtction. Th siz of th window should b balancd with th machin-lvl paralllism and th instruction-lvl paralllism. Bfor comparing th prformanc of th dynamic schduling algorithms, w first look at FCFS schduling with th fiv machin configurations and diffrnt window sizs. As shown in Tabl 2 for th comprss bnchmark, vn th ambitious Mach-3 modl dos not achiv significant prformanc gains. Th Opt machin modl valu for instructions issud pr clock cycl (IPC) is almost 3.5, indicating that thr is considrabl untappd instruction-lvl paralllism. Tabl 3 shows why. For comprss th branch prdiction succss rat is 1.3 prcnt for Mach-2 with a window siz of instructions. Additionally, th data cach hit rat is only 3. prcnt whil th instruction cach hit rat is prcnt. Th rlativly low branch prdiction succss rat coupld with a basic block siz of.63 instructions indicats that th piplins must b oftn flushd of incorrctly ftchd instructions. Similarly, th data cach has troubl srvicing load instruction rqusts at a sufficint rat. In contrast, th crypt bnchmark shows significant prformanc gains with incrass in scop and 1 1

3 Tabl 1: Machin Configurations At,tribut Bas Mach-1 M ach-2 Instruction Latncis SPARC* SPARC* SPARC* Maximum Ftch Width 1 Maximum Dcod Width 1 Window Siz 1 Numbr of ALUs Numbr of FPUs Nunibr of Shift/Logical ot 1 1 Numbr of Load/Stor 1 2 ot ot Numbr of Branch units Rgistr R.naming Mmory Disambiguation Out-of-ordr issu Branch Prdiction non l-bit > 5 2-bit Branch Tabl Siz n/a 1K 2K I-Cach Siz/D-Cach Siz Associativity Block Siz Ftch Policy Writ Policy Miss Pnalty $ M ach-3 Opt SPARC* SPARC* > 2-bit 2K Cach Configuration Kbyts/l6 Kbyts dirct byts miss prftch, 1 block copy-back, writ-allocat 10 cycls 00 prfct n/a Tabl 2: Instructions issud pr clock cycl for FCFS schduling Machin Mach- 1 Mach-2 Mach-3 Window Siz 1 6 comprss Bnchmark crypi gcc nroo fpppp tomcatv I 12

4 Tabl 3: Simulation masurmnts for six bnchmarks using th Mach-2 modl with a window siz of Attribut Dynamic Instruction Count Avrag Basic Block Siz Maximum Basic Block Siz Branch Prdiction Succss Branchs Takn Floating Point Instructions Intgr instructions Shift/Log Instructions Load/Stor Instructions Branch Instructions Prcnt of all cycls in which 0 instructions issud 1 instruction issud 2 instructions issud 3 instructions issud instructions issud 5 instructions issud 6 instructions issud I-cach Hit R.at D-cach Hit Rat Maximum Rordr Buffr Siz comprss 1M % 1.1% 25.% 31.5% 2.6% 1.6% 39.9% 20.% 23.% 9.9% 5.0% 0.5% 99.99% 3.% 102 crypt 11M % 0.9% 2.3% 35.% 25.7% 1.2% 3.0% 33.7% 3.6% 1.5%.3% 5.9% 99.92% 99.22% 111 Bnchmark qcc 222M % 5.% 2.6% 26.6% 27.3% 17.5% 3.6% 2.6% 1.3%.9% 3.% 0.7% 95.% 93.51% M % 5.11% 00% 27.6% 36.2% 1.0% 1.3% 20.3% 21.0% 3 1.5% 7.2% 2.% 9.9% 9.1% 109 fpppp 12M tomcatv 26M % 9.90% 5.21% 9.96% 3nT TiiT.3% 21.0% 5.%.0% 51.2% 1.% 1.% 2.% 5.6% 27.6% 1.5% 6.7% 1.5% 91.95% 9.93% % 30.7%.% 7.% 2.% 99.99% 7.96% 12 incrass in machin rsourcs (s Tabl 2). Tabl 3 show a branch prdiction succss rat of 9.3 prcnt and a data cach hit rat abov 99 prcnt, allowing th hardwar to ffctivly xtract th availabl ILP. It is intrsting to not th poor ovrall prformanc of qcc. Evn th Opt machin modl achivs an IPC of only This is du to th i-cach hit rat of only 95 prcnt. Simulating qcc with prfct cachs yilds an imprssiv 6.2 instructions pr clock. 3. Dynamic Schduling Having stablishd th baslin prformanc of th FCFS schduling algorithm, w comput th spdup of th othr four dynamic schduling algorithms with rspct to FCFS. To masur th spdup, th simulations wr rpatd for th sam bnchmarks and machin configurations with ach of th fiv schduling algorithms. Th spdup is computd with rspct to FCFS with th sam machin configuration, bnchmark, and window siz. Bcaus ach group of four bars is indpndntly normalizd to FCFS with th sam group attributs, dirct comparison cannot b mad btwn groups. As th window siz incrass within a machin configuration, th ALAP, VDLS, and FAN algorithms tnd to improv with rspct to FCFS. With a largr window siz of instructions, ths algorithms hav mor information about th critical path and thrfor ar abl to schdul instructions mor fficintly. As th amount of machin paralllism xcds th amount of instruction-lvl paralllism, most of th instructions rady for xcution will hav availabl function units. Consquntly, ths instructions will b issud in th currnt cycl making th computd instruction prioritis irrlvant. This ffct is vidnt from th small diffrnc in prformanc btwn th fiv schduling algorithms for th Mach-3 machin modl (s Figur 1). Th rmaining four bnchmarks xhibit similar trnds and charactristics to th comprss bnchmark. Howvr, th prformanc of th schduling algorithms is within fiv prcnt of FCFS. Spac limitations prvnt showing figurs for ths bnchmarks, s [6]. Implmntation Issus Both larg instruction windows and th complx dynamic schduling algorithms ar not fasibl for schduling instructions within a singl cycl. A mthod to xtnd fasibility is to prdtrmin th instruction schdul for svral cycls. In turn, this allows th schdulr svral cycls to analyz th instructions in th window. This tim can b usd 13

5 ~ ~~ to valuat mor complx dynamic schduling algoritlinis or to considr a largr scop of concurrncy..w call a suprscalar procssor that allows multipl cycls for dcod and schduling a hyprscalar procssor. In a suprscalar procssor, th dcod stag of th piplin must dcod nw instructions, ft,ch oprands from th rgistr fil and/or rordr buffr, chck for dpndncs and rsourc conflicts, and issu rady instructions to th function units. Th hyprscalar procssor distributs ths tasks ovr svral cvcls. Sinc th function unit hardwar has b; rplicatd, th cycl tim for th xcution phas of th hyprscalar piplin is uncliangd. 5 Summary A prformanc gain of th dynamic schduling algorit,hms with rspct, to first-com, first-srvd schduling (FCFS) rlis on two factors. First, th scop must b larg nough to rval nough inforinatmion to mak a bttr schduling dcision than FCFS. Scond, th amount of machin paralllism must b lss than th amount of instruction-lvl paralllisni. If not, it is suprfluous to assign prioritis to tli instructions if all rady instructions hav availabl function units. As w hav shown, if ithr of ths conditions is not satisfid, th prformanc gain of ths dynamic schduling algorithms will b minimal. In fact, th complxity of th schduling hardwar may actually dgrad prformanc. Th bst prformanc gains wr from ALAP and VDLS, but in most cass th prformanc was within fiv prcnt of FCFS schduling. Thus, th compilr-gnratd squnc is adquat for of schduling th instructions. It is also important to not that th instruction squncs analyzd in this work wr gnratd by compilrs without any attmpt to optimiz th cod for a suprscalar targt procssor. W conclud that ffort should b focusd on static schduling using rsourc information about th targt procssor coupld with a constant tim complxity dynamic schduling mchanism, such as FCFS and RAND, to rsolv additional conflicts at run-tim. Th hyprscalar piplin implmntation introducd hr may mak implmntation of ths largr windows and/or complx algorithms fasibl. Rfrncs [I] R. Acosta,. Kjlstrup, and H. Torng. An Instruction Issuing Approach to Enhancing Prformanc in Multipl Functional Unit Procssors. IEEE Trans. Com&rs, C-35(9):15-2, Spt [2] G. Blanck and S. Krugr. Th SuprSPARC Microprocssor. In 37th IEEE COMPCON, pags , [3] Cyprss Smiconductor. SPA RC RISC Usr s Gund, 2nd dition, []. Fishr. Trac Schduling: A Tchniqu for Global Microcod Compaction. IEEE Trans. Computrs, C-30( 7):7-90, uly 191. [5] R. Horst, R. Harris, and R. ardin. Multipl Instruction Issu in th Nonstop Cyclon Procssor. In 17th Int? Symp. Computr Architctur, pags 2-226, un [6] R. Kamin 111. Dynamic Trac Analysisfor Prformanc Evaluation of Suprscalar Procssors. PhD thsis, Purdu Univrsity, [7] M. Smith, M. Horowita, and M. Lam. Efficint Suptscalar Prformanc Through Boosting. In Procdings of th Fifth Conf. Arch. Support for Prog. Lung. and Oprating Sys., pags 2-259, Oct []. Thornton. Dsign of a Computr: Th Control Data Scott, Forman and Co., [9] R. Tomasulo. An Efficint Algorithm for Expoiting Multipl Arithmtic Units. IBM. Rs. and Dw., 11(1):25-33, an Normallzd prformanc of conprss R - RANDOM flmrh-l Fi.FANQ!T.....,.U M%h:2... A -AUP 1 MMrh-3 1.IO...\I-.YsILS... I.05 I.oo R -RANDOM Mrb- I 1,IS......I R P 2.m......,.,..~ hkb:2... mmrh V -VDU I.oo RFAV RFAV RFAV RFAV RFAV RFAV RFAV RfAV RFAV 0 6 Window Siz and Schduling Algorithm Figur 1: Spdup of comprss undr diffrnt schduling policis and machin configurations, with rspct to FCFS Figur 2: Spdup of fpppp undr diffrnt schduling policis and machin configurations, with rspct to FCFS 1