ANALOG MICROELECTRONICS ( A)
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1 ANALOG MICROELECTRONICS ( A) IBM 130 nm CMOS Technology An Introduction to Cadence Virtuoso Layout Tool and the Analog Simulation Environment Prepared By - Azhar A. Chowdhury Updated by Ming Yang CMOS PROCESS Step 1 The first step always is creating the schematic. Then we can perform the layout. Create the schematic of an inverter as per tutorial 1.
2 Figure 1: Schematic of an inverter Step 2: Create the Layout a. In icfb File --> New --> Cell View Tool : Virtuoso Click ok and Layout Editor will open with LSW b. In the layout Editor Options --> Display Set the following parameter: Minor Spacing: 0.01 Major Spacing: 0.1 X Snap Spacing: 0.01 Y Snap Spacing: 0.01 The unit here is in µm, and 0.01µm is the highest precision IBM.13 technology can have.
3 From Display Controls, select 'Pin Names' Display Levels, Start --> 0, Stop --> 20 option --> Layout Editor Set Aperture: You may also want to uncheck the Gravity On box to prevent components snipping together during the layout. c. In the layout editor, you can start the layout. There are two different ways to complete the layout design. Method 1 (traditional approach): In the layout window Create --> Instance (Shortcut i)
4 Place the component in the layout window, Now select the instance and press (Shift + q) for "Edit Instance Properties" Set the length, width, number of fingers according to your design. Select the "Connect S/D/G terminals" *for pmos make sure to select "Add NW contact" Complete the layout similarly, and route the wire accordingly. To put down a wire, select the LSW window and click on the material you would like to use (for example M1 drw means drawing with metal 1), and then use path (W) or rectangular (R) tool to draw. After the layout it should look like this
5 add metal 1 pins to specify input and output nodes 1) select metal1-pn in the LSW window 2) Create -> Pin... 3) give the terminal a name, e.g. VDD 4) select Shape Pin next to Mode (and select rectangle) 5) select Display Pin Name 6) select inputoutput/input/output next to I/O type 7) on the layout, draw a rectangle on the layer to be labelled (metal 1 in this case) and place the text label beside the pin - create four pins in total: VDD, vin, vout and VSS. Method 2 (by layout XL): Layout XL is a function integrated in Cadence that helps the designer to generate all the schematic components (transistors, resistors, pins etc., but except wire) directly from a schematic design. It also tells the designer how to connect components together. Getting familiar with this function can greatly reduce the layout time for a fairly complicated circuit. To invoke Layout XL and generate all components from schematic design: (1) Close your current Virtuoso Layout Editor window (2) In Virtuoso Schematic Editing window, select Tools-->Design Synthesis-->Layout XL (3) Select open existing and locate the file if your layout file has been created before (4) If everything works out correctly, Virtuoso XL Layout Editor window will pop up (5) In this window, select Design-->Gen From Sources (6) Within I/O Pins section, select the material for pins, here we use M1 pn for the layer,
6 then click apply to apply this setup to all pins (7) Click Ok to generate components from schematics Now all the components in your schematic design should be placed into the layout editor, move them into the design area (green box defined by layer prbound). The last step is to route the wire according to the schematic design. When drawing a wire or a rectangular on top of a component, the Layout XL Editor will tell you how it should be connected. For example, when drawing a metal 1 rectangular on the drain of the pfet, the editor will highlight all the places that should be connected together. After the layout it should look similar to the result produced by method 1. The only difference is that the label on top of each pin (in white) does not exist since the pins are automatically generated by the program without any label.
7 Step 3 : Calibre DRC To do a DRC, Layout -> IBM_PDK -> Checking -> Calibre -> DRC Select "Default Runset" from the pop-up. The Environment Variables Setup form will be set at defaults, change: BEOL_STACK = 3_2_3 TECHDIR = /CMC/kits/cmosp13.V DM/IBM_PDK/cmrf8sf/V DM/Calibre/ DENSITY_LOCAL = OFF DESIGN_TYPE = CELL This creates a runset file and opens the Calibre Interactive window. Select a directory below your working directory for the DRC Run Directory (eg. mkdir drc) and then save runset with File - > Save Runset as. The default name of the runset is "ibmpdkdrc.runset1", simply provide the path information. Your working directory is a good place to keep this runset file. The DRC rules, if not automatically filled in, is: /CMC/kits/cmosp13.V DM/IBM_PDK/cmrf8sf/V DM/Calibre/ DRC/cmrf8sf.drc.cal Finally, press the Run DRC button to get your results. After the DRC is complete DRC RVE window will show up with the results. See figure below:
8 If no error then it should look like the figure above. Error will also show up and you can see the reasons for the error. Step 4: Assura LVS To do LVS, Layout -> Assura ->Run LVS Schematic Design Source - DFII Then click Browse on Schematic Design Source to select your schematic from the your library The following Extract Rules, Compare Rules, Binding Files & RSF Include files should be in the form. /CMC/kits/cmosp13.V DM/IBM_PDK/cmrf8sf/V DM/Assura/QRC/32/extract.rul /CMC/kits/cmosp13.V DM/IBM_PDK/cmrf8sf/V DM/Assura/QRC/32/compare.cdl /CMC/kits/cmosp13.V DM/IBM_PDK/cmrf8sf/V DM/Assura/QRC/32/bind.cdl /CMC/kits/cmosp13.V DM/IBM_PDK/cmrf8sf/V DM/Assura/QRC/32/LVSinclude.rsf
9 Click ok to run the LVS and wait until the report appears The following window will appear with all the errors. Click yes If you have any error then the LVS Debug will show all the errors and a description.
10 Step 5: Assura QRC To do QRC, Then, Layout -> Assura ->Run QRC In the Extraction tab Extraction Type - RC Ref Node - /VSS Cap Coupling Mode - Coupling
11 In the Setup tab Setup Dir - /CMC/kits/cmosp13.V DM/IBM_PDK/cmrf8sf/V DM/Assura/QRC/32 Output - Extracted View After Successful QRC following window will show up
12 Step 6 - Simulation with the Extracted layout Open the schematics of the circuit test bed. Go to Analog Environment. Setup -> Environment Switch View List -> Write av_extracted before schematic Now you can run your simulation. If you go down in Hierarchy in your test bed circuit, it will take you to extracted view.
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