Tanner Analog Front End Flow. Student Workbook

Transcription

1 Student Workbook 2016 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject to license terms. No part of this document may be photocopied, reproduced, translated, distributed, disclosed or provided to third parties without the prior written consent of Mentor Graphics.

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3 Module 1: Introduction to Tanner Front-End Flow Objectives Course Schedule Course Objectives Analog Implementation Process What Is a Design Project? Tanner Analog IC Design: Front-End Flow Tanner Analog IC Design Features Typical Project Structure Libraries Cells: Overview Hierarchical Designs SPICE Netlists Process Design Kits Tanner Analog IC Design: Front-End Flow Starting Up Tanner Tools Accessing Help Setup Examples Example Design Outline Lab Exercise Module 2: Introduction to Tanner S-Edit Objectives Course Schedule Design Flow I

4 Tanner S-Edit Interface Tanner S-Edit User Interface Tanner S-Edit User Interface Window/Toolbars Positioning Window Positioning Command Window User Interface Customization Creating and Editing Toolbars Creating and Editing Menus Keyboard Shortcuts Tanner S-Edit Designs Creating New Designs Tanner S-Edit Project Data Structure Opening Existing Designs Library Navigator Exclusivity And Editing Protection Library Referencing Library Navigator Cell Navigation The Hierarchy Navigator Tanner S-Edit Settings Tanner S-Edit Settings Technology Settings Schematic Colors Technology Settings Schematic Grids Technology Settings Schematic Units Technology Settings Schematic Page II

5 Technology Settings Protection Preferences General Preferences Mouse Preferences Selection Preferences Text Editor Preferences Text Styles Saving/Loading Settings Additional Resources Lab Exercise Module 3: Schematic Entry in Tanner S-Edit Objectives Course Schedule Design Flow Basic Cell Operations Cell/View Operations Overview Creating New Cells Creating New Schematics Opening Cell Views Traversing Cell Views Cell Instantiation Instance Properties Properties Navigator Query and Editable Sub-properties Instance Arrays Design Area III

6 Design Area Elements Display Area View Options Design Area Default Controls View Mouse Buttons Toolbar Splitting a Schematic Into Multiple Pages Status Toolbar Locator Toolbar Design Tools Electrical Toolbar Drawing Wires Drawing Modes Net Labels Net Label Settings Buses Working With Buses And Vectors Soldering Point and Connect/Disconnect Net Caps Ports Editing Tools Selection and Editing Commands Rubber Banding Move By Edit In-Place Additional Tools and Features Accidental Connectivity Prevention IV

7 Net Highlighting Design Checking Design Checking Settings Snap To Grid Hierarchy Navigator Find And Replace Additional Resources Lab Exercise Module 4: Cell Operations in Tanner S-Edit Objectives Course Schedule Design Flow Creating Symbol Views Symbol Views Creating Symbol Views Procedure Creating Symbol Views New Symbol Creating Symbol Views Draw The Symbol Creating Symbol Views Add Ports Creating Symbol Views Add Properties Generating Symbols Automatically Cell Properties Property Types Property Data Types Property Values Property Value Evaluation V

8 Special Property Value Expressions Property Display Attributes Property Trees (Hierarchies) Service Sub-Properties Control Properties Creating Language Views Language Views Creating Language Views Language Design Checking Language Design Checking Settings Verilog-A Reference Manual Interface View of Language Views Symbols for Language Views Cell Operations Libraries Navigator Cells List Copying Cells Copying Views Renaming Cells Renaming Views Deleting Cells / Views Redirecting Instances Unresolved Instances Cells with Multiple Views Additional Resources Lab Exercise VI

9 Module 5: Capturing, Importing and Exporting Designs in Tanner S-Edit Objectives Course Schedule Design Flow Capturing Designs Capturing Designs Importing and Exporting Options Importing and Exporting Design Formats Importing EDIF Designs Exporting EDIF Designs Importing OpenAccess Importing and Exporting Language Formats Exporting SPICE Netlists Importing SPICE Files Importing Verilog Files Exporting Verilog Files Additional Resources Lab Exercise Module 6: Introduction to SPICE Simulation Objectives Course Schedule Design Flow Overview & General Setup Overview Simulation Types VII

10 Simulation Setup Setting Up Testbenches SPICE Simulation Setup General SPICE Simulation Setup Model Files and Libraries SPICE Simulation Setup Additional SPICE Commands SPICE Simulation Setup Parameters Running & Controlling Simulation SPICE Simulation Setup General Procedure Introduction to Tanner T-SPICE Tanner T-SPICE Interface Simulation Controls Running Tanner T-SPICE From the Command Line Simulation Manager Simulation Status Dialog Introduction to Tanner Waveform Viewer Tanner Waveform Viewer Interface Charts Window Features Default Keyboard and Mouse Shortcuts Draw Toolbar Chart books, Charts and Plots Controlling The Plot View Plot Operations Plot Properties Traces Navigator VIII

11 Waveform Comparison Dialog Application Preferences Application Preferences (Trace Styles) Command Window Additional Resources Lab Exercise Appendix A: T-SPICE Settings & Batch Simulations Batch Simulations Text Editor Simulation Settings Module 7: DC, AC and Noise Analysis Objectives Course Schedule Design Flow Simulation Types SPICE Libraries Waveform Probing Waveform Probing Procedure Small Signal Parameters Enabling Back Annotations General Notes / Rules DC Operating Point Analysis DC Operating Point Analysis DC Operating Point Analysis Procedure Contents of the.op File IX

12 Contents of Operating Point Results File DC Operating Point Analysis SPICE Command DC Sweep Analysis DC Sweep Analysis DC Sweep Analysis Procedure DC Sweep Analysis Example DC Sweep Analysis SPICE Command AC Analysis AC Analysis AC Analysis Procedure AC Analysis Example AC Analysis SPICE Command Noise Analysis Noise Analysis Noise Analysis Procedure Noise Analysis Print and Measurement Noise Analysis Example Noise Analysis SPICE Command Additional Resources Lab Exercise Module 8: Transient Analysis, Parametric Sweep and Temperature Sweep 307 Objectives Course Schedule Design Flow Simulation Types X

13 Transient Analysis Transient Analysis Transient Analysis Procedure Transient Analysis Example Transient Analysis SPICE Command Parameter Sweep Parameter Sweep Parameter Sweep Procedure Parameter Sweep Example Parameter Sweep SPICE Command Temperature Sweep Temperature Sweep Temperature Sweep Procedure Temperature Sweep Example Temperature Sweep SPICE Command Parameter List in Tanner Waveform Viewer Additional Resources Lab Exercise Module 9: Monte Carlo and Corner Simulations Objectives Course Schedule Design Flow Simulation Types Monte Carlo Analysis Monte Carlo Analysis XI

14 Monte Carlo Analysis Results Monte Carlo Analysis Prerequisites Monte Carlo Analysis Setup Monte Carlo Analysis Procedure Monte Carlo Analysis Example Histogram Chart Parameters Corner Simulations Corner Simulations Corner Simulations Setup Corner Simulations Example Corner Simulation Example Results Corner Simulations SPICE Command Additional Resources Lab Exercise Appendix A: Automation in Tanner S-Edit Objectives Course Schedule Design Flow Command Window Command Window Command Window Options Command Window Customization General Command Window Customization Filters Command Window Customization Folders Tcl/Tk Commands XII

15 Tcl/Tk Commands Help Creating & Editing Tcl/Tk Scripts Executing Tcl/Tk Scripts Sourcing Tcl/Tk Scripts Executing Tcl/Tk Scripts Automatically Callbacks Tcl Callbacks Protection Settings Evaluated Expressions Evaluated Expressions Evaluated Expressions & Control Properties Additional Resources Lab Exercise Appendix B: SPICE Netlisting Objectives Course Schedule Design Flow T-SPICE Fundamentals Basic T-SPICE Rules SPICE Options Supported Arithmetic Operators Supported Logical Operators Built-In Functions Device Statements Common Device Statements XIII

16 Subcircuits Subcircuit Device Statement Subcircuit Example Library & Include Files Defining Parameters & Functions Conditional Statements Compact Conditional Statement Simulation Options Accuracy vs. Speed DC Analysis Transient Analysis Tolerances Methods of Time Integration Common Simulation Problems Non-Convergence Errors Non-Convergence Checking Non-Convergence Solutions Trapezoidal Integration Failure Gear BDF Integration Failure Command Wizard Additional Resources Lab Exercise Appendix C: Verilog-A Behavioral Modeling Objectives Course Schedule XIV

17 Design Flow Verilog-A Simulation Verilog-A Modules Verilog-A Simulation Settings in Tanner S-Edit Verilog-A Settings in Tanner T-SPICE T-SPICE Commands to Include Verilog-A Models Instantiating Verilog-A Devices Simulating Verilog-A Models Procedure Additional Resources Lab Exercise XV