Memory Addressing. Pradipta De
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1 Memory Addressing Pradipta De
2 Today s Topic Allow processes (and kernel) to reliably access physical memory How to create illusions of large RAM Ensure memory protection Do not let other processes corrupt memory CSE506: Memory Addresing 2
3 Outline Processor Modes Segmentation Paging Advanced Features Extended Paging PAE (Physical Address Extension) Windows support CSE506: Memory Addresing 3
4 Addresses Logical Address specified as a <segment:offset> tuple Linear or virtual address A (20-bit) or 32 bit integer to address (1 MB) or upto 4 GB of RAM What if RAM > 4 GB? Physical address Address memory cells in memory chip Some useful facts: 32 bit (or 36-bit) address for 32 bit machines 64 bit address for 64 bit machines What is addressable memory? Theoretically 16 ExaByte Current: 48 bits i.e. 256TB (AMD64) and 42 bits i.e. 4 TB (Intel) CSE506: Memory Addresing 4
5 Different Modes Real Mode: uses real mode addressing Used at boot time CS << 4 + IP = Linear Address Of Instruction Segmentation (no paging) Protected Mode: hardware supported Switches by setting PE bit in CR0 register Paging available (80386 onwards) Privilege levels CSE506: Memory Addresing 5
6 Different Modes (contd) Long Mode: addressing in 64-bit mode not much different from 32 bit mode Linear addresses are now 64 bit 64-bit registers are available CSE506: Memory Addresing 6
7 Segmentation CSE506: Memory Addresing 7
8 Segmentation Hardware Logical address linear address Memory viewed as collection of segments Segment selector: chooses one of 8K segment descriptors Segment descriptor: provides segment base address CSE506: Memory Addresing 8
9 Segment Selector 13 bits: pointer to segment descriptor 1 bit: LDT/GDT 2 bits: privilege level Segment Selection Segment Descriptor Segment Base address Other control fields Limit: to check if the address exceeds the segment boundary used in memory protection One GDT, multiple LDTs (one for each process CSE506: Memory Addresing 9
10 Segment Descriptor CSE506: Memory Addresing 10
11 Segmentation in Linux Linux does not really use segmentation!! 4 segments user code, user data, kernel code and kernel data Table 2-3. Values of the Segment Descriptor fields for the four main Linux segments Segment Base G Limit S Type DPL D/B P user code 0x xfffff user data 0x xfffff kernel code 0x xfffff kernel data 0x xfffff CSE506: Memory Addresing 11
12 Paging Convert linear address to physical address CSE506: Memory Addresing 12
13 Regular Paging 10 bits: directory 10 bits: page table 1024 entries 12 bits: offset 4KB page Why 3 levels only? Saves memory for housekeeping CSE506: Memory Addresing 13
14 Translation Lookaside Buffers Cache: linear (virtual) address physical address Why cache? MMU takes time to translate Multiprocessor systems Each CPU has its own TLB When do we flush TLB? On context switch when cr3 register, that points to a page directory, is repopulated CSE506: Memory Addresing 14
15 Additional tricks (or hacks!!) Extended Paging Page frames > 4 KB it can be 4 MB Do not use a page table only page directory 1 level translation Saves the space for page table TLB entries are more long-lived CSE506: Memory Addresing 15
16 Additional tricks (or hacks!!) Physical address extension (PAE) Address RAM > 4 GB Soln: 4 extra pins for addressing, 36-bit address (64GB) Convert: 32 bit linear address to 36 bit physical address Page table entry: 24 bit (to address 2^24 page frames) + 12 bit (offset) Each PT entry is 64 bits total 512 PT entries CSE506: Memory Addresing 16
17 Advanced Features Moving on to 64 bit arch CSE506: Memory Addresing 17
18 64-bit addressing in Linux Lets review 3 level paging 4KB page 12 bit offset 48 bits virtual address in AMD64 (48-12)=36bits for PT and PD Using 18 bits, 2^18 entries in PT and PD Imagine the size of the PT and PD (per process!!) More levels are introduced ( ) CSE506: Memory Addresing 18
19 Linux: 64 bit paging Specify number of bits for each level to trigger different levels of paging CSE506: Memory Addresing 19
20 Windows: large memory support 4 GB Tuning Win 32 bit systems, allow user apps to use 2 GB virtual address space Feature to allow app use 3 GB system mem reduces to 1 GB On 64bit, it is 4 GB for app Large page support Allows apps to use large memory regions Specially useful for 64 bit Windows Fun Facts: memory limits for different WIN version CSE506: Memory Addresing 20
21 Putting It Together Early days Segmentation Evolution Paging Tricks to accommodate more memory Finally 64 bit arrived Linux uses Flat address mode ignores segmentation, uses paging for addressing, and memory protection Single data structure accommodates all hardware architectures CSE506: Memory Addresing 21
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