Using Synplify Pro, ISE and ModelSim

Transcription

1 Using Synplify Pro, ISE and ModelSim VLSI Systems on Chip ET4 351 Rene van Leuken Huib Lincklaen Arriëns Rev. 1.2 The EDA programs that will be used are: For RTL synthesis: Synplicity Synplify Pro For simulation: Modeltech Modelsim SE (XE behaves the same) For the back-end flow to FPGA: Xilinx ISE 6.3i The target FPGA is a Xilinx Spartan 3 (XC3V2000) on an AvNet Spartan-3 Development board. The programmer cable is a Xilinx Parallel IV Cable. It is connected between the parallel port of the PC and the FPGA board. The following steps will be described in the pages hereafter: RTL Synthesis Map, place, route and bit-file generation Programming the FPGA And although usually to be performed as a first step, we ll end with a description of using Modelsim. This tutorial is written with the Windows XP operating system in mind, so icons and menu lines may differ slightly when using a Linux environment. ET4 351 (May, 2005) Page 1 of 12

2 Xilinx Spartan -3 Development Kit The Spartan 3 Development Kit provides a platform for engineers designing with the Xilinx Spartan 3 FPGA. The board provides the necessary hardware to not only evaluate the features of the Spartan 3 but also to implement complete user applications. The following figure illustrates the placement of the jumpers to be installed on the development board to enable programming of the FPGA. Also shown is the push button that in the given vhd-files is assigned to be the Reset-button. the reset button for this project check the position of these 2 jumpers: they should be present to enable boundary-scan programming In your start-up directory, you will be given 3 files, e.g. testbrd_spartan3.vhd: the description of the circuitry to be synthesized testbrd_spartan3.ucf: the description of the FPGA pins to be used tb_tstbrd_sp3.vhd: a testbench for simulation ET4 351 (May, 2005) Page 2 of 12

3 Create a directory for your VHDL source files Create a directory vhdl in your home directory and copy the files: testbrd_spartan3.vhd and testbrd_spartan3.ucf (from /usr/local/msclab/et4351/labsession/) into this new directory. Synthesis Use Synplify Pro from Synplicity Start Synplify Pro, either by clicking on the icon on the desktop or by Start > All Programs > Synplicity > Synplify Pro First, we have to start a new project, which can be accomplished in the following way. From the top Menu toolbar choose: File > Build Project Navigate to the correct directory, select the testbrd_spartan3.vhd-file, click on < Add and confirm with OK. This is the only file needed for synthesis in our case. In the project s description, we have to supply information about which family and FPGA type the synthesizer should target. In the left column, select Impl Options and specify the following fields: Technology: Xilinx Spartan 3 Part: XC3S2000 Speed: -5 Package: FG676 confirm with OK ET4 351 (May, 2005) Page 3 of 12

4 Save the project s information by choosing from the top Menu toolbar: File > Save As and enter an appropriate name for the project. End with Save NB. The Xilinx software that we are going to use (Project Navigator) has the annoying property that it cannot handle pathnames or filenames with spaces in it, so, to avoid problems: never use a space character in a path or filename. To perform the synthesis, push the big Run button. Synplify Pro will translate the vhdl-file into components, modules and/or structures that specific to the target FPGA, and write this in a netlist file, called testbrd_spartan3.edf. Next to that, additional information is written to a number of other files. For instance, have a look at the at an RTL view by selecting HDL Analyst > RTL > Hierarchical View from the Menu toolbar. or by pressing the short-cut icon. If the synthesis has successfully finished, it will be possible to start the next program, i.e. the Xilinx design tools, from inside Synplify Pro. This has the advantage that the project s target information will be automatically passed to the Xilinx tools. From the top Menu toolbar choose: Options > Xilinx > Start ISE Project Navigator ET4 351 (May, 2005) Page 4 of 12

5 Xilinx Map, Place & Route and Bit-file Generation Check that the testbrd_spartan3 (testbrd_spartan3.edf) file is shown in the panel on the screen. The next step is to provide the project navigator with additional information about how the FPGA is physically connected to the other hardware on the FPGA-board. This information is stored in the.ucf-file. Right-click on the line that shows the filename and Add Source (Alternative: Menu toolbar s Source > Add Source ). Navigate to the correct directory (one up) and select and add the testbrd_spartan3.ucf description. The program will understand that the.ucf-file has to be complementary to the project s edf-file. Now we have to build the bit-file needed for programming the FPGA. But first, we should realize that the board will be programmed by means of a cable connected to a JTAG connector, thus following the JTAG programming protocol. This means that we have to use the JTAG Clock. Therefore, right-click on Generate Programming File and select Properties In the pop-up window, under the Startup Options Tab, change the FPGA Start-Up Clock into JTAG Clock and terminate with OK. ET4 351 (May, 2005) Page 5 of 12

6 The creation of the bit-file can be done by stepping sequentially through the Implement Design (Translate, Map, Place & Route) steps, but this will be done automatically when we select (double-click on) the Generate Programming File option. A in front of a description means a successfully terminated operation. Optionally, if you have enough time left: Look at Implement Design, Place & Route, View/Edit Placed Design (Floorplanner) to get an indication of the placement of the resources on the FPGA chip. ET4 351 (May, 2005) Page 6 of 12

7 Programming the FPGA Check that the Parallel IV Cable is correctly connected, i.e. there should be a 14-pin ribbon flat cable connected to the Par IV, JP5 connector at the lower right side of the board. On the host PC, the cable should be connected to the standard DB25 parallel (printer) port connector, and externally powered by interfacing to the PS/2 mouse or keyboard connection. Also verify the presence of the jumpers on header JP2 as drawn on the previously given board layout. Apply power to the FPGA board by means of the switch on the top left side, then start the impact programmer, by double clicking the Configure Device (impact) line or by clicking on the icon on the desktop. In the pop-up windows, select successively Configure Devices > Next Boundary-Scan Mode > Next Automatically connect to cable and identify Boundary scan chain > Finish Now, two devices should have been recognized in the Boundary-Chain, e.g. an xcf16p EPROM and the xc3s2000 FPGA. We won t use the xcf16p, so do not select it or answer Cancel or Pass if necessary. ET4 351 (May, 2005) Page 7 of 12

8 Sending the bit-file to the FPGA is accomplished by first telling impact which bit-file to use, followed by the actual transfer of the file: Right-click on the xc3s2000-icon and Assign New Configuration File Navigate to./rev_1 and select the testbrd_spartan3.bit file In case you had missed the step to change the FPGA Start-Up Clock into JTAG Clock, a warning message will pop-up saying that Startup clock has been changed to JtagClk. Just confirm with OK. Right click the xc3s2000 again, and select Program In the next window just select OK and programming will start. After a while you should see the message The LEDs now should show the on-off sequence as programmed in the vhdl file. With the Reset button SW2, at the right side of the LEDs you can (p)reset the LEDs in a predetermined state. ET4 351 (May, 2005) Page 8 of 12

9 Simulation with ModelSim ModelSim is a very powerful simulation environment, and as such can be difficult to master. The steps to create and use a ModelSim project manually are, however, fairly simple: 1. Create a directory for your project 2. Start ModelSim and create a new project 3. Add all your vhdl-files to the project 4. Compile your vhdl- files 5. Start the simulation 6. Add signals to the wave window 7. Run the simulation and examine the waveforms 8. If needed, recompile changed files 9. Restart and rerun the simulation Create a directory for your project Copy the files: testbrd_spartan3.vhd and tb_testbrd_spartan3.vhd into the vhdl directory that you created earlier (source in /usr/local/msclab/et4351/labsession/). Start ModelSim and create a project Start ModelSim, either by clicking on its icon on the desktop. or by Start > All Programs > ModelSim SE > ModelSim Pro (windows) At the main ModelSim window go to File > New > Project a. Enter a project name, this is for your reference only b. Set the Project Location to the directory you created in the step above. c. You can leave the Default Library Name as work d. Click OK Add the vhd files to the project Click File > Add to Project > Add Existing File to add your vhdl files to the project. a. Click Browse to locate the files to be added: testbrd_spartan3.vhd and tb_tstbrd_sp3.vhd (the top-level testbench) Note: you can add multiple files at a time by using Shift-Click or Control-Click to select them all at once. b. Leave all other settings on their default values, and verify that Reference from current location is selected, otherwise you will end up with multiple copies of the same files floating around. c. Click OK and finish with Close ET4 351 (May, 2005) Page 9 of 12

10 In the testbench, stimuli signals have been defined for the real signals on the board, such as the system-clock and the Reset signals. Their timing parameters are shown in the next figure. You can verify this, by looking at the testbench file in the editor. start 15 ns end 52 ns second reset-signal active between ns start simulation, t = 0 sys_clk period (20 ns) Compile your vhd files The project pane (selectable with the tab) on the left of the main ModelSim window should list all of the files in your project with a Status icon next to each one. a. A? means that the file has not been compiled since the last edit. b. An X means that the file could not be compiled, since it has an error. Double clicking the X will bring up a list of errors with line numbers c. A means that the file has been compiled successfully. The order in which the files are compiled is very important. Luckily, Modelsim can detect the necessary compilation order itself by examining the vhdl-code (one or more passes are needed). The procedure to obtain the correct situation is: select from the top Menu toolbar Compile > Compile Order In the next window, click on the Auto Generate button If in the Transcript pane # All compile dependencies have been resolved. is shown, and the Status of all files shows a, click on OK. If later on, a file is changed, it will show a? next to it. Such a file can be updated and recompiled by choosing Compile > Compile Selected Start the simulation Go to Simulate > Simulate to bring up the simulation dialog box. Alternatively you could have entered the vsim work.tb_testbrd_spartan3 command in the Transcript pane, see the ModelSim manual for more information. Usually, this will be much faster and easier. Go to the Design tab. a. Click the + next to the work library. ET4 351 (May, 2005) Page 10 of 12

11 b. select the testbench tb_testbrd_spartan3 and d. Click OK. Your design should now be loaded and is ready to simulate. If your design does not load, reread the above steps carefully. You should also check for errors and warnings from ModelSim, both are indicative of potential problems with your code. Add signals to the Wave Window With the simulation running, an additional Sim Tab should be visible in the Workspace pane on the left hand side a. The Sim Panel shows the hierarchy of all the modules in your project. b. Clicking the plus next to a module will show the modules instantiated within it. You should add as many signals as you might need to the ModelSim window. To add all signals from a module a. Right-Click on a module in the Sim Panel and select Add > Add to Wave. b. This will add all of the signals from that module to the Objects pane. Or, to add individual signals a. Go to the Signals Window If it is not visible, use the View > Signals window to display it b. Drag the signals you wish to see to the Wave Window Run the simulation From the toolbar menu select Simulate > Run and e.g. > Run 100ns, or, click on the icon on the Wave window toolbar. The wave window will now show the simulated signals. You can expand bus signals by clicking on the + signs, and zoom in, zoom out, etc. by clicking on the appropriate icons Verify that the LEDs change their states each time at a rising edge of bit1 of the div-counter, e.g. at a rate of sys_clk / 4. If there is time left, you can e.g. change the LED pattern, modify the sys_clk divider or deliberately introduce errors in the vhdl code. Be sure to use the copy of the vhdl files in your directory. Recompile changed vhd files When you have fixed bugs, or simply made changes you must recompile your vhdl files Near the bottom left of the ModelSim Main Window are tabs for the Project and Sim panes. Navigate to the Project Pane and Right-Click anywhere in the pane and select Compile > Compile Out-of-Date to recompile the modified files (which should have a? next to them). ET4 351 (May, 2005) Page 11 of 12

12 Restart / rerun the simulation You have to do this any time to make changes such as changing/recompiling vhdl code, or adding new signals to the wave window. At the command prompt type restart f; run 100ns a. restart f tells ModelSim that it needs to start the simulation over from the beginning, i.e. at time 0. b. run 100ns tells ModelSim to run the simulation for 100 nano-seconds. If you cannot see all of the necessary information, you may run the simulation for additional time, e.g. for a total running time of 1500ns: restart f; run 500ns run 1us ET4 351 (May, 2005) Page 12 of 12