1.Explain with the diagram IVT of 80X86. Ans-

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Malcolm McDonald
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1 1.Explain with the diagram IVT of 80X86 In kb from to 003ff are reserved for interrupt routine as shown in figure known as interrupt vector. It supports 256 interrupt procedures containing 16 bit IP & CS address. The type 0 4 are predefined or dedicated interrupts. Type 5 31 are reserved for intel. Type are available interrupt or user defined interrupts. Software Interrupts:- Software interrupt are produced by INT instructions. INTn :- It fetches the ISR from IT. The INTn instruction calls the ISR (procedure) that begins at the address represented in vector number n. 2.Differentiate between.com and.exe program Sr. No. Parame ters.com.exe 1. Maximu m size 64k length of (256 bytes) & mandatory word (2 byte) No limit 2. Entry = 0100H Derived by end statement

2 3. AL at 4. AH at 00 if default FCB # 1 has valid drive. OFFH for invalid drive 00 if default FCB # 2 has valid drive else OFFH for invalid drive 00 if default FCB # 1 has valid drive. OFFH for invalid drive. 00 if default FCB # 2 has valid drive else OFFH for invalid drive 5. CS at Segment containing module with 6. IP at 0100 Offset of within it s segment 7. DS at 8. ES at 9. SS at 10. SP at OFFFEH or top word available in memory Segment with stack Size of segment defined with stack attribute 11. Stack Zero word Initialize or uninitialized 12. Stack Size 13. Subrouti ne call 64k length of (256 bytes) & Mandatory word (2 byte) Unusually Near Defined in stack attribute NEAR OR FAR 14. Exit Method 15. Size of a file INT 21H 4CH Exact of program INT 21H 4CH Size of program & header 3.Explain separate code and cache concept? Pentium has superscalar architecture and has 2 integer pipe lines u and v. An 8 kb instruction cache is used to provide quick access to frequently used instruction when an instruction is not in cache, it is read from external data bus & code cache is updated for it. The branch target butter & pre fetch buffer work together with the instruction cachet to fetch instructions as fast as possible. A separate 8 kb data cache stores a copy of most frequently accessed memory data Since

3 memory access are significantly longer than processor clock cycles (longer time is required to access). The data & code cache is enabled or disabled by hardware or software. 4.Illustrate the loading of MS DOS into memory with graphical view 1) Reset a start of the system s the IP = OFFFFFOH (feature X 86 family). The IP jumps to system test code at ROM boot strap routine. 2) ROM Boot Strap reads Disk Boot Strap from the fist sector of the system startup disk & control transfer to it. 3) The disk boot strap routine checks the copies of MS DOS by reading first sector of boot directory & determining two files, IO.SYS & MS DOS.SYS. (a IBMB10.com & IBMDOS.com) 4) If files are not present user is prompted to change disk & strike any key to try again. 5) If two files are present boot strap reads them into memory & transfers control to the initial of IO.SYS 6) IO.SYS consist of two separate modules. 7) The fist module is BIOS which contains of link set of resident device drivers. 8) The second module is a SYS.INIT i.e. initialization code. It determines the amount of contiguous memory present in the system & then relocates itself to high memory & DOS kernel is loaded into the final memory.

4 9) This SYS.INIT file calls the initialization code i.e. MSDOS.SYS for device driver & setup the vectors for any external h/w interrupt service. 10) DOS kernel checks disk parameter block. 11) The entire CONFIG.SYS file is loaded into memory for processing. 12) After all installable device drivers have been loaded SYS.INIT closes all file handle & reopen to console printer & devices or standard i/o devices & calls MSDOS.EXE function to load command interpreter or shell. 5.Explain the structure of MSDOS with respective to its layers MS DOS (Microsoft Disk Operating System) The MS DOS is partitioned into several layers to isolate the kernel logic of the OS, user perception & hardware. The layers are as follows : 1) The BIOS (Basic Input Output System) 2) DOS kernel 3) The Command Processor (shell) 1) BIOS :- It is residual program provided by the manufacturer. Specific BIOS is available for individual computer & provided by manufacturer. It contains default resident hardware driver for : 1) Console display & keyboard (CON) 2) Line printer (PRN) 3) Auxiliary Device (AUX) 4) Date & Time (Clock) 5) Boot Disk Device (block device) Driver :- The drivers are responsible for i/o request pocket received from kernel & communicate with the network controller. Mostly drivers are available in ROM i.e. resident & sometime installed during initialization of device command i.e. installable (CONFIG.SYS) 2) DOS - Kernel :- The Kernel is a proprietary program supplied by Microsoft corporation & provides collection of hardware independent services on system function such as : 1) File & Record Management 2) Memory Management 3) Character Device I/O

5 4) Spawning of other program 5) Access to the real time clock 3) Command Processor :- Intrinsic command internal command Extrinsic command external command It is the user interface to the operating system. It is responsible for carrying out the commands i.e. loading or execution of program from the disk or mass storage device. The default shall command is command.com. It is a program under the control of MS DOS. It is fetcher divided into: 1) A resident portion at low portion of memory. 2) Initialization section at middle portion of the memory. 3) Transient Module at the high end of the memory. 6.Explain DOS-BIOS Interface User Program DOS BIOS Hardware Device 1) BIOS test & initialization attach devices & provide services that are used for reading to & for writing from the devices. 2) One task of a DOS is to interface with BIOS when there is a need to access its facilities. 3) When user program request a service of DOS, it may transfer the request the BIOS which in its turn access the requested device. 4) Sometimes a program makes request directly to the BIOS especially for keyboard or screen services. 7.List features of Pentium processor.

6 8.Distinguish between and Pentium Processor Parameter Pentium 1. Data Bus It has 32 bit data bus. It has 64 bit data bus. 2. Architecture RISC Super scalar 3. Operating Speed 100 MHz is the operating speed. 300 MHz is the operating speed. 4. Cache On board 8KB cache Separate cache for data and code 8 KB 5. Pipelining 5 stage pipe lining 8 stage Dual pipelining 9.Explain super scalar execution in Pentium? 1. Prefetch Stage (PF) :- 2. Decode 1 Stage (D1) :- 3. Decode 2 Stage (D2) :- 4. Execution Stage (EX) :- 5. Write Back Stage (WB) :- 10.Explain floating exceptions. i. There are two prefetch buffer or queue present in Pentium & at a time one of them is active to fetch instruction code from on chip cache or memory. In this stage CPU aligns the port appropriately because instructions are in variable length & given to decode stage DI. i. In DI stage CPU decodes the instruction & generates a control word by following some rules for instruction pairing. The two instructions are parable only if they are simple & register independent. i. In this stage control word from DI is decoded & memory addresses are generated for the data. i. In this stage CPU either access data cache for data operand or executes arithmetic logical function or floating operation. i. This is the final stage of integer instruction execution & CPU updates the target registers & E flag register. Ans As in the case if integer arithmetic there are six possible floating exceptions in Pentium. These are Divide by zero 2. Overflow 3. Underflow 4. Denormal operands and 5. Invalid operation. These exceptions carry their usual meanings. the divide by zero exception, invalid operations and denormal operand exemption can be easily detected even before the actual floating calculation.a mechanism known as safe instruction recognition (SIR) had been employed in Pentium mechanism determine where the exception is generated

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