Migrating from Spansion S25FL512S to Micron N25Q 512Mb Flash Device

Transcription

1 Technical Note TN-12-21: Migrating to Micron 512Mb Flash Device Introduction Migrating from Spansion 512S to Micron 512Mb Flash Device Introduction The purpose of this technical note is to compare features of the Micron (512Mb) and Spansion 512S Flash memory devices. Features compared include memory architecture, package options, signal descriptions, command sets, electrical specifications, and device identification. 1 Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. All information discussed herein is provided on an "as is" basis, without warranties of any kind.

2 Memory Array Architecture TN-12-21: Migrating to Micron 512Mb Flash Device Memory Array Architecture Table 1: Memory Array Architecture Features Features Two 256Mb devices stacked 512Mb monolithic Program 1 to 256 bytes Program 1 to 512 bytes Uniform sector erase (64KB) Uniform sector erase (256KB) Uniform subsector erase (4KB) N/A Cycling endurance 100,000 Cycling endurance 100,000 Data retention 20 years Data retention 20 years Package Configurations Table 2: Package Configurations Package V-PDFN-8 (8mm x 6mm) Yes No SOP2-16/300 mils Yes Yes T-PBGA-24b05 (6mm x 8mm, 5 x 5 ball) Yes Yes T-PBGA-24b05 (8mm x 6mm, 4 x 6 ball) No Yes Signal Descriptions Table 3: Signal Descriptions Signal Signal Type Description Notes C SCK Input Serial clock DQ0 SI/IO0 Input or I/O Serial data input or I/O DQ1 SO/IO1 Output or I/O S# CS# Input Chip select Serial data output or I/O W#/V PP /DQ2 WP#/IO2 Input or I/O Write protect/enhanced program supply voltage or I/O 1 HOLD#/DQ3 HOLD#/SIO3 Input or I/O HOLD or I/O V CC V CC Input Supply voltage V SS GND Input Ground RESET# RESET# Reset 2 V IO Input Versatile I/O power supply Notes: 1. V PP is not available on the 512S device. 2. The RESET# pin is only available for part numbers 512A83G1240X and 512A83GSF40X. On those two parts, the RESET# pin must be connected to an external pull-up. On the device, the pull-up is internal. For other part numbers, RE- SET# is replaced by HOLD#. 2

3 Commands Commands Table 4: Command Set Command RESET Operations Command Code Command Code RESET ENABLE 66h N/A RESET MEMORY 99h F0h PERFORMANCE ENHANCE MODE RESET N/A FFh 1 IDENTIFICATION Operations READ ID 9Eh/9Fh 9Fh MULTIPLE I/O READ ID AFh N/A READ ELECTRONICS SIGNATURE N/A ABh READ MAN & DEV ID N/A 90h READ SERIAL FLASH DISCOVERY PARAMETER 5Ah 5Ah READ Operations READ 03h 03h 0Bh 0Bh DUAL OUTPUT 3Bh 3Bh DUAL INPUT/OUTPUT BBh BBh QUAD OUTPUT 6Bh 6Bh QUAD INPUT/OUTPUT EBh EBh FAST_READ.DTR 0Dh 0Dh DUAL OUTPUT DTR 3Dh N/A DUAL INPUT/OUTPUT DTR BDh BDh QUAD OUTPUT DTR 6Dh N/A QUAD INPUT/OUTPUT DTR EDh EDh 4-BYTE ADDRESS MODE Operations ENTER 4-BYTE ADDRESSING B7h N/A 2 EXIT 4-BYTE ADDRESSING E9h N/A 4-BYTE READ 13h 13h 4-BYTE FAST_READ 0Ch 0Ch 4-BYTE DUAL OUTPUT 3Ch 3Ch 4-BYTE DUAL INPUT/OUTPUT BCh BCh 4-BYTE QUAD OUTPUT 6Ch 6Ch 4-BYTE QUAD INPUT/OUTPUT ECh ECh 4-BYTE PAGE PROGRAM 12h 12h 3 4-BYTE QUAD PAGE PROGRAM 34h 34h 3 4-BYTE FAST_READ.DTR N/A 0Eh 4-BYTE DUAL INPUT/OUTPUT DTR N/A BEh 4-BYTE QUAD INPUT/OUTPUT DTR N/A EEh Notes 3

4 Commands Table 4: Command Set (Continued) Command Command Code Command Code 4-BYTE SECTOR ERASE DCh DCh 3 4-BYTE SUB-SECTOR ERASE 4KB 21h N/A 3 WRITE Operations WRITE ENABLE 06h 06h WRITE DISABLE 04h 04h REGISTER Operations READ STATUS REGISTER 05h 05h READ STATUS REGISTER 2 N/A 07h WRITE STATUS REGISTER 01h 01h READ LOCK REGISTER E8h N/A WRITE LOCK REGISTER E5h N/A READ FLAG STATUS REGISTER 70h N/A CLEAR FLAG STATUS REGISTER 50h 30h 4 READ NONVOLATILE CONFIGURATION REGISTER B5h N/A WRITE NONVOLATILE CONFIGURATION REGISTER B1h N/A READ VOLATILE CONFIGURATION REGISTER 85h N/A WRITE VOLATILE CONFIGURATION REGISTER 81h N/A READ ENHANCED VOLATILE CONFIGURATION REGISTER 65h N/A WRITE ENHANCED VOLATILE CONFIGURATION REGISTER 61h N/A READ EXTENDED ADDRESS REGISTER C8h 16h WRITE EXTENDED ADDRESS REGISTER C5h 17h Misc. Operations ASP REGISTER READ N/A 2Bh ASP REGISTER WRITE N/A 2Fh READ CONFIGURATION REGISTER N/A 35h AUTOBOOT REGISTER READ N/A 14h AUTOBOOT REGISTER WRITE N/A 15h PPB LOCK BIT WRITE N/A A6h PPB LOCK BIT READ N/A A7h DYB READ N/A E0h DYB WRITE N/A E1h PPB READ N/A E2h PPB PROGRAM N/A E3h PPB ERASE N/A E4h PASSWORD READ N/A E7h PASSWORD PROGRAM N/A E8h PASSWORD UNLOCK N/A E9h Notes 4

5 Commands Table 4: Command Set (Continued) Command Command Code Command Code BANK REGISTER ACCESS N/A B9h READ DATA LEARNING PATTERN N/A 41h PROGRAM NV DATA LEARNING REGISTER N/A 43h WRITE VOLATILE DATA LEARNING REGISTER N/A 4Ah PROGRAM Operations PAGE PROGRAM 02h 02h DUAL INPUT FAST PROGRAM A2h N/A EXTENDED DUAL INPUT FAST PROGRAM D2h N/A QUAD INPUT FAST PROGRAM 32h 32h/38h EXTENDED QUAD INPUT FAST PROGRAM 12h/38h N/A 5 ERASE Operations BULK ERASE C7h C7h/60h SECTOR ERASE 64KB D8h D8h 6 SUB-SECTOR ERASE 4KB 20h N/A 6 PROGRAM/ERASE SUSPEND 75h 85h/75h PROGRAM/ERASE RESUME 7Ah 8Ah/7Ah ONE-TIME PROGRAMMABLE (OTP) Operations READ OTP ARRAY 4Bh 4Bh PROGRAM OTP ARRAY 42h 42h QUAD Operations ENTER QUAD 35h N/A 3 EXIT QUAD F5h N/A 3 Notes Notes: 1. Execution in place (XIP) device reset. For the device, the FFh sequence is used to exit from dual or quad protocol (see XIP and Protocol Exiting Algorithm). 2. The device also sets addressing protocol by volatile bit BAR<7>; the sets addressing protocol by bit NVCR<0> or with the ENTER 4-BYTE ADDRESS command. 3. This command is available only for part numbers 512A83G1240x and 512A83GSF40x. 4. Program/erase error bits are cleared by CLEAR FLAG STATUS REGISTER in the device; the device clears program/erase error bits the same way in status register h is valid for part numbers 512A83G1240x and 512A83GSF40x; 12h is valid for all other part numbers. 6. The device requires that 4-byte addressing be enabled by opcode 35h or default at power-up (NVCR) before the command. Table 5: Different Commands Sharing Same Command Code Command Code Command 512S Command ABh RELEASE FROM DEEP POWER-DOWN READ ELECTRONIC SIGNATURE 12h QUAD INPUT/OUTPUT FAST PROGRAM (QIOFP) 4-BYTE PAGE PROGRAM 1 5

6 Commands Table 5: Different Commands Sharing Same Command Code (Continued) Command Code Command 512S Command B9h DEEP POWER-DOWN BANK REGISTER ACCESS E8h READ LOCK REGISTER PASSWORD PROGRAM E9h EXIT 4-BYTE ADDRESSING PASSWORD UNLOCK 85h READ VOLATILE CONFIGURATION REGISTER PROGRAM/ERASE RESUME Note: 1. The sharing of this command is not valid for part numbers 512A83G1240x and 512A83GSF40x. READ Commands After any READ command is executed, the device will output data from the selected address in the die. After a die boundary is reached, the device will start reading again from the beginning of the same 256Mb die. A read is completed by executing the READ command twice. The selection of the die is done by writing the enhanced address register with the segment corresponding to the address of the device (see more details in the datasheet). The READ/ command sets for the and devices are identical, and each device follows the standard three-byte protocol. The and devices have configurable dummy cycles, in both DTR and STR. dummy cycles can be configured by configuration register bits 7 and 8; dummy cycles can be configured by nonvolatile configuration register bits or by volatile configuration register bits 7 4. Table 6: STR: Minimum Number of Dummy Cycles Required per Each Frequency Frequency MHz DUAL OUTPUT DUAL I/O FAST READ QUAD OUTPUT QUAD I/O FAST READ Note: 1. The device has one additional clock for mode bits in QUAD I/O only. Table 7: DTR: Minimum Number of Dummy Cycles Required per Each Frequency Frequency MHz DUAL OUTPUT DUAL I/O FAST READ QUAD OUTPUT QUAD I/O FAST READ

7 Commands Table 7: DTR: Minimum Number of Dummy Cycles Required per Each Frequency (Continued) Frequency MHz DUAL OUTPUT DUAL I/O FAST READ QUAD OUTPUT QUAD I/O FAST READ Notes: Execute-in-Place (XIP) Table 8: XIP Mode Summary at STR and DDR 1. The device has one additional clock for mode bits in QUAD I/O only. 2. For the device, the difference for dummy clock nr is due to various latency codes (LC) configurations. The device requires a nonvolatile quad bit in the configuration register to enable QUAD I/O functionality. When this bit is set, HOLD# and WP# are disabled. VECR or NVCR enables the QSPI protocol. (See the data sheet for more information on this protocol.) QUAD commands are available without any register setting. When the VECR or NVCR bits are set, W# and HOLD# remain functional. With NVCR set (bit 3 = 0), the device can be powererd up or down with QUAD I/O functionality. No additional commands are required for the device to use QUAD or DUAL I/O functionality. The manufacturer ID, memory type, and memory capacity of both the and devices can be read out by issuing a 9Fh command. The device outputs the same data when the 9Eh command is issued. The device contains commands that output the device ID (ABh) as well as a command that outputs the manufacturer ID and device ID (90h). The device enters and exits XIP via volatile and nonvolatile configuration register settings. The non-volatile configuration regsiter sets XIP mode at device power-on. Once enabled, XIP management in the matches that of the Spansion XIP usage mode. Spansion uses one nibble (code Ah) to enter or exit XIP mode. The solution is fully compatible with the methodology of enter and exit from XIP because other bits are "Don't Care." The following table compares XIP read configuration between the two devices. Yes N/A DUAL OUTPUT Yes N/A DUAL I/O Yes Yes QUAD OUTPUT Yes N/A QUAD I/O Yes Yes 7

8 Commands Figure 1: XIP Timing Configuration S# Confirmation bits B7 B0 Mode C Mode 0 I/O switches from Input to Output DQ DQ DQ DQ Dummy Dummy Byte 1 Byte 2 Table 9: XIP Confirmation Bit Software Commands XIP Confirmation Bit Enter/confirm XIP mode B4 = 0 (B7 B5 and B3 B0 = "Don't Care") Mode bits = Ah; B7 = 1; B6 = 0; B5 = 1; B4 = 0 Exit XIP mode B4 = 1 (B7 B5 and B3 B0 = "Don't Care") Mode bit Ah 8

9 XIP and Protocol Exiting Algorithm XIP Exiting Sequence TN-12-21: Migrating to Micron 512Mb Flash Device XIP and Protocol Exiting Algorithm For and devices, XIP mode and all memory and registers can be reset by the RESET# pin. If you only want to reset XIP mode for Spansion, using command FFh for, use the following procedure: Note: This procedure is required because, when power loss occurs, the device may start in an indeterminate state (XIP or an unnecessary protocol). 1. Perform the XIP exiting sequence. 2. Perform the dual SPI protocol exiting sequence. Note: During execution of the WRITE NONVOLATILE CONFIGURATION REGISTER command, t SHSL2 must be at least 50ns. Below is the RESET sequence for all possible XIP configurations (QUAD I/O, DUAL I/O, and ). Figure 2: XIP Exiting Sequence C S# DQ0 DQ3 Dual SPI Protocol Exiting Sequence Exit from DUAL or QUAD SPI protocol using the following FFh sequence. Figure 3: Dual SPI Protocol Exiting Sequence C S# DQ0 DQ3 9

10 Electrical Characteristics TN-12-21: Migrating to Micron 512Mb Flash Device Electrical Characteristics Table 10: DC Current Characteristics Parameter Symbol Min Max Min Max Standby current I CC µa 1 Operating current ( QUAD I/O) Units I CC ma Operating current (PAGE PROGRAM) I CC ma Operating current (WRITE STATUS REGISTER) I CC ma Operating current (ERASE) I CC ma Notes Note: µA if automotive grade. Table 11: DC Voltage Specifications Parameter Symbol Min Max Min Max Units Input low voltage V IL V CC V CC V Input high voltage V IH 0.7 V CC V CC V CC V CC V Output low voltage V OL V CC V Output high voltage V OH V CC V CC V 10

11 AC Characteristics AC Characteristics Table 12: AC Specifications Parameter Symbol Alternate Symbol Min Max Min Max Clock frequency (x1 ) f C f C MHz Clock frequency (x2, x4 ) f C f C MHz Clock frequency (READ) f R f R MHz S# active setup time t SLCH t CSS 4 10 ns Data-in setup time t DVCH t DSU 2 5 ns Data-in hold time t CHDX t DH 3 4 ns S# deselect time after correct READ (ARRAY READ to ARRAY READ) Units t SHSL t CSH ns Output disable time ( V) t SZQZ t DIS 8 8 ns Clock low to output valid (30pF) t CLQV t V 7 8 ns Output hold time t CLQX t HO 1 0 ns HOLD to output Low-Z t HHQX t LZ N/A 8 N/A 8 ns HOLD to output High-Z t HLQZ t HZ N/A 8 N/A 8 ns Note: 1. AC specifications compare the fastest versions available at the full voltage range ( V). Program and Erase Specifications Table 13: Program and Erase Specifications Operation Typ Max Typ Max Unit PAGE PROGRAM (256 bytes) N/A N/A ms PAGE PROGRAM (512 bytes) ms 4KB SUBSECTOR ERASE N/A N/A s 64KB SECTOR ERASE s BULK ERASE s Note: 1. Typical value is calculated by formula documented in data sheet. 11

12 Configuration and Memory Map TN-12-21: Migrating to Micron 512Mb Flash Device Configuration and Memory Map Table 14: Sectors and Subsectors Address Range Sector Subsector Start End FF F000h 03FF FFFFh : : : FF 0000h 03FF 0FFFh : : : : FF F000h 01FF FFFFh : : : FF 0000h 01FF 0FFFh : : : : FF F000h 00FF FFFFh : : : FF 0000h 00FF 0FFFh : : : : F 0000h 007F 0FFFh : : : F 0000h 007F 0FFFh : : : : F F000h 003F FFFh : : : F 0000h 003F 0FFFh : : : : F000h 0000 FFFFh : : : h FFFh 12

13 Device Identification Table 15: Read Identification Summary TN-12-21: Migrating to Micron 512Mb Flash Device Device Identification Manufacturer identification is assigned by JEDEC. As a result, the and devices have different manufacturer ID and memory type codes even though their memory capacity is identical. Command 9Fh is used to read these codes in both devices. has a unique ID (UID) composed of 17 read-only bytes, which contain the following data: The first byte is set to 10h. The next two bytes of extended device ID specify device configuration (top, bottom, or uniform architecture and hold or reset functionality). The next 14 bytes contain optional customized factory data. The customized factory data bytes are factory programmed. Refer to the 512Mb data sheet for more information. Parameter Manufacturer ID 20h 01h Memory type BAh 02h Memory capacity 20h 20h Part Numbers Table 16: Cross-Reference Part Numbers Micron Part Number Spansion Part Number Package Secure Media Notes 512A13G1240E 512SAGBFV700 T-PBGA No Tray 512A13G1240F 512SAGBFV703 T-PBGA No Tape & Reel 512A83G1240E 512SAGBFV700 T-PBGA No Tray 1 512A83G1240F 512SAGBFV703 T-PBGA No Tape & Reel 1 512A13G1241E N/A T-PBGA Yes Tray 2 512A13G1241F N/A T-PBGA Yes Tape & Reel 2 512A13G1241E N/A T-PBGA Yes Tray 1, 2 512A13G1241F N/A T-PBGA Yes Tape & Reel 1, 2 512A13GF840E N/A V-PDFN-8 No Tray 3 512A13GF840F N/A V-PDFN-8 No Tape & Reel 3 512A13GSF40F 512SAGBMFV703 SO16 wide No Tape & Reel 512A13GSF40G 512SAGBMFV701 SO16 wide No Tube 512A13GSF40F 512SAGBMFV703 SO16 wide No Tape & Reel 1 512A13GSF40G 512SAGBMFV701 SO16 wide No Tube 1 Notes: 1. Micron RESET# pin. 2. Secure release not available for Spansion device. 3. V-PDNN-8 package not available for Spansion device. 13

14 Conclusion Conclusion Comparing the features of the Micron 512Mb and the Spansion 512S Flash memory devices enables users to migrate applications from the 512S to the 512Mb device. 14

15 Revision History Revision History Rev. B 11/12 Rev. A 06/12 Signal Descriptions table: Updated last row; replaced notes 2 and 3 with new note Command Set table: Updated table and notes Reset Algorithm heading: Changed to XIP and Protocol Exiting Algorithm; updated description Reset XIP heading and figure: Changed to XIP Exiting Sequence Reset Dual SPI heading and figure: Changed to Dual SPI Protocol Exiting Sequence Cross-Reference Part Numbers table: Updated table Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID , Tel: Customer Comment Line: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 15