PlanAhead Software Tutorial

Transcription

1 PlanAhead Software Tutorial Team Design

2 NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. Copyright 2011 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 07/06/ Initial Xilinx release. Team Design Tutorial

3 Table of Contents Revision History PlanAhead Software Tutorial: Team Design Introduction Tutorial Objectives Getting Started Tutorial Steps Step 1: Opening a Project and Elaborating RTL Step 2: Setting Partitions and Drawing Pblocks Step 3: Synthesizing and Implementing the Design Step 4: Promoting Synthesis and Creating Team Member Projects Step 5: Working on cpuengine as Team Member Step 6: Working on usbengine as Team Member Step 7: Running the Assembly as Team Leader Conclusion Appendix A: Additional Resources Xilinx Resources PlanAhead Documentation Team Design Tutorial 3

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5 PlanAhead Software Tutorial: Team Design Introduction Tutorial Objectives Project Set Up The Team Design flow is a hierarchical design methodology that uses partitions to allow a large, complex design to be broken up into smaller logical blocks. These blocks can be implemented independently and simultaneously. This allows each block to be individually designed, implemented, and verified in context with the rest of the design. When all blocks are complete, the entire design is brought together in an assembly run in which results can be imported and preserved. A Team Design flow team consists of one team leader, and one or more team members. This tutorial provides an overview of the Team Design flow, in which you will complete a design acting as a team leader and various team members. The objectives of this tutorial are to familiarize you with the partitions and the Team Design flow using the PlanAhead software. Initially, as team leader you will: Define partitions on each team member block (each team member block is a black box) Define Pblocks and review existing physical and timing constraints Synthesize an initial version of the design using XST Incremental Synthesis Promote Synthesis results for the top partition Runs DRCs and Implement the initial design Create PlanAhead projects for each team member Team Member Work Then, with a PlanAhead project for each team member, you will complete the work of each team member as follows: Update project to include actual design files for the team member block Synthesize the updated team member design while importing the top partition (other team member blocks are black boxes) Team Design Tutorial 5

6 Getting Started Design Assembly Getting Started Implement the team member design (other team member blocks are black boxes) Promote successful synthesis and implementation results to a location accessible by the team leader The team leader then assembles the design by importing the results from each team member project. You will: Update the team leader project to include NGC files for each team member block Setup implementation to import each team member block while implementing the top partition Verify design assembles while maintaining placement and routing results from each team member Software Requirements Access to the ISE Design Suite software is required to perform this tutorial. Ensure that the PlanAhead software is operational and the sample design data is installed prior to beginning the tutorial. For installation instructions and information, see the ISE Design Suite: Installation and Licensing Guide (UG798) cited in Appendix A, Additional Resources. Hardware Requirements Xilinx recommends 2 GB or more of RAM for use with the PlanAhead software on larger devices. For this tutorial, a smaller design was used. 1 GB of RAM should be sufficient, but it could impact performance. Tutorial Description This tutorial uses and incremental synthesis flow to create separate netlist for each partitioned instance. These individual netlists are required for a team design flow. The design used throughout this tutorial contains: A RISC processor FFTs Gigabit transceivers Two USB port modules (to be partitioned) An xc6vlx75tff784 device A small design is used to allow the tutorial to be run with minimal hardware requirements and to enable timely completion, as well as to minimize the data size. 6 Team Design Tutorial

7 Tutorial Steps Tutorial Steps Step 1: Opening a Project and Elaborating RTL Step 2: Setting Partitions and Drawing Pblocks Step 3: Synthesizing and Implementing the Design Step 4: Promoting Synthesis and Creating Team Member Projects Step 5: Working on cpuengine as Team Member Step 6: Working on usbengine as Team Member Step 7: Running the Assembly as Team Leader Team Design Tutorial 7

8 Step 1: Opening a Project and Elaborating RTL Step 1: Opening a Project and Elaborating RTL This tutorial uses an existing PlanAhead project, and focuses on the team design aspects in the software. You will not create a new design using the New Project Wizard. Note: The PlanAhead software version 13.x supports partitions in RTL projects targeting Spartan -6, Virtex -6, and newer families. Downloading and Extracting the Team Design Tutorial Design Files 1. Download the PlanAhead_Tutorial.zip file from the Xilinx website: dt_planahead_planahead13-2_tutorials.htm 2. Extract the zip file contents into any write-accessible location. The unzipped design data directory is referred to in this tutorial as <Extract_Dir>. The tutorial sample design data is modified while performing this tutorial. A new copy of the original design file data is required each time you run the tutorial. Opening the PlanAhead RTL Project 1. Open the PlanAhead software. On Windows, double-click the Xilinx PlanAhead 13 Desktop icon, or select Start > Programs > Xilinx ISE Design Suite 13 > PlanAhead > PlanAhead. On Linux, go to the <Extract_Dir> directory and type planahead. 2. From the Getting Started page, click Open Project. 3. Browse to <Extract_Dir> and open the project file located at:./projects/project_tl/project_tl.ppr The Project Manager view opens. You can browse the sources for the design in the Sources window and note the various VHDL and Verilog files along with a UCF called top_full.ucf. This UCF contains timing constraints and I/O pin locations already. Elaborating RTL Design The RTL Design view must be used to define partitions in an RTL project. When the RTL Design view is opened the RTL code is elaborated, and the design hierarchy is displayed. This is a pre-synthesized view of the design that is used to define partitions and create constraints. 1. In the Flow Navigator, click RTL Design. 8 Team Design Tutorial

9 Step 1: Opening a Project and Elaborating RTL X-Ref Target - Figure 1 Figure 1: Opening the RTL Design view Messages warning against undefined instances and others about Critical Warnings in the design might be seen. These are mostly due to the fact that some modules are defined as black boxes, and these are expected. 2. In the Undefined Modules message windows, click OK. The Undefined Modules message is expected and can be safely ignored. This initial version of the design has black box module definitions for two modules. These modules are assigned to each team member later in this tutorial. A definition (or1200_bb.v and usbf_bb.v) already exists for each module to describe the port direction and port widths. 3. In the Constraint File Critical Warnings message box, click OK. The Constraint File Critical Warnings are expected and can be safely ignored. When the RTL Design view opens it parses the UCF. Because the RTL design view is a pre-synthesized version of the design, there are instances with constraints in the UCF that do not yet exist in the elaborated design, such as I/O buffers. Team Design Tutorial 9

10 Step 2: Setting Partitions and Drawing Pblocks Step 2: Setting Partitions and Drawing Pblocks Based on the results of the PlanAhead Software Tutorial: Design Analysis and Floorplanning for Performance (UG676), cited in Appendix A, the usbengine instances have been identified as timing-critical modules, and it is advantageous to preserve successful implementation results of these instances. However, this fact alone does not make these good candidates for partitions. They are good candidates for partitions because they are logically isolated from the rest of the design, and have reasonable interface timing by way of registered inputs and outputs. You can use the PlanAhead DRCs to help identify modules that are good candidates for partitions. For more information on how to select a module instance for partitioning, see the Hierarchical Design Methodology Guide (UG748), cited in Appendix A. Partitioned instances can be floorplanned just like any other instance, and creating Pblock (AREA_GROUP) constraints can help achieve timing closure and improve runtime. The UCF provided with this tutorial constrains the usbengine I/O logic along the left side of the device, and the steps below walk you through setting partitions and creating appropriate Pblock constraints for the team member instances. Note: Pblocks are required in a Team Design flow for each team member partition. Setting Partitions on Team Member Instances 1. From the RTL Design view, click the RTL Netlist tab. 2. Press the Ctrl key, and select usbengine0, usbengine1 and cpuengine. 3. Right-click, and select Set Partition. X-Ref Target - Figure 2 Figure 2: Setting Partitions on usbengine and cpuengine Instances After you set the partitions, the icon associated with the instances changes from. to 10 Team Design Tutorial

11 Step 2: Setting Partitions and Drawing Pblocks Note: Although there are three partitions being defined here, there are only two team members in addition to the team leader. Both usbengine instances are managed by a single team member because there is only one set of HDL associated with this module. Drawing Pblocks for the Team Member Partitions In this step, you will define Pblocks and review existing physical and timing constraints. Note: This step does not affect synthesis results and can be done post synthesis in the Netlist Design view as well. 1. From the RTL Netlist window, select usbengine1. 2. Right-click, and select Draw Pblock. Note: You can use the Draw Pblock button from the Device view toolbar also. X-Ref Target - Figure 3 Figure 3: Selecting the Draw Pblock Tool 3. With the Draw Pblock tool active, move the cursor to the Device window. 4. Click the top-left corner of the device where the CLBs start, and drag down and to the right to create a rectangle covering most of the top-left quadrant of the device (Figure 4). Team Design Tutorial 11

12 Step 2: Setting Partitions and Drawing Pblocks X-Ref Target - Figure 4 Figure 4: Pblock Rectangle for usbengine1 5. In the New Pblock dialog box: a. Verify that the SLICE and RAMB36 grids are selected, and deselect other resources that are not needed. b. Verify that the number of available RAMB36 is 36. Note: If the rectangle does not fully cover the region shown in Figure 4, this number could be less than the required 36, in which case the design fails to place. c. Click OK. 6. If the number of available RAMB36 resources is less than 36, adjust the size of the Pblock rectangle by selecting it and resizing. 7. Repeat steps 1 through 6 for usbengine0 in bottom-left quadrant. Again, only SLICE and RAMB36 (36 of them) are required for this block. 8. Repeat steps 1 through 6 for cpuengine in top-right quadrant. For cpuengine the Pblock should contain all four ranges (SLICE, DSP48, RAMB18, and RAMB36). The number of resources required for the cpuengine is not critical. The Pblock must roughly cover the top right quadrant of the die. The completed floorplan should look like Figure Team Design Tutorial

13 Step 2: Setting Partitions and Drawing Pblocks X-Ref Target - Figure 5 Figure 5: Completed Floorplan for Pblocks usbengine0, usbengine1, and cpuengine Team Design Tutorial 13

14 Step 3: Synthesizing and Implementing the Design Step 3: Synthesizing and Implementing the Design In the previous steps, you defined partitions on the elaborated HDL design and created the necessary constraints. In this step, you will run synthesis and implementation. During synthesis, XST recognizes that the design has partitions, and runs the design through an incremental flow. Normally, XST would generate individual NGC files for each partition when using the incremental flow. However, because all team member partitions are black boxes and contain no logic, only the top-level NGC file is created during synthesis. Note: This tutorial uses an RTL project. However, for a bottom-up or third-party incremental synthesis flow, synthesis is run outside of the PlanAhead software, and a netlist project is used in PlanAhead instead of an RTL project. Running Synthesis 1. In the Flow Navigator, click the Synthesize button to launch synthesis, as shown in Figure 6. This design uses the default synthesis options. X-Ref Target - Figure 6 Figure 6: Launch XST Incremental Synthesis You might be prompted to Save your design. Before running synthesis, PlanAhead saves all partition and floorplan changes. 2. If prompted to do so, click Save to save all recent changes. Running DRCs on Partitions Design Rule Checks (DRC) can be run on the RTL design, although the checks at this stage are limited. It is recommended that you run DRC on the post synthesis design, prior to implementation. To check DRC, load the Netlist Design view, and run partition-specific DRCs. 1. In the Flow Navigator, click Netlist Design to open the Netlist Design view Team Design Tutorial

15 Step 3: Synthesizing and Implementing the Design This loads the synthesis results and allows for additional DRC checking. 2. In the Flow Navigator under Netlist Design, click Run DRC. Alternatively, you can select Tools > Run DRC. 3. From the Run DRC dialog box, unselect all rules except Partition and Team Design. (Figure 7) 4. Click OK. X-Ref Target - Figure 7 Figure 7: Run Partition DRCs PlanAhead reports Advisory, Warning, Error, and Fatal messages for DRCs. In this case, the DRC returns several warning messages. The DRC messages can be safely ignored as they are caused by the black boxes in the design, along with some other minor messages. In an actual design, all messages by the DRCs should be investigated, and serious issues should be corrected. Running Implementation Implementation is run at this stage to provide a sanity check that all timing and floorplan constraints are valid before passing this design off to each team member. Given that the two usbengine instances and the cpuengine instance are black boxes, no real useful implementation results is obtained. 1. In the Flow Navigator, click Implement. 2. Click the Report tab to see a list of all the ISE Implementation report files. As each process finishes, the related report files can be opened. 3. After NGDBuild finishes, double-click the NGDBuild Report to open the report file. 4. Scroll to the bottom of the report file and note the partition information, as shown in Figure 8. Team Design Tutorial 15

16 Step 3: Synthesizing and Implementing the Design Note that the three team member partitions are all listed as Black Box Module. Partition information is provided in every report file (NGDBuild, Map, and PAR), and it is an easy way to verify the status of all partitions on a given run. X-Ref Target - Figure 8 Figure 8: Partition Implementation Status in Report Files 16 Team Design Tutorial

17 Step 4: Promoting Synthesis and Creating Team Member Projects Step 4: Promoting Synthesis and Creating Team Member Projects The design is now ready for the team members to start their work. Before generating PlanAhead projects for each team member, the initial synthesis results should be promoted. Because the implementation results of the previous step are not used by team members, we do not need to promote those results. Promoting the Successful Synthesis Results After synthesis (or implementation) has completed (in the last step), you can promote the results. 1. In the Flow Navigator, click Promote Partition to open the Promote Partitions dialog box. 2. For the synth_1 run, select only the top partition to be promoted, as shown in Figure 9. Note: Do not to promote other partitions at this stage since no useful data exists for the other partitions. Promoting them does not hurt anything, but will require additional steps by each team member to change the promoted partition state values back to implement for their runs. X-Ref Target - Figure 9 Figure 9: Promote Partitions Dialog Box Team Design Tutorial 17

18 Step 4: Promoting Synthesis and Creating Team Member Projects 3. Set the Directory for synth_1 to: <Extract_Dir>/Promote/TL/synth_1 4. Optionally, you can enter a description about the promoted data. 5. Verify that the check box Automatically manage Partition action and import location is checked. This enables PlanAhead to update the partition state and import location for the next synthesis run by the team leader or team member. If this box is not checked, it is your responsibility to manage these attributes. 6. Click OK to promote the top partition synthesis results. Because the synth_1 directory already exists, a message asking if it is OK to overwrite the existing directory appears. Click Yes. 7. Explore the changes caused by promoting partitions (Figure 10). In the RTL Design view, you will now see a Promoted Partitions tab. Note: If you do not see this window, open the window manually by selecting Window > Promoted Partitions. The Specify Partitions dialog box now shows the Action on the top partition as Import. Note: To access the Specify Partitions dialog box, click on the pull-down menu on the right side of the Synthesize button in the Flow Navigator. X-Ref Target - Figure 10 Figure 10: The Promoted Partitions Window Creating Team Member Projects for usbengine and cpuengine To create a simple and consistent starting point for all team members to start their development work, use the Save Project As command to create multiple copies of this initial project. For this tutorial, you will create one project for the cpuengine instance, and one project for the two usbengine instances because they are the same module and will be managed by a single team member. 1. Select File > Save Project As Team Design Tutorial

19 Step 4: Promoting Synthesis and Creating Team Member Projects 2. Enter project_tm_usbengine as the Project Name 3. Specify <Extract_Dir>/Tutorial_Created_Data as the Project location 4. Click OK. 5. Repeat steps 1 through 4 with the following parameters: Project Name: project_tm_cpuengine Project location: <Extract_Dir>/Tutorial_Created_Data Team Design Tutorial 19

20 Step 5: Working on cpuengine as Team Member Step 5: Working on cpuengine as Team Member Now that the team leader has set up the design and created a workspace for each team member, you will switch roles and implement each block as a team member. Normally the work of the team members can be done in parallel, but for this tutorial you will implement each team member block sequentially. For each team member project, you will: Update the project sources to include the completed logic for the team member block Synthesize the project Implement the project Promote the results Adding Sources to cpuengine Begin by adding sources to the cpuengine project since it is open already, from the last step. 1. Make sure the current PlanAhead project is project_tm_cpuengine. If it is not, open this project now. 2. Switch to the Project Manager view. 3. Select or1200_bb.v in the Sources window. This is the black box module for cpuengine that was used for the initial project, but will now be replaced with logic. 4. Right-click, and select Remove from Project. 5. Click OK to confirm this action. X-Ref Target - Figure 11 Figure 11: Remove or1200_bb.v Black Box Module 20 Team Design Tutorial

21 Step 5: Working on cpuengine as Team Member 6. At the top of the Sources window, click the Add Sources button ( ) to open the Add Sources wizard. Alternatively, you can right-click, and select Add Sources. 7. From the Add Sources wizard, select Add or Create Design Sources, and click Next. 8. Click the Add Directories button to add the completed sources for the cpuengine instance. 9. Browse to./sources/hdl/ and select the or1200 directory. 10. Click Select. X-Ref Target - Figure 12 Figure 12: Add Source Directory or Verify the directory to be added and click Finish. Synthesizing and Implementing cpuengine The RTL Design and Netlist Design views are now out of date. To update them, you will: Reload (or close and reopen) these views Verify the partition settings for synthesis and implementation Launch the runs Promote the results Team Design Tutorial 21

22 Step 5: Working on cpuengine as Team Member 1. Reload the design. X-Ref Target - Figure 13 If the RTL Design view was closed, in the Flow Navigator, click RTL Design to load the latest version of the design. If the RTL Design view is open, the banner across the top of the view states that it is out of date. In the banner, click the Reload hyperlink to reload the view. Figure 13: Banner with RTL Design Status 2. Verify that cpuengine is no longer a black box. When the RTL Design view is reloaded or reopened you should again receive a message about Undefined Modules Found." However, now the message should only refer to the usbengine module (usbf_top), which will remain a black box for this project. Click OK in the messages, and you should now see that the icon in the RTL Netlist window for cpuengine has changed. 3. In the Flow Navigator, click the pull-down menu next to the Synthesis or Implement buttons, and select Specify Partitions. The Specify Partitions dialog box opens and you can verify the partition settings for synthesis and implementation. X-Ref Target - Figure 14 Figure 14: Specify Partitions 4. From the Synthesis tab, verify that top is set to Import, and all other partitions are set to Implement. There is no other data to import besides the top-level synthesis results because top is the only partition that has been promoted. Note: If the top partition is not set to import for synthesis, top might not have been promoted correctly in the previous steps, or the checkbox Automatically manage Partition action and import location might have been unchecked in the Promote Partition dialog box. If top was not correctly promoted, it cannot be imported at this stage Team Design Tutorial

23 Step 5: Working on cpuengine as Team Member X-Ref Target - Figure 15 Figure 15: Specify Partitions Dialog Box 5. Click the Implementation tab, and verify that all partitions are set to Implement. 6. Click OK to exit the Specify Partitions dialog box. 7. In the Flow Navigator, click the green Implement button to synthesize and implement the design. 8. A message reports that synthesis is out-of-date. Click Yes to launch synthesis prior to implementation. Note: To save time, you can open the completed project instead of running synthesis and implementation. Open the completed project at <Extract_Dir>/Projects/project_TM_cpuEngine_completed. Verifying and Promoting Results of cpuengine 1. Open the Implemented Design view. If you ran synthesis and implementation, the Implementation Completed dialog box displays when implementation completes. a. In the Implemented Completed dialog box, select Open Implemented Design. Team Design Tutorial 23

24 Step 5: Working on cpuengine as Team Member b. Click OK. X-Ref Target - Figure 16 Figure 16: Implementation Completed Dialog Box If you skipped running implementation and opened the project_tm_cpuengine_completed design, or if the Implemented Completed dialog box did not open: a. In the Flow Navigator, click Implemented Design. When the Implemented Design view displays, you can see that the Pblock for cpuengine is relatively full, as shown in green in Figure 17, and the Pblocks for the two usbengine instances are relatively empty. Because the usbengine instances were black boxes, no logic exists for these two blocks in the implemented design. The logic belonging to the top partition is highlighted in yellow in Figure 17, and this logic can be seen in the usbengine Pblocks because it was not restricted from being placed inside of these Pblocks Team Design Tutorial

25 Step 5: Working on cpuengine as Team Member X-Ref Target - Figure 17 Figure 17: Implemented Design View of the cpuengine Project You can use the Highlight Primitives tool to create a highlighted view, as shown in Figure Verify that timing has been met. To do so, examine the Timing Score in the Design Runs view, the details in the Timing Results window, or the Timing Score in the Project Summary window. 3. In the Flow Navigator, click Promote Partition to promote the successful synthesis and implementation results. If the RTL Design view is not opened, you are prompted to open this first. Click OK to open the RTL Design view first. 4. Select only the cpuengine instance in both the synthesis and implementation runs. 5. Set the Promote directories. synth_1: <Extract_Dir>/Promote/cpuEngine/synth_1 impl_1: <Extract_Dir>/Promote/cpuEngine/impl_1 The promote directory used in team design should be a network location or repository that is accessible by all team members. This tutorial changes the default promote location to be in a folder outside of the project directory structure to emulate such a location. 6. Uncheck the Automatically manage Partition action and import location checkbox. Removing this option is not critical to this tutorial, but is recommended for team members in a team design flow. Unchecking this option prevents the tools from automatically importing cpuengine on the next run because the cpuengine team Team Design Tutorial 25

26 Step 5: Working on cpuengine as Team Member member might continue working on this block. These promoted results are imported by the team leader in a later step, but are not imported by the team member who is promoting it. X-Ref Target - Figure 18 Figure 18: Promote settings for cpuengine 7. Click OK to promote the cpuengine partition Team Design Tutorial

27 Step 6: Working on usbengine as Team Member Step 6: Working on usbengine as Team Member In this section, you will repeat the procedure in Step 5 as a team member working on usbengine. If you have multiple processors available, this step can be done in parallel while the cpuengine project is implementing. Adding Sources to usbengine 1. Open the PlanAhead project <Extract_Dir>/Tutorial_Created_Data/ project_tm_usbengine. The current open project can be closed unless you are doing this step in parallel and the cpuengine has not yet finished implementation or has not been promoted. 2. Click the Project Manager view. 3. Select the usbf_bb.v file in the Sources window. This black box module definition is used for the two usbengine instances in the initial project, and will now be replaced with logic. 4. Right-click, and select Remove from Project. 5. Click OK to confirm this action. X-Ref Target - Figure 19 Figure 19: Remove Black Box module usbf_bb.v 6. At the top of the Sources window, click the Add Sources button to open the Add Sources wizard. Alternatively, right-click in the Sources window, and select Add Sources. 7. From the Add Sources wizard, select Add or Create Design Sources. 8. Click Next. 9. Click the Add Directories button, and browse to./sources/hdl/, and select the usbf directory to add the completed sources for the usbengine instance. 10. Click Select. Team Design Tutorial 27

28 Step 6: Working on usbengine as Team Member 11. Verify the directory to be added, and click Finish. Synthesizing and Implementing usbengine 1. In the Flow Navigator, click RTL Design to open the RTL Design view. 2. Verify that the two usbengine instances are no longer black boxes. When the RTL Design view opens you should again receive a message about Undefined Modules Found. However, now the message should only refer to the cpuengine module (or1200_top), which will remain a black box for this project. Click OK on the message. You should now see that the icons in the RTL Netlist window for the two usbengine instances have changed. 3. In the Flow Navigator, click the pull-down menu next to the Synthesis or Implement buttons, and select Specify Partitions. 4. From the Synthesis tab, verify that top is set to Import, and all other partitions are set to Implement. There is no other data to import besides the top level synthesis results because this is the only partition that has been promoted. Note: If the top partition is not set to import for synthesis, top might not have been promoted correctly in the previous steps, or the checkbox Automatically manage Partition action and import location might have been unchecked in the Promote Partition dialog box. If top was not correctly promoted, it cannot be imported at this stage. 5. Click the Implementation tab, verify that all partitions are set to Implement. 6. Click OK to exit the Specify Partitions dialog box. Note: The next two steps can be skipped to save time. Instead of running synthesis and implementation, you can open the completed project at <Extract_Dir>/Projects/project_TM_usbEngine_completed. 7. Optional. In the Flow Navigator, click the green Implement button to synthesize and implement the design. 8. A message reports that synthesis is out-of-date. Click Yes to launch synthesis prior to implementation Team Design Tutorial

29 Step 6: Working on usbengine as Team Member Verifying and Promoting Results of usbengine 1. Open the Implemented Design view. If you ran synthesis and implementation, the Implementation Completed dialog box displays when implementation completes. a. In the Implemented Completed dialog box, select Open Implemented Design. b. Click OK. If you skipped running implementation and opened the project_tm_usbengine_completed design, or if the Implemented Completed dialog box did not open: a. In the Flow Navigator, click Implemented Design. 2. When the Implemented Design view displays, you can that the Pblocks for usbengine0 and usbengine1 are relatively full, as shown in red and blue in Figure 20, and the Pblock for the cpuengine instance is relatively empty. Because the cpuengine instance was a black box, it is expected to be empty. However, some logic can be seen in this region. The logic from the top level partition, as shown in yellow in Figure 20, was not restricted from being placed inside of the cpuengine Pblock. You can use the Highlight Primitives tool to create a highlighted view, as shown in Figure 20. X-Ref Target - Figure 20 Figure 20: Implemented Design View of the usbengine Project 3. Verify that timing as been met. To do so, examine the Timing Score in the Design Runs view, the details of the Timing Results window, or the Timing Score in the Project Summary window. Team Design Tutorial 29

30 Step 6: Working on usbengine as Team Member 4. In the Flow Navigator, click Promote Partition to promote the successful synthesis and implementation results If the RTL Design view is not opened, you are prompted to open this first. Click OK to open the RTL Design view first. 5. Select only the usbengine0 and usbengine1 instances in both the synthesis and implementation runs. 6. Set the promote directories. synth_1: <Extract_Dir>/Promote/usbEngine/synth_1 impl_1: <Extract_Dir>/Promote/usbEngine/impl_1 7. Uncheck Automatically manage Partition action and import location. X-Ref Target - Figure 21 Figure 21: Promote settings for usbengine0 and usbengine1 8. Click OK to promote the usbengine0 and usbengine1 partitions Team Design Tutorial

31 Step 7: Running the Assembly as Team Leader Step 7: Running the Assembly as Team Leader In the previous steps, each team member synthesized, implemented, and promoted a version of their blocks. Now, the team leader can assemble the design. The team leader reopens the team leader project and sets up the partitions for import. Setting Up the Team Leader Project To Do an Assembly Run 1. Reopen the <Extract_Dir>/Projects/project_TL project. This project is the original project, which should already have the team member partitions defined, the successful synthesis results of top, and the Pblocks for the team member blocks. 2. Update the project to define the team member blocks as logic instead of black boxes. To do this, add the successful synthesis results (NGC) from each team member s promoted synthesis run. a. From the Project Manager, click the Add Sources button at the top of the Sources window. b. Select Add or Create Design Sources. c. Click Next. d. Select Add Files and add the following files: <Extract_Dir>/Promote/usbEngine/synth_1/usbEngine0#usbf_top.ngc <Extract_Dir>/Promote/usbEngine/synth_1/usbEngine1#usbf_top.ngc <Extract_Dir>/Promote/cpuEngine/synth_1/cpuEngine#or1200_top.ngc e. Click Finish. Team Design Tutorial 31

32 Step 7: Running the Assembly as Team Leader X-Ref Target - Figure 22 Figure 22: Add Post Synthesis Results for Team Member Partitions 3. In the Flow Navigator, click Netlist Design to open the Netlist Design view. Note that all partitions are now defined for this project, and it is not necessary to rerun synthesis. The latest synthesis results of all team members (including the team leader) are used for this assembly run Team Design Tutorial

33 Step 7: Running the Assembly as Team Leader X-Ref Target - Figure 23 Figure 23: Netlist Design With All Partitions Defined, and No Black Boxes Updating Partition Settings and Running the Assembly 1. In the Flow Navigator, click the Implement pull-down menu, and select Specify Partitions to access the Implementation Partition settings. 2. Leave the top partition action as Implement. 3. Change the remaining partition (cpuengine, usbengine0, and usbengine1) actions to Import. 4. Change the Import from field to the location where the team members promoted the implementation results. cpuengine: <Extract_Dir>/Promote/cpuEngine/impl_1 usbengine0: <Extract_Dir>/Promote/usbEngine/impl_1 usbengine1: <Extract_Dir>/Promote/usbEngine/impl_1 Note: Because both usbengine instances were implemented together and promoted together, the Import from location is also the same. Team Design Tutorial 33

34 Step 7: Running the Assembly as Team Leader X-Ref Target - Figure 24 Figure 24: Partition Settings for Assembly run 5. Click OK to accept the Partition Settings. Note: You do not need to run the next step in which you run implementation. To save time, open the completed project at <Extract_Dir>/Projects/project_TL_assembled. 6. Optional. Click Implement in the Flow Navigator to launch implementation and assemble the full design. Verifying and Promoting Results of the Assembly In this design, each team member block is logically isolated from other team member blocks, all the boundaries are registered, and the placement of each team member block was sufficient the first time through. For more complex designs, this assembly run may be the first of many, and the process described in this tutorial may be repeated as necessary. Additionally, each team member project could start to import other team member blocks from this promoted assembly run. This would help interface timing to converge early in the design cycle instead of leaving other team member blocks as black boxes and finding interface timing issues at the end of the design. 1. Open the Implemented Design view. When implementation completes, the Implementation Completed dialog box displays. a. In the Implemented Completed dialog box, select Open Implemented Design. b. Click OK. If you skipped running implementation and opened the project_tl_assembled design, or if the Implemented Completed dialog box did not open: a. In the Flow Navigator, click Implemented Design When the Implemented Design view opens, you can see the entire design. Figure 25 shows an example of this placement. The usbengine instances are highlighted in red and blue, the logic belonging to the top partition is highlighted in yellow, and the cpuengine is highlighted in green. You can use the Highlight Primitives tool to create this highlighted view Team Design Tutorial

35 Step 7: Running the Assembly as Team Leader X-Ref Target - Figure 25 Figure 25: Implemented Design View of the Assembled Design 2. Verify that timing as been met. To do so, examine the Timing Score in the Design Runs view, the details of the Timing Results window, or the Timing Score in the Project Summary window. 3. Verify all team member partitions were imported by looking at the Implemented Partition section of the Project Summary view. X-Ref Target - Figure 26 Figure 26: Partition Summary Section of Project Summary Team Design Tutorial 35

36 Step 7: Running the Assembly as Team Leader 4. In the Flow Navigator, click Promote Partition to promote the successful synthesis and implementation results. If the RTL Design view is not opened, you are prompted to open this first. Click OK to open the RTL Design view first. 5. Select all partitions in both the synthesis and implementation to be promoted. Because the placement of the top partition meets all interface timing, each team member could now begin to import top as well as other team member partitions to maintain this interface timing in all future iterations. 6. Set the promote directories: synth_1: <Extract_Dir>/Promote/TL/synth_1 impl_1: <Extract_Dir>/Promote/TL/impl_1 For this tutorial, the synthesis results for the team leader have not changed from the last time we promoted. However, the team leader might develop additional logic in the top level design in parallel with the other team members. In this case, you would promote synthesis and implementation results at this stage to ensure all team members are working on the latest code. 7. Again, uncheck Automatically manage Partition action and import location. Disabling this option prevents the tools from automatically changing the import locations of the team member partitions to the location they were just promoted to, which is./promote/tl, and instead maintains the locations defined in previous steps. This makes running the assembly step even easier in future iterations Team Design Tutorial

37 Conclusion X-Ref Target - Figure 27 Figure 27: Promote Settings for Assembled Design 8. Click OK to promote the assembled design. Conclusion In this tutorial you used partitions and the Team Design methodology to synthesize and implement a design in multiple parts, and then assembled the full design. You were able to synthesize and implement blocks as black boxes, promote successfully synthesized and implemented partitions to a central repository, and even create PlanAhead projects for each team member to help them get started. This tutorial did not demonstrate the full power of implementing several team member blocks in parallel, but did show how this could be done. Team Design Tutorial 37

38 Conclusion 38 Team Design Tutorial

39 Appendix A Additional Resources Xilinx Resources PlanAhead Documentation ISE Design Suite: Installation and Licensing Guide (UG798): ISE Design Suite 13: Release Notes Guide (UG631): Xilinx Documentation: Xilinx Glossary: Xilinx Support: Video Demonstrations: index.htm PlanAhead User Guide (UG632): PlanAhead_UserGuide.pdf PlanAhead Methodology Guides: dt_planahead_planahead13-2_userguides.htm Hierarchical Design Methodology Guide (UG748) Hierarchical_Design_Methodology_Guide.pdf PlanAhead Tutorials: dt_planahead_planahead13-2_tutorials.htm Design Analysis and Floorplanning for Performance (UG676) PlanAhead_Tutorial_Design_Analysis_Floorplan.pdf Team Design Tutorial 39

40 Appendix A: Additional Resources 40 Team Design Tutorial