The Big Picture: Where are We Now? EEM 486: Computer Architecture. Lecture 3. Designing a Single Cycle Datapath
|
|
- Emil Jennings
- 6 years ago
- Views:
Transcription
1 The Big Picture: Where are We Now? EEM 486: Computer Architecture Lecture 3 The Five Classic Components of a Computer Processor Input Control Memory Designing a Single Cycle path path Output Today s Topic: Design a Single Cycle Processor Lec 32
2 The Big Picture: The Performance Perspective Single-cycle datapath CPI Performance of a machine is determined by: count Clock cycle time Inst Count Clock cycles per instruction Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction Cycle Time All instructions execute in a single cycle of the clock (positive edge to positive edge) Advantage: a great way to learn CPU Unrealistic hardware assumptions, slow clock period Lec 33 Lec 34
3 Single cycle data paths: Assumptions Review: Edge-Triggered D Flip Flops Processor uses synchronous logic design (a clock ) f T 1 MHz 1 µs 1 MHz 1 ns 1 MHz 1 ns 1 GHz 1 ns CLK D Q Value of D is sampled on positive clock edge Q outputs sampled value for rest of cycle All state elements act like positive edge-triggered flip flops Clocks arrive at all flip flops simultaneously clk D Q Lec 35 D Q Lec 36
4 How to Design a Processor: Step-by-Step 1 Analyze instruction set => datapath requirements Meaning of each instruction is given by the register transfers path must include storage element for ISA registers - possibly more path must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting the requirements The MIPS Formats The three instruction formats: R-type I-type J-type op rs rt rd shamt funct op 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 6 bits 5 bits 5 bits bits target address 6 bits bits Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic Lec 37 The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction Lec 38
5 Step 1a: The MIPS-lite Subset for Today Step 1a: Executing MIPS s ADD/SUB addu rd, rs, rt subu rd, rs, rt OR Immediate: ori rt, rs, imm LOAD/STORE Word lw rt, rs, imm sw rt, rs, imm BRANCH beq rs, rt, imm op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 6 bits 5 bits 5 bits bits 6 bits 5 bits 5 bits bits 6 bits 5 bits 5 bits bits 11 6 Fetch Decode Operand Fetch Execute Result Store - Fetch next inst from memory - Get ready for the next instruction opcode rs rt rd shamt funct - Decode fields to get a particular instruction - Retrieve register values (rs, rt) - Perform the operation (add, sub, or, lw, sw, beq) - Place the result in a register (rt/rd) / memory, or modify PC Lec 39 Lec 31
6 Step 1a: Logical Register Transfers Step 1: Requirements of the Set RTL gives the meaning of the instructions All start by fetching the instruction inst op rs rt rd shamt funct = MEM[ PC ] op rs rt Imm = MEM[ PC ] Register Transfers ADDU R[rd] < R[rs] + R[rt]; PC < PC + 4 SUBU R[rd] < R[rs] R[rt]; PC < PC + 4 ORi R[rt] < R[rs] zero_ext(imm); PC < PC + 4 LOAD R[rt] < MEM[ R[rs] + sign_ext(imm)]; PC < PC + 4 STORE MEM[ R[rs] + sign_ext(imm) ] < R[rt]; PC < PC + 4 BEQ if ( R[rs] == R[rt] ) then PC < PC [sign_ext(imm) ] else PC < PC + 4 Memory instruction & data ( x ) read RS read RT Write RT or RD PC Extender Add and Sub registers or register and extended immediate Logical Or of a register and extended immediate Add 4 or extended immediate to PC Lec 311 Lec 312
7 Step 2: Components of the path Combinational Elements Storage Elements Clocking methodology Combinational Logic Elements (Basic Building Blocks) A Adder B Select CarryIn Adder Sum Carry MUX A MUX Y B OP A B Result Lec 313 Lec 314
8 Storage Element: Register (Basic Building Block) Register Similar to the D Flip Flop except - N-bit input and output - Write Enable input Write Enable: - Negated (): Out will not change - Asserted (1): Out becomes In Write Enable In N Out N Storage Element: Register File Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: busw RA (number) selects the register to put on busa (data) RB (number) selects the register to put on busb (data) RW (number) selects the register to be written via busw (data) when Write Enable is 1 RW RA RB Write Enable bit busa busb Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - RA or RB valid => busa or busb valid after access time Lec 315 Lec 3
9 Storage Element: Idealized Memory Clocking Methodology Memory (idealized) One input bus: In One output bus: Out Write Enable Address In Out Setup Hold Don t Care Setup Hold Memory word is selected by: Address selects the word to put on Out Write Enable = 1: address selects the memory word to be written via the In bus Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - Address valid => Out valid after access time Lec 317 All storage elements are clocked by the same clock edge Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF, and we have the usual clock-to-q delay Critical path (longest path through logic) determines length of clock period Lec 318
10 Step 3: Assemble path Meeting Requirements 3a: Overview of the Fetch Unit Register Transfer Requirements path Assembly Fetch Read Operands and Execute Operation The common RTL operations Fetch the : mem[pc] - PC == Program Counter, points to next instruction Update the program counter: - Sequential Code: PC <- PC Branch and Jump: PC <- something else PC Next Address Logic Address Memory Word Lec 319 Lec 32
11 Straight-line Fetch Instr Mem Addr 11 6 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 6 bits 5 bits 5 bits bits op target address 6 bits bits 3b: Add & Subtract R[rd] <- R[rs] op R[rt] Example: addu rd, rs, rt Ra, Rb, and Rw come from instruction s rs, rt, and rd fields ctr and RegWr: control logic produces after decoding the instruction 11 6 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits CLK Address PC PC + 4 PC + 8 IMem[PC] IMem[PC + 4] IMem[PC + 8] busw Rd Rs Rt RegWr Rw Ra Rb -bit busa busb ctr Result Why +4 and not +1? Lec 3 Lec 322
12 How data flows after posedge Register-Register Timing: One complete cycle 4 Adder D PC Q Addr Instr Mem PC Rs, Rt, Rd, Op, Func ctr Old Value -to-q New Value Old Value Old Value Memory Access Time New Value Delay through Control Logic New Value Ra Rb Rw RegFile WE op A L U Control Logic RegWr Old Value New Value busa, B busw busw Old Value Old Value Rd Rs Rt RegWr Rw Ra Rb -bit busa busb Register File Access Time New Value ctr Delay New Value Result Register Write Occurs Here Lec 323 Lec 324
13 3c: Logical Operations with Immediate R[rt] <- R[rs] op ZeroExt[imm] 3d: Load Operations R[rt] <- Mem[R[rs] + SignExt[imm]] Eg: lw rt, rs, imm 6 bits 5 bits 5 bits bits 6 bits 5 bits 5 bits bits Rd Rt RegDst Rs Rt? RegWr busw imm Rw Ra Rb -bit busb ZeroExt busa Src ctr Result Lec 325 Rd Rt RegDst Rs Rt? RegWr busw imm Rw Ra Rb -bit busb Extender busa ExtOp ctr In?? Src MemWr WrEn Adr Memory W_Src Mu x Lec 3
14 3e: Store Operations 3f: The Branch Mem[ R[rs] + SignExt[imm] ] <- R[rt] Eg: sw rt, rs, imm 6 bits 5 bits 5 bits bits 6 bits 5 bits 5 bits bits Rd Rt RegDst Rs Rt RegWr busw imm Rw Ra Rb -bit busb Extender busa ctr In MemWr WrEn Adr Memory W_Src Mu x beq rs, rt, imm mem[pc] Fetch the instruction from memory Equal <- R[rs] == R[rt] Calculate the branch condition if (Equal) Calculate the next instruction s address - PC <- PC ( SignExt(imm) x 4 ) else - PC <- PC + 4 ExtOp Src Lec 327 Lec 328
15 path for Branch Operations Putting it All Together: A Single Cycle path beq rs, rt, imm path generates condition (equal) 6 bits 5 bits 5 bits bits Inst Memory Adr Rs <:25> Rt <:2> Rd <11:15> <:15> Imm <:> 4 imm PC Ext Adder Adder npc_sel PC Inst Address Rs Rt RegWr busa Rw Ra Rb busw -bit busb Cond Equal? imm 4 PC Ext Adder Adder npc_sel PC RegDst Rd Rt 1 Rs Rt RegWr busa busw Rw Ra Rb -bit busb imm Extender Equal 1 ctr = MemWr In WrEn Adr Memory MemtoReg 1 Lec 329 ExtOp Src Lec 33
16 A Single Cycle path An Abstract View of the Critical Path PC 4 Read address memory Add [ ] [ ] [25 ] [2 ] [15 11] [15 ] Control M u x 1 RegDst Branch MemRead MemtoReg Op MemWrite Src RegWrite Read register 1 Read register 2 Write register Write data [5 ] Read data 1 Read data 2 Sign extend Shift left 2 M u x 1 control Add result Zero result Write data M u x 1 Address memory Read data 1 M u x Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: Address Next Address - Address valid => Output valid after access time Ideal Memory PC Rd 5 Rs 5 Rw Ra Rt 5 Rb -bit Imm A B Critical Path (Load Operation) = PC s -to-q + Memory s Access Time + Register File s Access Time + to Perform a -bit Add + Memory Access Time + Setup Time for Register File Write + Clock Skew Address In Ideal Memory Lec 3 Lec 3
17 An Abstract View of the Implementation Steps 4 & 5: Implement the control Address Next Address Ideal Memory PC Rd 5 Rs 5 Rw Ra Rt 5 Rb -bit A B Control Control Signals Conditions Address In Ideal Memory Out Next time path Lec 333 Lec 334
18 Summary 5 steps to design a processor 1 Analyze instruction set => datapath requirements 2 Select set of datapath components & establish clock methodology 3 Assemble datapath meeting the requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic MIPS makes it easier s same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Single cycle datapath => CPI=1, CCT => long Next time: implementing control Lec 335
361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath
361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative
More informationOutline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath
Outline EEL-473 Computer Architecture Designing a Single Cycle path Introduction The steps of designing a processor path and timing for register-register operations path for logical operations with immediates
More informationCOMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The
More informationECE468 Computer Organization and Architecture. Designing a Single Cycle Datapath
ECE468 Computer Organization and Architecture Designing a Single Cycle Datapath ECE468 datapath1 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Input Datapath
More informationCpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath
CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU
More informationCOMP303 Computer Architecture Lecture 9. Single Cycle Control
COMP33 Computer Architecture Lecture 9 Single Cycle Control A Single Cycle Datapath We have everything except control signals (underlined) RegDst busw Today s lecture will look at how to generate the control
More informationCh 5: Designing a Single Cycle Datapath
Ch 5: esigning a Single Cycle path Computer Systems Architecture CS 365 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory path Input Output Today s Topic:
More informationCS 61C: Great Ideas in Computer Architecture Datapath. Instructors: John Wawrzynek & Vladimir Stojanovic
CS 61C: Great Ideas in Computer Architecture Datapath Instructors: John Wawrzynek & Vladimir Stojanovic http://inst.eecs.berkeley.edu/~cs61c/fa15 1 Components of a Computer Processor Control Enable? Read/Write
More informationCS61C : Machine Structures
CS 61C L path (1) insteecsberkeleyedu/~cs61c/su6 CS61C : Machine Structures Lecture # path natomy: 5 components of any Computer Personal Computer -7-25 This week Computer Processor ( brain ) path ( brawn
More informationECE170 Computer Architecture. Single Cycle Control. Review: 3b: Add & Subtract. Review: 3e: Store Operations. Review: 3d: Load Operations
ECE7 Computer Architecture Single Cycle Control Review: 3a: Overview of the Fetch Unit The common operations Fetch the : mem[] Update the program counter: Sequential Code: < + Branch and Jump: < something
More informationReview. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU
CS6C L9 CPU Design : Designing a Single-Cycle CPU () insteecsberkeleyedu/~cs6c CS6C : Machine Structures Lecture #9 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker Review
More informationCS3350B Computer Architecture Winter Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2)
CS335B Computer Architecture Winter 25 Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) Marc Moreno Maza www.csd.uwo.ca/courses/cs335b [Adapted from lectures on Computer Organization and Design,
More informationCS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction
CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock
More information361 control.1. EECS 361 Computer Architecture Lecture 9: Designing Single Cycle Control
36 control. EECS 36 Computer Architecture Lecture 9: Designing Single Cycle Control Recap: The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm6 3 3 26 2 6 op rs rt rd
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17 Single Cycle CPU Datapath CPS today! 2005-10-31 There is one handout today at the front and back of the room! Lecturer PSOE, new dad
More informationEEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control
EEM 48: Computer Architecture Lecture 3 Designing Single Cycle The Big Picture: Where are We Now? Processor Input path Output Lec 3.2 An Abstract View of the Implementation Ideal Address Net Address PC
More informationCPU Organization (Design)
ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1 Guest Lecturer: Sagar Karandikar hfp://inst.eecs.berkeley.edu/~cs61c/ http://research.microsoft.com/apps/pubs/default.aspx?id=212001!
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 25 CPU Design: Designing a Single-cycle CPU Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia T-Mobile s Wi-Fi / Cell phone
More informationLecture #17: CPU Design II Control
Lecture #7: CPU Design II Control 25-7-9 Anatomy: 5 components of any Computer Personal Computer Computer Processor Control ( brain ) This week ( ) path ( brawn ) (where programs, data live when running)
More informationCS 110 Computer Architecture Single-Cycle CPU Datapath & Control
CS Computer Architecture Single-Cycle CPU Datapath & Control Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides
More informationHow to design a controller to produce signals to control the datapath
ECE48 Computer Organization and Architecture Designing Single Cycle How to design a controller to produce signals to control the datapath ECE48. 2--7 Recap: The MIPS Formats All MIPS instructions are bits
More informationinst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I ! Nasty new windows vulnerability!
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I CS61C L18 CPU Design: The Single-Cycle I (1)! 2010-07-21!!!Instructor Paul Pearce! Nasty new windows vulnerability!
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 34 Single Cycle CPU Control I 24-4-16 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia 1.5 Quake?! NBC movie on May 3 rd. Truth stranger
More informationMIPS-Lite Single-Cycle Control
MIPS-Lite Single-Cycle Control COE68: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview Single cycle
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2
CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs6c/ Review:
More informationCS359: Computer Architecture. The Processor (A) Yanyan Shen Department of Computer Science and Engineering
CS359: Computer Architecture The Processor (A) Yanyan Shen Department of Computer Science and Engineering Eecuting R-type Instructions 7 Instructions ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate:
More informationInstructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs61c/fa13. Fall Lecture #18. Warehouse Scale Computer
/29/3 CS 6C: Great Ideas in Computer Architecture Building Blocks for Datapaths Instructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs6c/fa3 /27/3 Fall 23 - - Lecture #8 So5ware Parallel Requests Assigned
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures The Internet is broken?! The Clean Slate team at Stanford wants to revamp the Internet, making it safer (from viruses), more reliable
More informationCS 61C: Great Ideas in Computer Architecture Lecture 12: Single- Cycle CPU, Datapath & Control Part 2
CS 6C: Great Ideas in Computer Architecture Lecture 2: Single- Cycle CPU, Datapath & Control Part 2 Instructor: Sagar Karandikar sagark@eecs.berkeley.edu hbp://inst.eecs.berkeley.edu/~cs6c Midterm Results
More informationMajor CPU Design Steps
Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected
More informationLecture 6 Datapath and Controller
Lecture 6 Datapath and Controller Peng Liu liupeng@zju.edu.cn Windows Editor and Word Processing UltraEdit, EditPlus Gvim Linux or Mac IOS Emacs vi or vim Word Processing(Windows, Linux, and Mac IOS) LaTex
More informationCPU Design Steps. EECC550 - Shaaban
CPU Design Steps 1. Analyze instruction set operations using independent RTN => datapath requirements. 2. Select set of datapath components & establish clock methodology. 3. Assemble datapath meeting the
More informationCS152 Computer Architecture and Engineering Lecture 10: Designing a Single Cycle Control. Recap: The MIPS Instruction Formats
CS52 Computer Architecture and Engineering Lecture : Designing a Single Cycle February 7, 995 Dave Patterson (patterson@cs) and Shing Kong (shing.kong@eng.sun.com) Slides available on http://http.cs.berkeley.edu/~patterson
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures Lecture 26 Single-cycle CPU Control 27-3-2 Exhausted TA Ben Sussman www.icanhascheezburger.com Qutrits Bring Quantum Computers Closer:
More informationinst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 19 CPU Design: The Single-Cycle II & Control !
inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture 9 CPU Design: The Single-Cycle II & Control 2-7-22!!!Instructor Paul Pearce! Dell may have shipped infected motherboards! Dell is warning
More informationCSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade
CSE 141 Computer Architecture Summer Session 1 2004 Lecture 3 ALU Part 2 Single Cycle CPU Part 1 Pramod V. Argade Reading Assignment Announcements Chapter 5: The Processor: Datapath and Control, Sec. 5.3-5.4
More informationFull Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI
CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Full Datapath Branch Target Instruction Fetch Immediate 4 Today s Contents We have looked
More informationWorking on the Pipeline
Computer Science 6C Spring 27 Working on the Pipeline Datapath Control Signals Computer Science 6C Spring 27 MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Imm6 Adder
More informationThe Processor: Datapath & Control
Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control Processor Design Step 3 Assemble Datapath Meeting Requirements Build the
More informationRecap: The MIPS Subset ADD and subtract EEL Computer Architecture shamt funct add rd, rs, rt Single-Cycle Control Logic sub rd, rs, rt
Recap: The MIPS Subset EEL-47 - Computer Architecture Single-Cycle Logic ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm 2 rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits
More informationSingle Cycle CPU Design. Mehran Rezaei
Single Cycle CPU Design Mehran Rezaei What does it mean? Instruction Fetch Instruction Memory clk pc 32 32 address add $t,$t,$t2 instruction Next Logic to generate the address of next instruction The Branch
More informationCS 61C: Great Ideas in Computer Architecture Control and Pipelining
CS 6C: Great Ideas in Computer Architecture Control and Pipelining Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs6c/sp6 Datapath Control Signals ExtOp: zero, sign
More informationUniversity of California College of Engineering Computer Science Division -EECS. CS 152 Midterm I
Name: University of California College of Engineering Computer Science Division -EECS Fall 996 D.E. Culler CS 52 Midterm I Your Name: ID Number: Discussion Section: You may bring one double-sided pages
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1
CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs61c/ Review
More informationMidterm I March 3, 1999 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Spring 1999 John Kubiatowicz Midterm I March 3, 1999 CS152 Computer Architecture and Engineering Your Name: SID
More informationCENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu
CENG 342 Computer Organization and Design Lecture 6: MIPS Processor - I Bei Yu CEG342 L6. Spring 26 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified
More informationChapter 4. The Processor. Computer Architecture and IC Design Lab
Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS
More informationCSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Today s Content
3/6/8 CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Today s Content We have looked at how to design a Data Path. 4.4, 4.5 We will design
More informationDesigning a Multicycle Processor
Designing a Multicycle Processor Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras Multicycle-
More informationEECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction
EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement
More informationCENG 3420 Lecture 06: Datapath
CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference
More informationProcessor (I) - datapath & control. Hwansoo Han
Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two
More informationEECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer
EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM
More informationRecap: A Single Cycle Datapath. CS 152 Computer Architecture and Engineering Lecture 8. Single-Cycle (Con t) Designing a Multicycle Processor
CS 52 Computer Architecture and Engineering Lecture 8 Single-Cycle (Con t) Designing a Multicycle Processor February 23, 24 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs52/
More information361 multipath..1. EECS 361 Computer Architecture Lecture 10: Designing a Multiple Cycle Processor
36 multipath.. EECS 36 Computer Architecture Lecture : Designing a Multiple Cycle Processor Recap: A Single Cycle Datapath We have everything except control signals (underline) Today s lecture will show
More informationMidterm I March 12, 2003 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm I March 2, 2003 CS52 Computer Architecture and Engineering Your Name: SID Number:
More informationSystems Architecture
Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software
More informationLecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang
Lecture 12: Single-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Control unit design Single cycle processor Control unit circuit implementation 2 Computer Organization Computer Processor Memory Devices
More informationCS 152 Computer Architecture and Engineering. Lecture 10: Designing a Multicycle Processor
CS 152 Computer Architecture and Engineering Lecture 1: Designing a Multicycle Processor October 1, 1997 Dave Patterson (http.cs.berkeley.edu/~patterson) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/
More informationCPE 335 Computer Organization. Basic MIPS Architecture Part I
CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s8/index.html CPE232 Basic MIPS Architecture
More informationMidterm I October 6, 1999 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I October 6, 1999 CS152 Computer Architecture and Engineering Your Name: SID
More informationECE468 Computer Organization and Architecture. Designing a Multiple Cycle Controller
ECE468 Computer Organization and Architecture Designing a Multiple Cycle Controller ECE468 multicontroller Review of a Multiple Cycle Implementation The root of the single cycle processor s problems: The
More informationIf you didn t do as well as you d hoped
7/3/5 CS 6C: Great Ideas in Computer Architecture Midterm Results Lecture 2: Single- Cycle CPU, path & Control Part 2 ructor: Sagar Karandikar sagark@eecsberkeleyedu hfp://insteecsberkeleyedu/~cs6c You
More informationCS3350B Computer Architecture Quiz 3 March 15, 2018
CS3350B Computer Architecture Quiz 3 March 15, 2018 Student ID number: Student Last Name: Question 1.1 1.2 1.3 2.1 2.2 2.3 Total Marks The quiz consists of two exercises. The expected duration is 30 minutes.
More informationECE 361 Computer Architecture Lecture 10: Designing a Multiple Cycle Processor
ECE 6 Computer Architecture Lecture : Designing a Multiple Cycle Processor 6 multipath.. Recap: A Single Cycle Datapath We have everything except control signals (underline) RegDst Today s lecture will
More information1048: Computer Organization
48: Compter Organization Lectre 5 Datapath and Control Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A- Introdction In this lectre, we will try to implement simplified IPS which contain emory
More informationThe Processor (1) Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University
The Processor (1) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu Jeong (jinkyu@skku.edu)
More informationAdding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20)
Adding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20) The MIPS jump and link instruction, jal is used to support procedure calls by jumping to jump address (similar to j ) and
More informationCOMPUTER ORGANIZATION AND DESIGN. The Hardware/Software Interface. Chapter 4. The Processor: A Based on P&H
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface Chapter 4 The Processor: A Based on P&H Introduction We will examine two MIPS implementations A simplified version A more realistic pipelined
More informationCS 61C: Great Ideas in Computer Architecture (Machine Structures) Single Cycle MIPS CPU
CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single Cycle MIPS CPU ructors: Randy H Katz David A PaGerson hgp://insteecsberkeleyedu/~cs6c/sp Spring 2 - - Lecture #8 Parallel Requests
More informationThe Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture
The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count
More informationThe MIPS Processor Datapath
The MIPS Processor Datapath Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath
More informationReview: Abstract Implementation View
Review: Abstract Implementation View Split memory (Harvard) model - single cycle operation Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions:
More informationECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller. Review of a Multiple Cycle Implementation
ECE 6 Computer Architecture Lecture : Designing a Multiple Cycle ler 6 multicontroller. Review of a Multiple Cycle Implementation The root of the single cycle processor s problems: The cycle time has to
More informationComputer Science 61C Spring Friedland and Weaver. The MIPS Datapath
The MIPS Datapath 1 The Critical Path and Circuit Timing The critical path is the slowest path through the circuit For a synchronous circuit, the clock cycle must be longer than the critical path otherwise
More informationCSE 141 Computer Architecture Summer Session I, Lecture 3 Performance and Single Cycle CPU Part 1. Pramod V. Argade
CSE 141 Computer Architecture Summer Session I, 2005 Lecture 3 Performance and Single Cycle CPU Part 1 Pramod V. Argade CSE141: Introduction to Computer Architecture Instructor: Pramod V. Argade (p2argade@cs.ucsd.edu)
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified
More informationEECS 151/251A Fall 2017 Digital Design and Integrated Circuits. Instructor: John Wawrzynek and Nicholas Weaver. Lecture 13 EE141
EECS 151/251A Fall 2017 Digital Design and Integrated Circuits Instructor: John Wawrzynek and Nicholas Weaver Lecture 13 Project Introduction You will design and optimize a RISC-V processor Phase 1: Design
More informationChapter 4. The Processor
Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations
More informationLecture 7 Pipelining. Peng Liu.
Lecture 7 Pipelining Peng Liu liupeng@zju.edu.cn 1 Review: The Single Cycle Processor 2 Review: Given Datapath,RTL -> Control Instruction Inst Memory Adr Op Fun Rt
More informationCOMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor? Chapter 4 The Processor 2 Introduction We will learn How the ISA determines many aspects
More informationECE4680. Computer Organization and Architecture. Designing a Multiple Cycle Processor
ECE468 Computer Organization and Architecture Designing a Multiple Cycle Processor ECE468 Multipath. -- Start X:4 op 6 Instr RegDst A Single Cycle Processor busw RegWr Clk Main imm6 Instr Rb -bit
More informationCpE 442. Designing a Multiple Cycle Controller
CpE 442 Designing a Multiple Cycle Controller CPE 442 multicontroller.. Outline of Today s Lecture Recap (5 minutes) Review of FSM control (5 minutes) From Finite State Diagrams to Microprogramming (25
More informationECE4680. Computer Organization and Architecture. Designing a Multiple Cycle Processor
ECE68 Computer Organization and Architecture Designing a Multiple Cycle Processor ECE68 Multipath. -- op 6 Instr RegDst A Single Cycle Processor busw RegWr Main imm6 Instr Rb -bit Registers 6 op
More informationELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control
ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849
More informationECE468. Computer Organization and Architecture. Designing a Multiple Cycle Processor
ECE68 Computer Organization and Architecture Designing a Multiple Cycle Processor ECE68 multipath.. op 6 Instr RegDst A Single Cycle Processor busw RegWr Main imm6 Instr Rb -bit Registers 6 op RegDst
More informationCS 110 Computer Architecture Review Midterm II
CS 11 Computer Architecture Review Midterm II http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides based on UC Berkley's CS61C 1 Midterm II Date:
More informationThe Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined
More informationCS152 Computer Architecture and Engineering. Lecture 8 Multicycle Design and Microcode John Lazzaro (www.cs.berkeley.
CS152 Computer Architecture and Engineering Lecture 8 Multicycle Design and Microcode 2004-09-23 John Lazzaro (www.cs.berkeley.edu/~lazzaro) Dave Patterson (www.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs152/
More informationMidterm I March 1, 2001 CS152 Computer Architecture and Engineering
University of California, Berkeley College of Engineering Computer Science Division EECS Spring 200 John Kubiatowicz Midterm I March, 200 CS52 Computer Architecture and Engineering Your Name: SID Number:
More informationLECTURE 5. Single-Cycle Datapath and Control
LECTURE 5 Single-Cycle Datapath and Control PROCESSORS In lecture 1, we reminded ourselves that the datapath and control are the two components that come together to be collectively known as the processor.
More informationCSE140: Components and Design Techniques for Digital Systems
CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing Announcements and Outline Check webct grades, make sure everything is there and is correct Pick up graded d homework at
More informationSystems Architecture I
Systems Architecture I Topics A Simple Implementation of MIPS * A Multicycle Implementation of MIPS ** *This lecture was derived from material in the text (sec. 5.1-5.3). **This lecture was derived from
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition The Processor - Introduction
More informationChapter 4. Instruction Execution. Introduction. CPU Overview. Multiplexers. Chapter 4 The Processor 1. The Processor.
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor The Processor - Introduction
More informationInitial Representation Finite State Diagram Microprogram. Sequencing Control Explicit Next State Microprogram counter
Control Implementation Alternatives Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently;
More informationFundamentals of Computer Systems
Fundamentals of Computer Systems Single Cycle MIPS Processor Stephen. Edwards Columbia University Summer 26 Illustrations Copyright 27 Elsevier The path The lw The sw R-Type s The beq The Controller Encoding
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle
More information