Fundamentals of Computer Systems
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1 Fundamentals of Computer Systems Single Cycle MIPS Processor Stephen. Edwards Columbia University Summer 26 Illustrations Copyright 27 Elsevier
2 The path The lw The sw R-Type s The beq The Controller Encoding The LU Decoder The Main Decoder The j Processor Performance The Critical Path
3 Let s Build a Simple Processor Supported instructions: R-type: and, or, addu, subu, slt instructions: lw, sw Branch instructions: beq Version 2.: I-type: addiu J-type: j
4 MIPS State Elements This is the programmer-visible state in the IS
5 LU Interface and Implementation N B N N B N LU N Y F2 F F Func. 3 F N N F 2 & B B B & B B B < B (slt) C out Extend N 3 [N-] S N 2 N Y N N 2 F :
6 path Elements for the lw Fetch instruction from instruction memory: Send the to the instruction memory s address lw rt, offset(base) LW base rt offset
7 path Elements for the lw Read the base register 25: lw rt, offset(base) LW base rt offset
8 path Elements for the lw Sign-extend the immediate 25: : lw rt, offset(base) LW base rt offset
9 path Elements for the lw dd the base register and the sign-extended immediate to compute the data memory address LUControl 2: 25: Src SrcB LU LUResult 5: lw rt, offset(base) LW base rt offset
10 path Elements for the lw Read data from memory and write it back to rt in the register file 25:2 2: LUControl 2: Src SrcB LU LUResult Read 5: lw rt, offset(base) LW base rt offset
11 path Elements for the lw dd four to the program counter to determine address of the the next instruction to execute 25:2 2: LUControl 2: Src SrcB LU LUResult Read Plus 5: Result lw rt, offset(base) LW base rt offset
12 dditional Elements for sw Read rt from the register file and write it to data memory 25:2 2:6 2: LUControl 2: Src SrcB LU LUResult Write MemWrite Read Plus 5: Result sw rt, offset(base) SW base rt offset
13 dditional Elements for R-Type s Read from rs and rt Write LUResult to rd (instead of rt) Plus 25:2 2:6 2:6 5: 5: RegDst LUSrc LUControl 2: MemWrite MemtoReg varies WriteReg : SrcB Src LU LUResult Write Read Result addu rd, rs, rt SPECIL rs DDU rt rd
14 dditional Elements for beq Determine whether rs and rt are equal Calculate branch target address Plus 25:2 2:6 2:6 5: 5: RegDst LUSrc LUControl 2: Branch MemWrite MemtoReg x x WriteReg : Src SrcB <<2 LU LUResult Write Branch Src Read Result beq rs, rt, offset BEQ rs rt offset
15 dd a controller to complete it 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Plus 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read Result Op rs Funct
16 R-Type Encoding addu rd, rs, rt SPECIL rs DDU rt rd subu rd, rs, rt SPECIL rs SUBU rt rd and rd, rs, rt SPECIL rs ND rt rd or rd, rs, rt SPECIL rs OR rt rd slt rd, rs, rt SPECIL rs SLT rt rd
17 The LU Decoder Control Unit Opcode 5: Funct 5: Main Decoder LU Decoder LUOp : MemtoReg MemWrite Branch LUSrc RegDst LUControl 2: Part of the control unit responsible for implementing the opcode Funct field. LU Funct LU LU Op Ctrl. Function dd - Subtract - dd - Subtract - ND - OR - Slt
18 The Main Decoder Inst. OP RegDst LUSrc Branch MemWrite MemToReg LUOp R-type lw sw beq 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Plus 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read Result
19 The Main Decoder Inst. OP RegDst LUSrc Branch MemWrite MemToReg LUOp R-type - lw sw beq MemtoReg Control MemWrite Unit Branch LUControl 2: 3:26 Op LUSrc 5: Funct RegDst Src Plus 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read Result
20 The Main Decoder Inst. OP RegDst LUSrc Branch MemWrite MemToReg LUOp R-type - lw sw beq 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Plus 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read Result
21 The Main Decoder Inst. OP RegDst LUSrc Branch MemWrite MemToReg LUOp R-type - lw sw - - beq 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Plus 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read Result
22 The Main Decoder Inst. OP RegDst LUSrc Branch MemWrite MemToReg LUOp R-type - lw sw - - beq - - 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Plus 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read Result
23 The Main Decoder Inst. OP RegDst LUSrc Branch MemWrite MemToReg LUOp R-type - lw sw - - beq - - addiu Can we do this with our datapath? 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Plus 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read Result
24 The Main Decoder Inst. OP RegDst LUSrc Branch MemWrite MemToReg LUOp R-type - lw sw - - beq - - addiu 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Plus 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read Result
25 dditional Elements for the j Inst. OP RegDst LUSrc Branch MemWrite MemToReg LUOp Jump R-type - lw sw - - beq - - addiu j Jump 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Jump Plus 25:2 3 2: :6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Result Read 27: 3:28 25: <<2
26 Processor Performance Seconds Program = s Clock Cycles Program Seconds Clock Cycle Seconds Program s Program Clock Cycles Seconds Clock Cycle How long you have to wait Number that must execute to complete the task CPI: Cycles per instruction The clock period (/frequency)
27 The Critical Path Here: Load from 3:26 5: MemtoReg Control MemWrite Unit Branch LUControl 2: Op Funct LUSrc RegDst Src Plus 3 25:2 2:6 2:6 5: 5: WriteReg : Src SrcB <<2 LU LUResult Write Branch Read to to LU to to Result
28 3:26 5: 25:2 2:6 2:6 5: 5: The Critical Path Dictates the Clock Period Element Delay clk-to-q t pcq- 3 ps setup t setup 2 Multiplexer t mux 25 LU t LU 2 Read t mem 25 file read t RFread 5 file setup t RFsetup 2 Plus MemtoReg Control MemWrite Unit Branch LUControl 2: Op LUSrc Funct RegDst WriteReg : Src LUResult SrcB Write <<2 Branch LU Src Read Result T C = t pcq- t mem-i t RFread t LU t mem-d t mux t RFsetup = ( ) ps = 925 ps =.8 GHz
29 Execution Time for Our Single-Cycle Processor For a billion-instruction task on our single-cycle processor with a 925 ps clock period, Seconds Program = s Clock Cycles Program Seconds Clock Cycle = ps = 92.5 seconds
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