EEC 483 Computer Organization

Transcription

1 EEC 483 Compter Organization Chapter 4.4 A Simple Implementation Scheme Chans Y The Big Pictre The Five Classic Components of a Compter Processor Control emory Inpt path Otpt path & Control 2

2 path and Control path Between memory,, register When a 32-bit instrction is ready It is decoded to obtain opcode, register nmbers, nmbers go to register and the register vales become ready Immediate vale becomes ready emory is read and ready Control Need to decide which inpts shold be sed (mltipleors) control sch as operation, binvert, carryin, signal (register write, memory write) 3 Control Signal When does the contents of state element change? Edge triggered methodology Every inpt to pdate state element mst be stable at the active clock edge Feedback cannot occr within the same clock cycle (no race) If the contents of state element change every clock cycle, it s OK. If not??? We need a write control signal that mst be asserted for a write to occr at the clock edge. => Reg, em, em State element Combinational logic 4 2

3 Generation of Control Signals 32-bit instrction 6-bit opcode Control Logic 9 control signals 5 Control Signals (9) ltipletor selector Src RegDst emtoreg PCSrc control Op Op : second operand for : destination reg. no. for register : destination reg. for reg. :??? (the only eception that cannot be set based on the given instrction) signals Reg : what happen add $s, $s, $s2??? em / em 6 3

4 Signal add $8, $7, $8 op rs rt rd shamt fnct lw $, ($2) op rs rt 6 bit offset ( write reqired) 7 emory (emory read reqired) ( write reqired) Signal sw $, ($2) op rs rt 6 bit offset emory (emory write reqired) 8 4

5 Signal nmbers 5 control 3 register 5 5 register 2 s register 2 Reg add, lw: sw, beq:??? Zero reslt add, lw, sw, beq:??? Address em memory em add, lw, sw, beq:??? What happen before write vale to $ is ready? => need some time to be stabilized => this will be the longest path (critical path) => determines the clock cycle for the CPU 9 Control Signals (9) 3 write signals emto- Reg em em (PCSrc) Instrction RegDst Src Reg Branch Op p R-format lw sw X X beq X X 9 control signals 5

6 IPS Instrction Types add/ sb (destination) reg reg reg 32/34 and/ or slt reg reg reg 36/37 reg reg reg R-type lw sw beq (destination) 35 reg reg address (destination) 43 reg reg address 4 reg reg address I-type ltipleer Selector 4 Add RegDst Branch Shift left 2 Add reslt PCSrc em Instrction [3 26] emtoreg Control Op em Src Reg PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 s register 2 Zero reslt Address memory Instrction [5 ] RegDst Src emtoreg 6 32 Sign etend control Instrction [5 ] 2 6

7 ltipleor Selector Src add: lw: 3 control add: lw: RegDst Inst. : rt => Inst. : 6-bit offset m Zero reslt Inst. : rd Inst. : rt m nmbers register register 2 s register 2 memory m Reg 3 add: lw: emtoreg ltipleer Selector add $8, $7, $8 op rs rt rd shamt fnct lw $, ($2) op rs rt 6 bit offset Src emory In case of sw RegDst emtoreg X (don t care) X (don t care) 4 7

8 One ore ltipleor Selector PC ADD 4 S.E.(6-bit)<<2 ADD PCSrc Branch Zero flag 5 Control Signals (9) 4 mltipleor selectors emto- Reg em em (PCSrc) Instrction RegDst Src Reg Branch Op p R-format lw sw X X beq X X 9 control signals 6 8

9 Control What shold the do with this instrction? Information comes from the 32 bits of the instrction 's operation based on instrction type and fnction code lti-level control (for simplifying control logic) Instrction s opcode (bit3-bit26) => Op & Op (with instrction s fnct (bit4-bit)) => inpts: binvert (= carryin), operation 7 Generation of Control Signals 32-bit instrction 6-bit opcode 6-bit fnc Control Logic 9 control signals OP/ Control 3 control Zero reslt 8 9

10 9 Control control inpts binvert=carryin operation opcode lw 2 <= add for address calclation sw 2 <= add for address calclation beq 2 <= sb for comparison add 2 sb 2 and or slt 3 2

11 Control: lti-level st level control: Instrction s opcode (bit3-bit26) => Op & Op lw () => sw () => Op compted from instrction beq () => type (mltiple levels of control to arithmetic () => redce the size of control nit) 2 nd level control: Op & Op + fnct (bit5-bit) => binvert (=carryin), operation lw/sw beq arithmetic Op Fnct field Operation Op Op F5 F4 F3 F2 F F X X X X X X X X X X X X X X X X X X X X X X X X X X X X add add add () sb () and () or () slt () 2 Implement with gates based on this trth table e.g. bit=a(f3+f) since there is only one for F3 and F Control st describe hardware to compte 4-bit control inpt given instrction type = lw, sw = beq, = arithmetic fnction code for arithmetic Describe it sing a trth table (can trn into gates): Op compted from instrction type 22

12 Control Signals (9) Simple combinational logic (trth tables) Inpts Op control block Op Op Opcode (bit3-26) Op5 Op4 Op3 Op2 Op F (5 ) F3 F2 F F Operation2 Operation Operation Operation Op R-format Iw sw beq Otpts RegDst Src e.g. bit=a(f3+f) emtoreg Reg em em Branch Op OpO 23 Control Signals (9) Add reslt 4 Add RegDst Branch Shift left 2 em Instrction [3 26] emtoreg Control Op em Src Reg PC address Instrction memory Instrction [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] register register 2 s register 2 Zero reslt Address memory Instrction [5 ] 6 32 Sign etend control Instrction [5 ] 24 2

13 Control Signals (9) 4 mltipleor selectors 2 write signals 2 controls emto- Reg em em (PCSrc) Instrction RegDst Src Reg Branch Op p R-format lw sw X X beq X X 9 control signals 25 Or Simple Control Strctre All of the logic is combinational We wait for everything to settle down, and the right thing to be done might not prodce right answer right away we se write signals along with clock to determine when to write Cycle time determined by length of the longest path State element Combinational logic State element 2 Clock cycle We are ignoring some details like setp and hold times 26 3

14 Single Cycle Implementation Calclate cycle time assming negligible delays ecept: memory (2ns), and adders (2ns), register access (ns) PCSrc 4 Add Reg Shift left 2 Add reslt PC address Instrction [3 ] Instrction memory Instrction [25 2] Instrction [2 6] Instrction [5 ] RegDst Instrction [5 ] register register 2 register 2 s 6 Sign 32 etend Src control Zero reslt em Address memory em emtoreg Instrction [5 ] Op 27 Where we are headed Single Cycle Problems: what if we had a more complicated instrction like floating point? wastefl of area (dplicated fnction blocks) One Soltion: se a smaller cycle time have different instrctions take different nmbers of cycles a mlticycle path: PC Address emory Instrction or Instrction register emory register # s # # A B Ot 28 4