# Computer Architecture Experiment

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1 Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1

2 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU Design 3 Pipelined CPU with stall 4 Pipelined CPU with forwarding 5 Pipelined CPU resolving control hazard and support execution 31 MIPS Instructions Architecture Lab_jxh 2 2

3 Outline Experiment Purpose Experiment Task Basic Principle Operating Procedures Precaution Architecture Lab_jxh 3 3

4 Experiment Purpose 1 Understand 31 MIPS instructions. Extend your design to support all the 31 MIPS instructions in pipelined CPU. Architecture Lab_jxh 4 4

5 Experiment Purpose 2 Understand why and when Control Hazards arise Master the methods of resolving Control Hazards Freeze or flush Predict-not-taken Predict-taken Delayed-branch Implement the predict-not-taken scheme in your final pipelined CPU. Write the verification program yourself to test whether it can execute right in both taken and not-taken cases and to test all the 31 instructions. Architecture Lab_jxh 5 5

6 Architecture Lab_jxh 6 Pipelined CPU supporting execution of 31 MIPS instructions MIPS Instructions Bit # Operations R-type op rs rt rd sa func add rs rt rd rd = rs + rt; with overflow PC+=4 addu rs rt rd rd = rs + rt; without overflow PC+=4 sub rs rt rd rd = rs - rt; with overflow PC+=4 subu rs rt rd rd = rs - rt; without overflow PC+=4 and rs rt rd rd = rs & rt; PC+=4 or rs rt rd rd = rs rt; PC+=4 xor rs rt rd rd = rs ^ rt; PC+=4 nor rs rt rd rd = ~(rs rt); PC+=4 slt rs rt rd if(rs < rt)rd = 1; else rd = 0; <(signed) PC+=4 sltu rs rt rd if(rs < rt)rd = 1; else rd = 0; <(unsigned) PC+=4 sll rt rd sa rd = rt << sa; PC+=4 srl rt rd sa rd = rt >> sa (logical); PC+=4 sra rt rd sa rd = rt >> sa (arithmetic); PC+=4 sllv rs rt rd rd = rt << rs; PC+=4 srlv rs rt rd rd = rt >> rs (logical); PC+=4 srav rs rt rd rd = rt >> rs(arithmetic); PC+=4 jr rs PC=rs

7 Pipelined CPU supporting execution of 31 MIPS instructions MIPS Instructions Bit # Operations I-type op rs rt immediate addi rs rt imm rt = rs + (sign_extend)imm; with overflow PC+=4 addiu rs rt imm rt = rs + (sign_extend)imm;without overflow PC+=4 andi rs rt imm rt = rs & (zero_extend)imm; PC+=4 ori rs rt imm rt = rs (zero_extend)imm; PC+=4 xori rs rt imm rt = rs ^ (zero_extend)imm; PC+=4 lui rt imm rt = imm << 16; PC+=4 lw rs rt imm rt = memory[rs + (sign_extend)imm]; PC+=4 sw rs rt imm memory[rs + (sign_extend)imm] <-- rt; PC+=4 beq rs rt imm if (rs == rt) PC+=4 + (sign_extend)imm <<2; PC+=4 bne rs rt imm if (rs!= rt) PC+=4 + (sign_extend)imm <<2; PC+=4 slti rs rt imm sltiu rs rt imm Architecture Lab_jxh 7 if (rs < (sign_extend)imm) rt =1 else rt = 0; less than signed if (rs < (zero_extend)imm) rt =1 else rt = 0; less than unsigned J-type op address j address PC = (PC+4)[31..28],address<<2 jal address PC = (PC+4)[31..28],address<<2 ; \$31 = PC+4 PC+=4 PC+=4

8 Architecture Lab_jxh 8

9 Careful with JAL and LUI Need add data path for JAL and LUI JAL: How many stall? When write R31? What write to R31? Architecture Lab_jxh 9 9

10 Observation Info Input West Button: Step execute South Button: Reset North Button + 4 Slide Button: Register Index East Button: High 16-bit of Reg. Content Sel. Output 0-7 Character of First line: Instruction Code 8 of First line : Space 9-10 of First line : Clock Count 11 of First line : Space of First line : Register Content Second line : stage name / number / type: stage name: 1- f, 2- d, 3- e, 4- m, 5- w (high bits is ignored) Architecture Lab_jxh 1010

11 Precautions 1 According to datapath to modify the modules of top module, then modify the definitions of the modules, then modify the CPU Controller. 2 The signals which transfer from former stage to later stage should be stored to stage registers temporally. 3 Design the program for verification by yourself, includes: Stall Forwarding All kinds of instructions Architecture Lab_jxh 1111

12 Signed and unsigned type Reg and wire are unsigned type Signed type: reg signed wire signed Type conversion \$signed() \$unsiged() Architecture Lab_jxh 1212

13 Submission Lab report 5 named as StID_name_Lab5.doc ( or pdf) All your verilog code, coe file, testing file, etc., in your project directory compacted as StID_name_prj.rar (from Lab 6) Architecture Lab_jxh 1313

14 Thanks! Architecture Lab_jxh 1414

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