Chapter 1 About the Kit Kit Contents Connectivity Getting Help Chapter 2 Architecture of the ADA...

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1 THD-D User Manual 1

2 CONTENTS Chapter 1 bout the Kit Kit Contents Connectivity Getting Help... 9 Chapter 2 rchitecture of the D Chapter 3 Using the D Digital-to-nalog Converter nalog-to-digital Converter oard Components Clock Circuitry Chapter 4 D Demonstration rbitrary Waveform Generator /D and D/ Converter Performance Evaluation Chapter 5 ppendix The Revision History lways Visit Terasic Webpage for New pplications THD-D User Manual 2

3 Chapter 1 bout the Kit The THD_D (D) daughter board is designed to provide DSP solution on DE series and Cyclone III Starter Kit, or other boards with HSMC or GPIO interface. It is equipped with one DC (nalog-to-digital Converter) and DC (Digital-to-nalog Converter) each, to provide dual-channel ports. This chapter provides users key information about the kit. 1.1 Kit Contents Figure 1-1 and Figure 1-2 show the picture of the D-HSMC and D-GPIO package, respectively. The package includes: 1. The Terasic nalog-to-digital and Digital-to-nalog (D) board 2. Complete reference design with source code Figure 1-1 D-HSMC THD-D User Manual 3

4 Figure 1-2 D-GPIO 1.2 Connectivity There are two models available, D-GPIO and D-HSMC, which offer the compatibility of connection to DE2/DE1/DE0/DE2-70 and TR4/DE4/DE3/ DE2-115/DE2i-150/SoCkit/DE1-SoC/Cyclone V Starter Kit/Cyclone III Starter Kit, respectively. THD-D User Manual 4

5 Figure 1-3 Connect D-GPIO with DE2-70 Figure 1-4 Connect D-HSMC with Cyclone III Starter Kit THD-D User Manual 5

6 Figure 1-5 Connect D-HSMC with DE3 (HSTC conector D) (Note, an HFF or SFF adapter card is required in its connection part of the bundled package on the DE3) Figure 1-6 Connect D-HSMC with DE4 (HSMC port ) (Note, an HMF2 adapter card is required in its connection part of the bundled package on the DE4) THD-D User Manual 6

7 Figure 1-7 Connect D-HSMC with DE2-115 Figure 1-8 Connect D-HSMC with C5G(Cyclone V GX Starter Kit) THD-D User Manual 7

8 Figure 1-9 Connect D-HSMC with TR4 (HSMC port ) Figure 1-10 Connect D-HSMC with DE2i-150 THD-D User Manual 8

9 Figure 1-11 Connect D-GPIO with DE1-SoC Figure 1-12 Connect D-HSMC with SoCkit 1.3 Getting Help This chapter describes the architecture of the tpad including block diagram and components. to Taiwan & China: Korea : Japan: THD-D User Manual 9

10 Chapter 2 rchitecture of the D This chapter will illustrate the architecture of the D including device features and applications. The feature set of the D is listed below: 1. Dual D channels with 14-bit resolution and data rate up to 65 MSPS 2. Dual D channels with 14-bit resolution and data rate up to 125 MSPS 3. Dual interfaces include HSMC and GPIO, which are fully compatible with Cyclone III Starter Kit and DE1/DE2/DE2_70/DE2_115/DE3/DE4, respectively 4. Clock sources include oscillator 100MHz, SM for D and D each, and PLL from either HSMC or GPIO interface 5. D converter analog input range 2V p-p range. 6. D converter output voltage range 2V p-p range. 7. D and D converters do not support DC signaling THD-D User Manual 10

11 Chapter 3 Using the D This chapter illustrates some special features of the D including interleaved data mode for digital-to-analog converter and multiplexed data mode for analog-to-digital converter. 3.1 Digital-to-nalog Converter This section will describe the interleaved data mode for D/ converter of the D. The DC integrates two 14-bit TxDC+ cores with dual-port input, while supporting refresh rate up to 125 MSPS. The dual-channel makes it capable of transmitting different data to two separate ports with different update rates. ut it is the interleaving mode that makes it special, especially for processing I and Q data in communication applications. The input data stream is demuxed into its original I and Q data and latched. In the next phase they are converted by the two TxDC+ cores and updated at half the input data rate. Figure 3-1 shows the timing of DC in interleaved mode. THD-D User Manual 11

12 Figure 3-1 Interleaved Mode Timing 3.2 nalog-to-digital Converter This section will describe the multiplexed data mode for /D converter of the D. The DC features dual sample-and-hold amplifiers with data rate up to 65 MSPS at the resolution of 14-bit. Its dual-channel inputs can also operate as two independent ports with different clock rates. ased on the state of the MUX option, multiplexed data output can be achieved by mixing data from the dual ports and the data rate is twice the sample rate. Figure 3-2 shows the multiplexed data format using the channel output and the same clock tied to clock inputs of port and, and the selection of MUX option. THD-D User Manual 12

13 Figure 3-2 Multiplexed Data Format using the Channel Output 3.3 oard Components This section illustrates the detailed information of the connector interfaces and pin mapping tables of the D daughter board. The clock, control, and data signals of the D daughter board are connected to the HSMC or GPIO connector. The tables below list the pin no. of the HSMC and GPIO connector. Pin No. Schematic Description GPIO 0 (J7) Name 1 DC_OTR /D Out-of-Range Indicator Channel 2 DC_D0 /D Data Output bit 0 Channel 3 DC_OTR /D Out-of-Range Indicator Channel 4 DC_D1 /D Data Output bit 1 Channel 5 DC_D2 /D Data Output bit 2 Channel 6 DC_D4 /D Data Output bit 4 Channel 7 DC_D3 /D Data Output bit 3 Channel 8 DC_D5 /D Data Output bit 5 Channel 9 DC_D6 /D Data Output bit 6 Channel 10 DC_D8 /D Data Output bit 8 Channel GND Ground 13 DC_D7 /D Data Output bit 7 Channel 14 DC_D9 /D Data Output bit 9 Channel 15 DC_D10 /D Data Output bit 10 Channel 16 DC_D12 /D Data Output bit 12 Channel 17 DC_D11 /D Data Output bit 11 Channel 18 DC_D13 /D Data Output bit 13 Channel THD-D User Manual 13

14 19 PLL_OUT_DC0 PLL Clock input Channel 20 DC_D0 /D Data Output bit 0 Channel 21 PLL_OUT_DC1 PLL Clock input Channel 22 DC_D1 /D Data Output bit 1 Channel 23 DC_D2 /D Data Output bit 2 Channel 24 DC_D4 /D Data Output bit 4 Channel 25 DC_D3 /D Data Output bit 3 Channel 26 DC_D5 /D Data Output bit 5 Channel 27 DC_D6 /D Data Output bit 6 Channel 28 DC_D8 /D Data Output bit 8 Channel 29 VCC3 3.3V Power 30 GND Ground 31 DC_D7 /D Data Output bit 7 Channel 32 DC_D9 /D Data Output bit 9 Channel 33 DC_D10 /D Data Output bit 10 Channel 34 DC_D12 /D Data Output bit 12 Channel 35 DC_D11 /D Data Output bit 11 Channel 36 DC_D13 /D Data Output bit 13 Channel 37 POWER_ON Power-Down Function for Channel & 38 DC_OE /D Output Enable Pin for Channel DC_OE /D Output Enable Pin for Channel Pin No. Schematic Description GPIO 1 (J8) Name 1 SM_DC4 SM D/ External Clock Input (J5) 2 DC_D13 D/ Data bit 13 Channel 3 OSC_SM_DC4 SM /D External Clock Input (J5) or 100MHz Oscillator Clock Input 4 DC_D12 D/ Data bit 12 Channel 5 DC_D11 D/ Data bit 11 Channel 6 DC_D9 D/ Data bit 9 Channel 7 DC_D10 D/ Data bit 10 Channel 8 DC_D8 D/ Data bit 8 Channel 9 DC_D7 D/ Data bit 7 Channel 10 DC_D5 D/ Data bit 5 Channel GND Ground 13 DC_D6 D/ Data bit 6 Channel 14 DC_D4 D/ Data bit 4 Channel 15 DC_D3 D/ Data bit 3 Channel 16 DC_D1 D/ Data bit 1 Channel 17 DC_D2 D/ Data bit 2 Channel THD-D User Manual 14

15 18 DC_D0 D/ Data bit 0 Channel 19 PLL_OUT_DC0 PLL Clock Input Channel 20 DC_WRT Input Write Signal Channel 21 PLL_OUT_DC1 PLL Clock Input Channel 22 DC_D13 D/ Data bit 13 Channel DC_D12 D/ Data bit 12 Channel 25 DC_D11 D/ Data bit 11 Channel 26 DC_D9 D/ Data bit 9 Channel 27 DC_D10 D/ Data bit 10 Channel 28 DC_D8 D/ Data bit 8 Channel 29 VCC3 3.3V Power 30 GND Ground 31 DC_D5 D/ Data bit 5 Channel 32 DC_D7 D/ Data bit 7 Channel 33 DC_D4 D/ Data bit 4 Channel 34 DC_D6 D/ Data bit 6 Channel 35 DC_D1 D/ Data bit 1 Channel 36 DC_D3 D/ Data bit 3 Channel 37 DC_D0 D/ Data bit 0 Channel 38 DC_D2 D/ Data bit 2 Channel 39 DC_WRT Input Write Signal Channel 40 DC_MODE Mode Select. 1=dual port, 0=interleaved Pin No. D HSMC Pin No. HSMC Pin No. HSTC (DE3 Schematic Name Description (J9) only) PLL_OUT_D PLL Clock Input Channel C D_OTR /D Out-of-Range Indicator Channel PLL_OUT_D PLL Clock input Channel C D_OTR /D Out-of-Range Indicator Channel D_D0 /D Data Output bit 0 Channel D_D0 /D Data Output bit 0 Channel D_D1 /D Data Output bit 1 Channel D_D1 /D Data Output bit 1 Channel THD-D User Manual 15

16 D_D2 /D Data Output bit 2 Channel D_D2 /D Data Output bit 2 Channel D_D3 /D Data Output bit 3 Channel D_D3 /D Data Output bit 3 Channel D_D4 /D Data Output bit 4 Channel D_D4 /D Data Output bit 4 Channel D_D5 /D Data Output bit 5 Channel D_D5 /D Data Output bit 5 Channel D_D6 /D Data Output bit 6 Channel D_D6 /D Data Output bit 6 Channel D_D7 /D Data Output bit 7 Channel D_D7 /D Data Output bit 7 Channel D_D8 /D Data Output bit 8 Channel D_D8 /D Data Output bit 8 Channel D_D9 /D Data Output bit 9 Channel D_D9 /D Data Output bit 9 Channel D_D10 /D Data Output bit 10 Channel D_D10 /D Data Output bit 10 Channel D_D11 /D Data Output bit 11 Channel D_D11 /D Data Output bit 11 Channel D_D12 /D Data Output bit 12 Channel D_D12 /D Data Output bit 12 Channel D_D13 /D Data Output bit 13 Channel THD-D User Manual 16

17 D_D13 /D Data Output bit 13 Channel DC_OE /D Output Enable Pin for Channel DC_OE /D Output Enable Pin for Channel PLL_OUT_D PLL Clock Input Channel C SM_DC4 SM D/ External Clock Input (J5) PLL_OUT_D PLL Clock Input Channel C OSC_SM_ DC4 SM /D External Clock Input (J5) or 100MHz Oscillator Clock Input D_MODE Mode Select. 1=dual port, 0=interleaved D_WRT Input Write Signal Channel D_WRT Input Write Signal Channel D_D13 D/ Data bit 13 Channel D_D13 D/ Data bit 13 Channel D_D12 D/ Data bit 12 Channel D_D12 D/ Data bit 12 Channel D_D11 D/ Data bit 11 Channel D_D11 D/ Data bit 11 Channel D_D10 D/ Data bit 10 Channel D_D10 D/ Data bit 10 Channel D_D9 D/ Data bit 9 Channel D_D9 D/ Data bit 9 Channel D_D8 D/ Data bit 8 Channel D_D8 D/ Data bit 8 Channel D_D7 D/ Data bit 7 Channel D_D7 D/ Data bit 7 Channel D_D6 D/ Data bit 6 Channel D_D6 D/ Data bit 6 Channel D_D5 D/ Data bit 5 Channel D_D5 D/ Data bit 5 Channel D_D4 D/ Data bit 4 Channel D_D4 D/ Data bit 4 Channel D_D3 D/ Data bit 3 Channel D_D3 D/ Data bit 3 Channel D_D2 D/ Data bit 2 Channel D_D2 D/ Data bit 2 Channel D_D1 D/ Data bit 1 Channel D_D1 D/ Data bit 1 Channel D_D0 D/ Data bit 0 Channel THD-D User Manual 17

18 D_D0 D/ Data bit 0 Channel POWER_ON Power-Down Function for Channel & TDO_TDI JTG TDO_TDI JTG ID_I2CDT I2C EEPROM serial address/data I/O ID_I2CSCL I2C EEPROM serial clock 3.4 Clock Circuitry This section describes the board s clock inputs and outputs The clock sources available on the D daughter board include the 100MHz oscillator, external SM clock input, and the PLL clock input from either HSMC or GPIO interface. Each channel of the D and D converter has the selection of choosing one of the clock sources (oscillator, SM, and PLL) corresponding to the CLK SEL jumper of the D daughter board. Figure 3-3 D Clock System THD-D User Manual 18

19 Chapter 4 D Demonstration This chapter illustrates how to setup the D kit as an arbitrary waveform generator and evaluate the performance of /D and D/ converter. 4.1 rbitrary Waveform Generator This section illustrates the implementation of random waveform generator using D. For Terasic mainboards with more than one HSMC connector, please refer to the table below for recommended connection. Terasic Mainboard DE3 DE4 TR4 Reference Figure 1-5 Connect D-HSMC with DE3 (HSTC conector D) Figure 1-6 Connect D-HSMC with DE4 (HSMC port ) Figure 1-9 Connect D-HSMC with TR4 (HSMC port ) Figure 4-1 is the complete setup of an D connected on DE3. Simply perform the following steps to display any pattern generated from PC-based GUI on an oscilloscope. The <path> is the directory where you copy the reference design folder, DE3_D, from CD to your PC. THD-D User Manual 19

20 Figure 4-1 Configuration Setup of Random Waveform Generator on DE3 Configuring the oard: 1. Connect the D-HSMC to DE3, as shown in Figure Use a SM cable to connect D-Channel with an oscilloscope.. 3. For DC clock, add a jumper to JP5 with pins labeled PLL. 4. Use a US cable to connect DE3 with PC 5. Power-on DE3 6. Open DE3_D.qsf from <path>\demonstrations\de3_d 7. Open Quartus Programmer from Tools -> Programmer 8. Press Start on the left-hand side. Starting PC-ased Graphical User Interface: 1. Open D_Utility.exe from <path>\d_utility (If you are using Cyclone III Starter oard, please first run the Q3_D.bat file) THD-D User Manual 20

21 2. Use your mouse to draw a custom waveform from left to right. You may drag it or add more points to be sampled later on. 3. Set the frequency and the amplitude. 4. Press Start 5. Press uto set on the oscilloscope if necessary. Figure 4-2 Pattern generated from DC Channel- is displayed on an oscilloscope 4.2 /D and D/ Converter Performance Evaluation This section illustrates the steps to evaluate the performance of /D and D/ converter on D, based on the data collected from DE2-70. Similar steps can also be applied to DE2-115/DE2/DE1 or DE4/Cyclone III Starter Kit. The <path> is the directory where you copy the reference design folder, DE2_70_D, from CD to your PC. THD-D User Manual 21

22 Figure 4-3 Connect D-GPIO with DE2-70 Configuring the oard: 1. Connect the D-GPIO to DE2-70, as shown in Figure Use a SM cable to connect D-Channel with D-Channel. 3. Use a US cable to connect DE2-70 with PC 4. dd appropriate jumpers for the mode and the clocks. a. For DC clock, add a jumper to JP5 with pins labeled PLL. b. For DC clock, add a jumper to JP2 with pins labeled PLL. c. For the selection of MUX option, add a jumper to JP3, between pins 1 and Power-on DE Open stp1.stp from <path>\demonstrations\de2_70_d, as shown in Figure 4-4. THD-D User Manual 22

23 Figure 4-4 Connect D-GPIO with DE2-70 Collecting Data Using the SignalTap II Logic nalyzer 1. Click Program Device after Hardware and Device are detected correctly. 2. Click Run nalysis and observe signals DC_D and comb, which shows attenuated and original combinations of two sine waves, respectively. 3. Choose File -> Create/Update -> Create SignalTap II List File and the Quartus II will generate the file stp1_auto_signaltap_0.txt in the project directory. If your Quartus II version is above 9.1, Please click DC_D and right click to select "Create SignalTap II List File" for outputting the List file. s show on the Figure 4-5. THD-D User Manual 23

24 Figure 4-5 Using Quartus 10.0 sp1 SignalTap II to generate the SignalTap II List File nalyzing the Data in the MTL Software 1. Start the MTL software. 2. Make sure the current directory is set to <path>\demonstrations\de2_70_d 3. If you are using the DE1 oard please copy the file nstp_plot.m from <path>\mtl to <path>\demonstrations\de1_d. 4. Type nstp_plot( stp1_auto_signaltap_0.txt ) at the MTL command prompt. The MTL will display normalized FFT plots of DC input and DC output similar to Figure 4-6 and Figure 4-7, respectively. THD-D User Manual 24

25 Figure 4-6 Normalized Spectral Plot of The 14-bit DC Input Data Figure 4-7 Normalized Spectral Plot of The 14-bit DC Output Data THD-D User Manual 25

26 Chapter 5 ppendix 5.1 The Revision History Version V1.0.0 V1.1.0 V1.2.0 V1.2.1 V1.2.2 V1.2.3 V1.2.4 Change Log Initial Version (Preliminary) dd Default Demo for DE1 and DE2 DE4 and DE2-115 Demo added Change Figure Change DC and DC description Update Section 1.2 Connectivity Update Section 1.2 Connectivity 5.2 lways Visit Terasic Webpage for New pplications We will continually provide interesting examples and labs on our D webpage. Please visit for more information. THD-D User Manual 26