HD44780U (LCD-II) A single HD44780U can display up to one 8-character line or two 8-character lines.

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1 H4478U (LC-II) (ot Matrix Liquid Crystal isplay Controller/river) E (Z) '99.9 Rev.. escription The H4478U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RM, character generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver. single H4478U can display up to one 8-character line or two 8-character lines. The H4478U has pin function compatibility with the H4478S which allows the user to easily replace an LC-II with an H4478U. The H4478U character generator ROM is extended to generate dot character fonts and 32 5 dot character fonts for a total of 24 different character fonts. The low power supply (2.7V to 5.5V) of the H4478U is suitable for any portable battery-driven product requiring low power dissipation. Features 5 8 and 5 dot matrix possible Low power operation support: 2.7 to 5.5V Wide range of liquid crystal display driver power 3. to V Liquid crystal drive waveform (One line frequency C waveform) Correspond to high speed MPU bus interface 2 MHz (when V CC = 5V) 4-bit or 8-bit MPU interface enabled 8 8-bit display RM (8 characters max.) 9,92-bit character generator ROM for a total of 24 character fonts 28 character fonts (5 8 dot) 32 character fonts (5 dot)

2 H4478U 64 8-bit character generator RM 8 character fonts (5 8 dot) 4 character fonts (5 dot) 6-common 4-segment liquid crystal display driver Programmable duty cycles /8 for one line of 5 8 dots with cursor / for one line of 5 dots with cursor /6 for two lines of 5 8 dots with cursor Wide range of instruction functions: isplay clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift Pin function compatibility with H4478S utomatic reset circuit that initializes the controller/driver after power on Internal oscillator with external resistors Low power consumption Ordering Information Type No. Package CGROM H4478UFS HC4478U H4478UTF H4478U2FS HC4478U2 H4478U2TF H4478UBxxFS HC4478UBxx H4478UBxxTF Note: xx: ROM code No. FP-8B Chip TFP-8F FP-8B Chip TFP-8F FP-8B Chip TFP-8F Japanese standard font European standard font Custom font 2

3 H4478U H4478U Block iagram OSC OSC2 CL CL2 Reset circuit CL CPG Timing generator M 8 Instruction register (IR) 7 E MPU interface Instruction decoder isplay data RM (RM) 8 8 bits 6-bit shift register Common signal driver COM to COM6 B4 to B to B3 Input/ output buffer 8 7 ata register (R) Busy flag ddress counter bit shift register 4 4-bit latch circuit Segment signal driver LC drive voltage selector SEG to SEG4 GN Character generator RM (CGRM) 64 bytes Character generator ROM (CGROM) 9,92 bits Cursor and blink controller 5 5 Parallel/serial converter and attribute circuit V CC V V2 V3 V4 V5 3

4 H4478U 4 H4478U Pin rrangement (FP-8B) FP-8B (Top view) SEG39 SEG4 COM6 COM5 COM4 COM3 COM2 COM COM COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM B5 B4 B3 B2 SEG22 SEG2 SEG2 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG GN OSC SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 OSC2 V V2 V3 V4 V5 CL CL2 V CC M E B B SEG38

5 H4478U 5 H4478U Pin rrangement (TFP-8F) TFP-8F (Top view) COM6 COM5 COM4 COM3 COM2 COM COM COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM B5 B4 SEG2 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG SEG SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG4 GN OSC OSC2 V V2 V3 V4 V5 CL CL2 V CC M E B B B2 B3

6 H4478U HC4478U Pad Location Coordinates Coordinate Coordinate Pad No. Function X (um) Y (um) Pad No. Function X (um) Y (um) SEG B SEG B SEG B SEG B SEG SEG SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM SEG COM GN SEG OSC SEG OSC SEG V SEG V SEG V SEG V SEG V SEG CL SEG CL SEG V CC SEG M SEG SEG SEG SEG E SEG B SEG B SEG

7 H4478U Pin Functions Signal No. of Lines I/O evice Interfaced with Function I MPU Selects registers. : Instruction register (for write) Busy flag: address counter (for read) : ata register (for write and read) I MPU Selects read or write. : Write : Read E I MPU Starts data read/write. B4 to 4 I/O MPU Four high order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the H4478U. can be used as a busy flag. B to B3 4 I/O MPU Four low order bidirectional tristate data bus pins. Used for data transfer and receive between the MPU and the H4478U. These pins are not used during 4-bit operation. CL O Extension driver Clock to latch serial data sent to the extension driver CL2 O Extension driver Clock to shift serial data M O Extension driver Switch signal for converting the liquid crystal drive waveform to C O Extension driver Character pattern data corresponding to each segment signal COM to COM6 6 O LC Common signals that are not used are changed to non-selection waveforms. COM9 to COM6 are non-selection waveforms at /8 duty factor and COM2 to COM6 are non-selection waveforms at / duty factor. SEG to SEG4 4 O LC Segment signals V to V5 5 Power supply Power supply for LC drive V CC V5 = V (max) V CC, GN 2 Power supply V CC : 2.7V to 5.5V, GN: V OSC, OSC2 2 Oscillation resistor clock When crystal oscillation is performed, a resistor must be connected externally. When the pin input is an external clock, it must be input to OSC. 8

8 H4478U Function escription Registers The H4478U has two 8-bit registers, an instruction register (IR) and a data register (R). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RM (RM) and character generator RM (CGRM). The IR can only be written from the MPU. The R temporarily stores data to be written into RM or CGRM and temporarily stores data to be read from RM or CGRM. ata written into the R from the MPU is automatically written into RM or CGRM by an internal operation. The R is also used for data storage when reading data from RM or CGRM. When address information is written into the IR, data is read and then stored into the R from RM or CGRM by an internal operation. ata transfer between the MPU is then completed when the MPU reads the R. fter the read, data in RM or CGRM at the next address is sent to the R for the next read from the MPU. By the register selector () signal, these two registers can be selected (Table ). Busy Flag (BF) When the busy flag is, the H4478U is in the internal operation mode, and the next instruction will not be accepted. When = and = (Table ), the busy flag is output to. The next instruction must be written after ensuring that the busy flag is. ddress Counter (C) The address counter (C) assigns addresses to both RM and CGRM. When an address of an instruction is written into the IR, the address information is sent from the IR to the C. Selection of either RM or CGRM is also determined concurrently by the instruction. fter writing into (reading from) RM or CGRM, the C is automatically incremented by (decremented by ). The C contents are then output to B to when = and = (Table ). Table Register Selection Operation IR write as an internal operation (display clear, etc.) Read busy flag () and address counter (B to ) R write as an internal operation (R to RM or CGRM) R read as an internal operation (RM or CGRM to R) 9

9 H4478U isplay ata RM (RM) isplay data RM (RM) stores display data represented in 8-bit character codes. Its extended capacity is 8 8 bits, or 8 characters. The area in display data RM (RM) that is not used for display can be used as general data RM. See Figure for the relationships between RM addresses and positions on the liquid crystal display. The RM address ( ) is set in the address counter (C) as hexadecimal. -line display (N = ) (Figure 2) When there are fewer than 8 display characters, the display begins at the head position. For example, if using only the H4478, 8 characters are displayed. See Figure 3. When the display shift operation is performed, the RM address shifts. See Figure 3. C (hexadecimal) High order bits Low order bits Example: RM address 4E C6 C5 C4 C3 C2 C C Figure RM ddress isplay position (digit) RM address (hexadecimal) E 4F Figure 2 -Line isplay isplay position RM address For shift left For shift right 4F Figure 3 -Line by 8-Character isplay Example

10 H4478U 2-line display (N = ) (Figure 4) Case : When the number of display characters is less than 4 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. For example, when just the H4478 is used, 8 characters 2 lines are displayed. See Figure 5. When display shift operation is performed, the RM address shifts. See Figure 5. isplay position RM address (hexadecimal) Figure 4 2-Line isplay isplay position RM address For shift left For shift right Figure 5 2-Line by 8-Character isplay Example

11 H4478U Case 2: For a 6-character 2-line display, the H4478 can be extended using one 4-output extension driver. See Figure 6. When display shift operation is performed, the RM address shifts. See Figure 6. isplay position RM address BC E F B4C 4 4E 4F H4478U display Extension driver display For shift left BC E F B4C 4 4E 4F 5 For shift right BC E B4C 4 4E Figure 6 2-Line by 6-Character isplay Example 2

12 H4478U Character Generator ROM (CGROM) The character generator ROM generates 5 8 dot or 5 dot character patterns from 8-bit character codes (Table 4). It can generate dot character patterns and 32 5 dot character patterns. Userdefined character patterns are also available by mask-programmed ROM. Character Generator RM (CGRM) In the character generator RM, the user can rewrite character patterns by program. For 5 8 dots, eight character patterns can be written, and for 5 dots, four character patterns can be written. Write into RM the character codes at the addresses shown as the left column of Table 4 to show the character patterns stored in CGRM. See Table 5 for the relationship between CGRM addresses and data and display patterns. reas that are not used for display can be used as general data RM. Modifying Character Patterns Character pattern development procedure The following operations correspond to the numbers listed in Figure 7:. etermine the correspondence between character codes and character patterns. 2. Create a listing indicating the correspondence between EPROM addresses and data. 3. Program the character patterns into the EPROM. 4. Send the EPROM to Hitachi. 5. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which is sent to the user. 6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI proceeds at Hitachi. 3

13 H4478U Hitachi User Start Computer processing etermine character patterns Create character pattern listing 5 Create EPROM address data listing 2 Evaluate character patterns Write EPROM 3 No OK? EPROM Hitachi 4 Yes rt work M/T Masking Trial Sample Sample evaluation 6 OK? No Yes Mass production Note: For a description of the numbers used in this figure, refer to the preceding page. Figure 7 Character Pattern evelopment Procedure 4

14 H4478U Programming character patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. The H4478U character generator ROM can generate dot character patterns and 32 5 dot character patterns for a total of 24 different character patterns. Character patterns EPROM address data and character pattern data correspond with each other to form a 5 8 or 5 dot character pattern (Tables 2 and 3). Table 2 Example of Correspondence between EPROM ddress ata and Character Pattern (5 8 ots) EPROM ddress ata LSB O4 O3 O2 O O Cursor position Character code Line position Notes:. EPROM addresses to 4 correspond to a character code. 2. EPROM addresses 3 to specify a line position of the character pattern. 3. EPROM data O4 to O correspond to character pattern data. 4. EPROM data O5 to O7 must be specified as. 5. lit display position (black) corresponds to a. 6. Line 9 and the following lines must be blanked with s for a 5 8 dot character fonts. 5

15 H4478U Handling unused character patterns. EPROM data outside the character pattern area: lways input s. 2. EPROM data in CGRM area: lways input s. (Input s to EPROM addresses H to FFH.) 3. EPROM data used when the user does not use any H4478U character pattern: ccording to the user application, handled in one of the two ways listed as follows. a. When unused character patterns are not programmed: If an unused character code is written into RM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is due to the EPROM being filled with s after it is erased.) b. When unused character patterns are programmed as s: Nothing is displayed even if unused character codes are written into RM. (This is equivalent to a space.) Table 3 Example of Correspondence between EPROM ddress ata and Character Pattern (5 ots) EPROM ddress ata LSB O4 O3 O2 O O Cursor position Character code Line position Notes:. EPROM addresses to 3 correspond to a character code. 2. EPROM addresses 3 to specify a line position of the character pattern. 3. EPROM data O4 to O correspond to character pattern data. 4. EPROM data O5 to O7 must be specified as. 5. lit display position (black) corresponds to a. 6. Line and the following lines must be blanked with s for a 5 dot character fonts. 6

16 H4478U Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: ) Lower 4 Bits Upper 4 Bits xxxx CG RM () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) xxxx () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) Note: The user can specify any pattern for character-generator RM. 7

17 H4478U Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: 2) Lower 4 Bits Upper 4 Bits xxxx CG RM () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) xxxx () xxxx (2) xxxx (3) xxxx (4) xxxx (5) xxxx (6) xxxx (7) xxxx (8) 8

18 H4478U 9 Table 5 Relationship between CGRM ddresses, Character Codes (RM) and Character Patterns (CGRM ata) Character Codes (RM data) CGRM ddress Character Patterns (CGRM data) High Low High Low High Low Character pattern () Cursor position Character pattern (2) Cursor position For 5 8 dot character patterns Notes:. Character code bits to 2 correspond to CGRM address bits 3 to 5 (3 bits: 8 types). 2. CGRM address bits to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at as the cursor display. If the 8th line data is, bits will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRM data bits to 4 (bit 4 being at the left). 4. s shown Table 5, CGRM character patterns are selected when character code bits 4 to 7 are all. However, since character code bit 3 has no effect, the R display example above can be selected by either character code H or 8H. 5. for CGRM data corresponds to display selection and to non-selection. Indicates no effect.

19 H4478U 2 Table 5 Relationship between CGRM ddresses, Character Codes (RM) and Character Patterns (CGRM ata) (cont) Character Codes (RM data) CGRM ddress Character Patterns (CGRM data) High Low High Low High Low Character pattern Cursor position For 5 dot character patterns Notes:. Character code bits and 2 correspond to CGRM address bits 4 and 5 (2 bits: 4 types). 2. CGRM address bits to 3 designate the character pattern line position. The th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the th line data corresponding to the cursor display positon at as the cursor display. If the th line data is, bits will light up the th line regardless of the cursor presence. Since lines 2 to 6 are not used for display, they can be used for general data RM. 3. Character pattern row positions are the same as 5 8 dot character pattern positions. 4. CGRM character patterns are selected when character code bits 4 to 7 are all. However, since character code bits and 3 have no effect, the P display example above can be selected by character codes H, H, 8H, and 9H. 5. for CGRM data corresponds to display selection and to non-selection. Indicates no effect.

20 H4478U Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as RM, CGROM and CGRM. RM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to RM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. Liquid Crystal isplay river Circuit The liquid crystal display driver circuit consists of 6 common signal drivers and 4 segment signal drivers. When the character font and number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output non-selection waveforms. Sending serial data always starts at the display data character pattern corresponding to the last address of the display data RM (RM). Since serial data is latched when the display data character pattern corresponding to the starting address enters the internal shift register, the H4478U drives from the head display. Cursor/Blink Control Circuit The cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will appear with the digit located at the display data RM (RM) address set in the address counter (C). For example (Figure 8), when the address counter is 8H, the cursor position is displayed at RM address 8H. C6 C5 C4 C3 C2 C C C For a -line display isplay position RM address (hexadecimal) For a 2-line display cursor position isplay position RM address (hexadecimal) cursor position Note: The cursor or blinking appears when the address counter (C) selects the character generator RM (CGRM). However, the cursor and blinking become meaningless. The cursor or blinking is displayed in the meaningless position when the C is a CGRM address. Figure 8 Cursor/Blink isplay Example 2

21 H4478U Interfacing to the MPU The H4478U can send data in either two 4-bit operations or one 8-bit operation, thus allowing interfacing with 4- or 8-bit MPUs. For 4-bit interface data, only four bus lines (B4 to ) are used for transfer. Bus lines B to B3 are disabled. The data transfer between the H4478U and the MPU is completed after the 4-bit data has been transferred twice. s for the order of data transfer, the four high order bits (for 8-bit operation, B4 to ) are transferred before the four low order bits (for 8-bit operation, B to B3). The busy flag must be checked (one instruction) after the 4-bit data has been transferred twice. Two more 4-bit operations then transfer the busy flag and address counter data. For 8-bit interface data, all eight bus lines (B to ) are used. E IR7 IR3 BF C3 R7 R3 IR6 IR2 C6 C2 R6 R2 B5 IR5 IR C5 C R5 R B4 IR4 IR C4 C R4 R Instruction register (IR) write Busy flag (BF) and address counter (C) read ata register (R) read Figure 9 4-Bit Transfer Example 22

22 H4478U Reset Function Initializing by Internal Reset Circuit n internal reset circuit automatically initializes the H4478U when the power is turned on. The following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state until the initialization ends (BF = ). The busy state lasts for ms after V CC rises to 4.5 V.. isplay clear 2. Function set: L = ; 8-bit interface data N = ; -line display F = ; 5 8 dot character font 3. isplay on/off control: = ; isplay off C = ; Cursor off B = ; Blinking off 4. Entry mode set: I/ = ; Increment by S = ; No shift Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail to initialize the H4478U. For such a case, initial-ization must be performed by the MPU as explained in the section, Initializing by Instruction. Instructions Outline Only the instruction register (IR) and the data register (R) of the H4478U can be controlled by the MPU. Before starting the internal operation of the H4478U, control information is temporarily stored into these registers to allow interfacing with various MPUs, which operate at different speeds, or various peripheral control devices. The internal operation of the H4478U is determined by signals sent from the MPU. These signals, which include register selection signal (), read/ write signal (), and the data bus (B to ), make up the H4478U instructions (Table 6). There are four categories of instructions that: esignate H4478U functions, such as display format, data length, etc. Set internal RM addresses Perform data transfer with internal RM Perform miscellaneous functions 23

23 H4478U Normally, instructions that perform data transfer with internal RM are used the most. However, autoincrementation by (or auto-decrementation by ) of internal H4478U RM addresses after each data write can lighten the program load of the MPU. Since the display shift instruction (Table ) can perform concurrently with display data write, the user can minimize system development time with maximum programming efficiency. When an instruction is being executed for internal operation, no instruction other than the busy flag/address read instruction can be executed. Because the busy flag is set to while an instruction is being executed, check it to make sure it is before sending another instruction from the MPU. Note: Be sure the H4478U is not in the busy state (BF = ) before sending an instruction from the MPU to the H4478U. If an instruction is sent without checking the busy flag, the time between the first instruction and next instruction will take much longer than the instruction time itself. Refer to Table 6 for the list of each instruc-tion execution time. Table 6 Instructions Code Execution Time (max) (when f cp or Instruction B5 B4 B3 B2 B B escription f OSC is 27 khz) Clear display Return home Entry mode set isplay on/off control Cursor or display shift Function set Set CGRM address Set RM address Read busy flag & address Clears entire display and sets RM address in address counter. Sets RM address in address counter. lso returns display from being shifted to original position. RM contents remain unchanged. I/ S Sets cursor move direction and specifies display shift. These operations are performed during data write and read. C B Sets entire display () on/off, cursor on/off (C), and blinking of cursor position character (B). S/C R/L Moves cursor and shifts display without changing RM contents. L N F Sets interface data length (L), number of display lines (N), and character font (F). CG CG CG CG CG CG Sets CGRM address. CGRM data is sent and received after this setting. Sets RM address. RM data is sent and received after this setting. BF C C C C C C C Reads busy flag (BF) indicating internal operation is being performed and reads address counter contents..52 ms 37 µs 37 µs 37 µs 37 µs 37 µs 37 µs µs 24

24 H4478U Table 6 Instructions (cont) Code Execution Time (max) (when f cp or Instruction B5 B4 B3 B2 B B escription f OSC is 27 khz) Write data to CG or RM Read data from CG or RM Note: Write data Writes data into RM or CGRM. Read data Reads data from RM or CGRM. I/ = : Increment I/ = : ecrement S = : ccompanies display shift S/C = : isplay shift S/C = : Cursor move R/L = : Shift to the right R/L = : Shift to the left L = : 8 bits, L = : 4 bits N = : 2 lines, N = : line F = : 5 dots, F = : 5 8 dots BF = : Internally operating BF = : Instructions acceptable RM: isplay data RM CGRM: Character generator RM CG: CGRM address : RM address (corresponds to cursor address) C: ddress counter used for both and CGRM addresses 37 µs t = 4 µs 37 µs t = 4 µs Execution time changes when frequency changes Example: When f cp or f OSC is 25 khz, µs = 4 µs 25 indicates no effect. fter execution of the CGRM/RM data write or read instruction, the RM address counter is incremented or decremented by. The RM address counter is updated after the busy flag turns off. In Figure, t is the time elapsed after the busy flag turns off until the address counter is updated. Busy signal ( pin) Busy state ddress counter (B to pins) + t Note: t depends on the operation frequency t =.5/(f cp or f OSC ) seconds Figure ddress Counter Update 25

25 H4478U Instruction escription Clear isplay Clear display writes space code 2H (character pattern for character code 2H must be a blank pattern) into all RM addresses. It then sets RM address into the address counter, and returns the display to its original status if it was shifted. In other words, the display disappears and the cursor or blinking goes to the left edge of the display (in the first line if 2 lines are displayed). It also sets I/ to (increment mode) in entry mode. S of entry mode does not change. Return Home Return home sets RM address into the address counter, and returns the display to its original status if it was shifted. The RM contents do not change. The cursor or blinking go to the left edge of the display (in the first line if 2 lines are displayed). Entry Mode Set I/: Increments (I/ = ) or decrements (I/ = ) the RM address by when a character code is written into or read from RM. The cursor or blinking moves to the right when incremented by and to the left when decremented by. The same applies to writing and reading of CGRM. S: Shifts the entire display either to the right (I/ = ) or to the left (I/ = ) when S is. The display does not shift if S is. If S is, it will seem as if the cursor does not move but the display does. The display does not shift when reading from RM. lso, writing into or reading out from CGRM does not shift the display. isplay On/Off Control : The display is on when is and off when is. When off, the display data remains in RM, but can be displayed instantly by setting to. C: The cursor is displayed when C is and not displayed when C is. Even if the cursor disappears, the function of I/ or other specifications will not change during display data write. The cursor is displayed using 5 dots in the 8th line for 5 8 dot character font selection and in the th line for the 5 dot character font selection (Figure 3). B: The character indicated by the cursor blinks when B is (Figure 3). The blinking is displayed as switching between all blank dots and displayed characters at a speed of 49.6-ms intervals when f cp or f OSC is 25 khz. The cursor and blinking can be set to display simultaneously. (The blinking frequency changes according to f OSC or the reciprocal of f cp. For example, when f cp is 27 khz, /27 = ms.) 26

26 H4478U Cursor or isplay Shift Cursor or display shift shifts the cursor position or display to the right or left without writing or reading display data (Table 7). This function is used to correct or search the display. In a 2-line display, the cursor moves to the second line when it passes the 4th digit of the first line. Note that the first and second line displays will shift at the same time. When the displayed data is shifted repeatedly each line moves only horizontally. The second line display does not shift into the first line position. The address counter (C) contents will not change if the only action performed is a display shift. Function Set L: Sets the interface data length. ata is sent or received in 8-bit lengths ( to B) when L is, and in 4-bit lengths ( to B4) when L is.when 4-bit length is selected, data must be sent or received twice. N: Sets the number of display lines. F: Sets the character font. Note: Perform the function at the head of the program before executing any instructions (except for the read busy flag and address instruction). From this point, the function set instruction cannot be executed unless the interface data length is changed. Set CGRM ddress Set CGRM address sets the CGRM address binary into the address counter. ata is then written to or read from the MPU for CGRM. 27

27 H4478U B5 B4 B3 B2 B B Clear display Code B5 B4 B3 B2 B B Return home Code Note: on t care. B5 B4 B3 B2 B B Entry mode set Code I/ S B5 B4 B3 B2 B B isplay on/off control Code C B B5 B4 B3 B2 B B Cursor or display shift Code S/C R/L Note: on t care. B5 B4 B3 B2 B B Function set Code L N F B5 B4 B3 B2 B B Set CGRM address Code Higher order bit Lower order bit Figure Instruction () 28

28 H4478U Set RM ddress Set RM address sets the RM address binary into the address counter. ata is then written to or read from the MPU for RM. However, when N is (-line display), can be H to 4FH. When N is (2-line display), can be H to 27H for the first line, and 4H to 67H for the second line. Read Busy Flag and ddress Read busy flag and address reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction. If BF is, the internal operation is in progress. The next instruction will not be accepted until BF is reset to. Check the BF status before the next write operation. t the same time, the value of the address counter in binary is read out. This address counter is used by both CG and RM addresses, and its value is determined by the previous instruction. The address contents are the same as for instructions set CGRM address and set RM address. Table 7 Shift Function S/C R/L Shifts the cursor position to the left. (C is decremented by one.) Shifts the cursor position to the right. (C is incremented by one.) Shifts the entire display to the left. The cursor follows the display shift. Shifts the entire display to the right. The cursor follows the display shift. Table 8 Function Set No. of N F isplay Lines Character Font uty Factor 5 8 dots /8 5 dots / Remarks dots /6 Cannot display two lines for 5 dot character font Note: Indicates don t care. 29

29 H4478U Cursor 5 8 dot 5 dot lternating display character font character font Cursor display example Blink display example Figure 2 Cursor and Blinking B5 B4 B3 B2 B B Set RM address Code Higher order bit Lower order bit B5 B4 B3 B2 B B Read busy flag and address Code BF Higher order bit Lower order bit Figure 3 Instruction (2) 3

30 H4478U Write ata to CG or RM Write data to CG or RM writes 8-bit binary data to CG or RM. To write into CG or RM is determined by the previous specification of the CGRM or RM address setting. fter a write, the address is automatically incremented or decremented by according to the entry mode. The entry mode also determines the display shift. Read ata from CG or RM Read data from CG or RM reads 8-bit binary data from CG or RM. The previous designation determines whether CG or RM is to be read. Before entering this read instruction, either CGRM or RM address set instruction must be executed. If not executed, the first read data will be invalid. When serially executing read instructions, the next address data is normally read from the second read. The address set instructions need not be executed just before this read instruction when shifting the cursor by the cursor shift instruction (when reading out RM). The operation of the cursor shift instruction is the same as the set RM address instruction. fter a read, the entry mode automatically increases or decreases the address by. However, display shift is not executed regardless of the entry mode. Note: The address counter (C) is automatically incremented or decremented by after the write instructions to CGRM or RM are executed. The RM data selected by the C cannot be read out at this time even if read instructions are executed. Therefore, to correctly read data, execute either the address set instruction or cursor shift instruction (only with RM), then just before reading the desired data, execute the read instruction from the second time the read instruction is sent. B5 B4 B3 B2 B B Write data to CG or RM Code Higher order bits Lower order bits B5 B4 B3 B2 B B Read data from CG or RM Code Higher order bits Lower order bits Figure 4 Instruction (3) 3

31 H4478U Instruction and isplay Correspondence 8-bit operation, 8-digit -line display with internal reset Refer to Table for an example of an 8-digit -line display in 8-bit operation. The H4478U functions must be set by the function set instruction prior to the display. Since the display data RM can store data for 8 characters, as explained before, the RM can be used for displays such as for advertising when combined with the display shift operation. Since the display shift operation changes only the display position with RM contents unchanged, the first display data entered into RM can be output when the return home operation is performed. 4-bit operation, 8-digit -line display with internal reset The program must set all functions prior to the 4-bit operation (Table 2). When the power is turned on, 8-bit operation is automatically selected and the first write is performed as an 8-bit operation. Since B to B3 are not connected, a rewrite is then required. However, since one operation is completed in two accesses for 4-bit operation, a rewrite is needed to set the functions (see Table 2). Thus, B4 to of the function set instruction is written twice. 8-bit operation, 8-digit 2-line display For a 2-line display, the cursor automatically moves from the first to the second line after the 4th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the RM address must be again set after the 8th character is completed. (See Table 3.) Note that the display shift operation is performed for the first and second lines. In the example of Table 3, the display shift is performed when the cursor is on the second line. However, if the shift operation is performed when the cursor is on the first line, both the first and second lines move together. If the shift is repeated, the display of the second line will not move to the first line. The same display will only shift within its own line for the number of times the shift is repeated. Note: When using the internal reset, the electrical characteristics in the Power Supply Conditions Using Internal Reset Circuit table must be satisfied. If not, the H4478U must be initialized by instructions. See the section, Initializing by Instruction. 39

32 H4478U Table 8-Bit Operation, 8-igit -Line isplay Example with Internal Reset Step Instruction No. B5 B4 B3 B2 B B isplay Operation Power supply on (the H4478U is initialized by the internal reset circuit) 2 Function set 3 isplay on/off control 4 Entry mode set 5 Write data to CGRM/RM 6 Write data to CGRM/RM H_ HI_ Initialized. No display. Sets to 8-bit operation and selects -line display and 5 8 dot character font. (Number of display lines and character fonts cannot be changed after step #2.) Turns on display and cursor. Entire display is in space mode because of initialization. Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the /CGRM. isplay is not shifted. Writes H. RM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right. Writes I. 7 8 Write data to CGRM/RM 9 Entry mode set Write data to CGRM/RM HITCHI_ HITCHI_ ITCHI _ Writes I. Sets mode to shift display at the time of write. Writes a space. 4

33 H4478U Table 8-Bit Operation, 8-igit -Line isplay Example with Internal Reset (cont) Step Instruction No. B5 B4 B3 B2 B B isplay Operation Write data to CGRM/RM 2 3 Write data to CGRM/RM 4 Cursor or display shift 5 Cursor or display shift 6 Write data to CGRM/RM 7 Cursor or display shift 8 Cursor or display shift 9 Write data to CGRM/RM 2 2 Return home TCHI M_ MICROKO_ MICROKO _ MICROKO _ ICROCO _ MICROCO _ MICROCO_ ICROCOM_ HITCHI _ Writes M. Writes O. Shifts only the cursor position to the left. Shifts only the cursor position to the left. Writes C over K. The display moves to the left. Shifts the display and cursor position to the right. Shifts the display and cursor position to the right. Writes M. Returns both display and cursor to the original position (address ). 4

34 H4478U Table 2 4-Bit Operation, 8-igit -Line isplay Example with Internal Reset Step Instruction No. B5 B4 isplay Operation Power supply on (the H4478U is initialized by the internal reset circuit) 2 Function set 3 Function set 4 isplay on/off control 5 Entry mode set Initialized. No display. Sets to 4-bit operation. In this case, operation is handled as 8 bits by initialization, and only this instruction completes with one write. Sets 4-bit operation and selects -line display and 5 8 dot character font. 4-bit operation starts from this step and resetting is necessary. (Number of display lines and character fonts cannot be changed after step #3.) Turns on display and cursor. Entire display is in space mode because of initialization. Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the /CGRM. isplay is not shifted. 6 Write data to CGRM/RM H_ Note: The control is the same as for 8-bit operation beyond step #6. Writes H. The cursor is incremented by one and shifts to the right. 42

35 H4478U Table 3 8-Bit Operation, 8-igit 2-Line isplay Example with Internal Reset Step Instruction No. B5 B4 B3 B2 B B isplay Operation Power supply on (the H4478U is initialized by the internal reset circuit) Initialized. No display. 2 Function set 3 isplay on/off control 4 Entry mode set 5 Write data to CGRM/RM H_ Sets to 8-bit operation and selects 2-line display and 5 8 dot character font. Turns on display and cursor. ll display is in space mode because of initialization. Sets mode to increment the address by one and to shift the cursor to the right at the time of write to the /CGRM. isplay is not shifted. Writes H. RM has already been selected by initialization when the power was turned on. The cursor is incremented by one and shifted to the right. 6 7 Write data to CGRM/RM HITCHI_ Writes I. 8 Set RM address HITCHI _ Sets RM address so that the cursor is positioned at the head of the second line. 43

36 H4478U Table 3 8-Bit Operation, 8-igit 2-Line isplay Example with Internal Reset (cont) Step Instruction No. B5 B4 B3 B2 B B isplay Operation 9 Write data to CGRM/RM Write data to CGRM/RM 2 Entry mode set 3 Write data to CGRM/RM 4 5 Return home HITCHI M_ HITCHI MICROCO_ HITCHI MICROCO_ ITCHI ICROCOM_ HITCHI _ MICROCOM Writes M. Writes O. Sets mode to shift display at the time of write. Writes M. isplay is shifted to the left. The first and second lines both shift at the same time. Returns both display and cursor to the original position (address ). 44

37 H4478U Initializing by Instruction If the power supply conditions for correctly operating the internal reset circuit are not met, initialization by instructions becomes necessary. Refer to Figures 23 and 24 for the procedures on 8-bit and 4-bit initializations, respectively. Power on Wait for more than 5 ms after V CC rises to 4.5 V Wait for more than 4 ms after V CC rises to 2.7 V B5 B4 B3B2 B B BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than 4. ms B5 B4 B3 B2 B B BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than µs B5 B4 B3 B2 BB BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) B5 B4 B3 N B2 B B F I/ S BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 6.) Function set (Interface is 8 bits long. Specify the number of display lines and character font.) The number of display lines and character font cannot be changed after this point. isplay off isplay clear Entry mode set Initialization ends Figure 23 8-Bit Interface 45

38 H4478U Power on Wait for more than 5 ms after V CC rises to 4.5 V Wait for more than 4 ms after V CC rises to 2.7 V B5 B4 BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than 4. ms B5 B4 BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) Wait for more than µs B5 B4 BF cannot be checked before this instruction. Function set (Interface is 8 bits long.) N F B5 B4 I/ S BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 6.) Function set (Set interface to be 4 bits long.) Interface is 8 bits in length. Function set (Interface is 4 bits long. Specify the number of display lines and character font.) The number of display lines and character font cannot be changed after this point. isplay off isplay clear Initialization ends Entry mode set Figure 24 4-Bit Interface 46

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