19: I/O Devices: Clocks, Power Management

Transcription

1 19: I/O Devices: Clocks, Power Management Mark Handley Clock Hardware: A Programmable Clock Pulses Counter, decremented on each pulse Crystal Oscillator On zero, generate interrupt and reload from holding register To CPU (interrupt) Holding register (holds programmable initial value) A programmable clock, used to generate clock tick interrupts at the CPU. Clock tick rate is settable by the OS. 1

2 Clocks in Linux Real-Time Clock (RTC) Independent of CPU CPU Cycle Counter (TSC Register) For keeping track of time of day (gettimeofday()) For accurate time measurements Granularity: CPU cycle (e.g. 2GHz) Kernel Clock (Programmable Interval Timer) Each tick: cause timer interrupt at a fixed interval For the kernel to keep track of time Granularity: much larger: in terms of 10 Hz-1000 Hz Realtime Clock Most computers have a battery-powered backup clock, used to maintain time when the machine is powered off. On boot, the backup clock is read by the OS, and the system clock initialized from it. OS provides utilities to set the system clock (and copy this to the backup clock). May also use NTP to automatically set the system clock via the network. 2

3 Clock Software Functions Maintaining the time of day. Preventing processes running longer than they re allowed to. Accounting for CPU usage. Handling the alarm() system call made by user processes. Providing watchdog timers for parts of the OS. Doing profiling, monitoring, statistics gathering. Maintaining Time of Day Increment a counter at each clock tick. Unix: time since 1st Jan Windows: time since 1st Jan Needs more than 32 bits to store. Use a 64 bit counter Store seconds and ticks separately Store ticks since boot time. 3

4 Maintaining Time of Day Unix: realtime clock set to UTC. Converted to localtime when needed based on timezone data and daylight-savings time tables. Windows: realtime clock set to localtime. Converted to UTC when needed. Coordinated Universal Time (UTC) - atomic time roughly equivalent to Greenwich Mean Time (GMT) Process Switching When a process is scheduled, initialize its quantum counter to some multiple of the clock interrupt time. Each clock interrupt, decrement the quantum counter. When counter reaches zero, clock interrupt service routine calls scheduler to make a scheduling decision. 4

5 Clock Software: Alarms Simulating multiple timers with a single kernel clock. Alarms scheduled for 4203, 4207, 4213, 4215, Each clock tick, decrement next signal counter. When counter reaches zero, send first alarm signal, and reset next signal counter from next item in list. Watchdog Timers OS needs the equivalent of alarms for internal tasks. Retransmit a lost network packet. Wait for a device to start up. Similar timer chain used to that for alarms, but instead of sending a signal, a registered function is called. Watchdog reset: When system is performing normally it resets a watchdog timer periodically. If the timer ever goes off, the system has failed seriously in some way. Usually cause the machine to reboot. 5

6 Soft Timers Most systems have a second programmable clock available for timer interrupts. Use can be specified by applications. This is no problems if interrupt frequency is low. If interrupt rate is high, system can livelock. Same problem with high I/O interrupt rates. Soft timers are an attempt to avoid interrupts. Whenever kernel is running, it checks for soft timer expiration before it exits to user mode. No context switch needed. How well this works depends on rate of kernel entry calls (due to system calls, page faults, interrupts, idle loop calls). Soft Timers for Networking Normal way to transmit packets on gigabit ethernet is for the transmit complete interrupt to cause the next packet to be sent to the device. At full speed: One full size packet every 12us. One 64 byte packet every 0.5us. Interrupt takes ~4us (Pentium II) Not atypical for average latency between interrupt and entering kernel to be in range of 2us to 20us. Soft clocks + polling + sending several packets to device at a time is feasible. Can use second hardware timer to bound delay. 6

7 Power Management Power Management Power is becoming a big problem for hardware designers. Long battery lifetime needed for mobile devices. Heat management issues for desktops and servers. OS knows most about what is going on, so is playing an increasing role in power management. Turn off unused peripherals. Reduce performance to conserve power/heat. Monitor batteries, and shutdown safely when needed. 7

8 Disk Power Management Can spin down disk when not in use. Takes time to spin up (annoyed users). Takes power to spin up. OS needs to predict that disk will be idle for more than about 20 seconds before worth powering down. Disk buffering helps a lot. Using a memory filesystem for temporary files (/tmp on Unix) really helps. May be able to signal apps that now is a good time to save because disk is currently spinning. CPU Power Management CPU can be put to sleep if nothing s happening. An interrupt will wake it. OS must be aware that sleep occurred and reset CPU counter-based clocks. CPU clock rate and voltage can be reduced. 50% CPU rate can reduce power to 25% of full power. If CPU is only running at 50% utilization, halving the rate is a big power win. 8

9 ACPI: Advanced Configuration and Power Interface Conceived by Intel, Microsoft, and Toshiba Allow OS-directed Power Management (OSPM) Defines Hardware registers: Implemented in chipset silicon BIOS interfaces: Configuration tables Interpreted executable function interface (Control Methods) Motherboard device enumeration and configuration System and device power states ACPI Thermal Model ACPI Architecture Applications Kernel OS Dependent Application APIs OSPM System Code Device Driver ACPI Driver/ AML Interpreter OS Specific technologies, interfaces, and code. Existing industry standard register interfaces to: CMOS, PIC, PITs,... ACPI Register Interface ACPI Registers ACPI BIOS Interface ACPI BIOS ACPI Table Interface ACPI Tables OS Independent technologies, interfaces, code, and hardware. Platform Hardware BIOS - ACPI Spec Covers this area. - OS specific technology - Hardware/Platform - Provided by ACPI CA 9

10 ACPI Power States G0: Normal running state G1: Sleeping S0:CPU Cache flushed and CPU Halted. CPU and Memory still powered. S1: Not commonly implemented S2:Suspend-to-RAM, aka Standby. Memory powered, but not much else. S3: Suspend-to-Disk, aka Hibernate Memory saved to disk. Almost everything off. G2: Soft Off. Off, but keyboard can initiate boot. G3: Mechanical Off. Really off! Only realtime clock powered. 10