IN THE UNITED STATES PATENT AND TRADEMARK OFFICE PETITION FOR INTER PARTES REVIEW UNDER 35 U.S.C. 311 AND 37 C.F.R

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1 IN THE UNITED STATES PATENT AND TRADEMARK OFFICE In the Inter Partes Review of: Trial Number: To Be Assigned U.S. Patent No. 5,839,108 Filed: June 30, 1997 Issued: November 17, 1998 Inventor(s): Norbert P. Daberko, Richard K. Davis Assignee: e.digital Corporation Title: Flash Memory File System In a Handheld Record and Playback Device Panel: To Be Assigned Mail Stop Inter Partes Review Commissioners for Patents P.O. Box 1450 Alexandria, VA PETITION FOR INTER PARTES REVIEW UNDER 35 U.S.C. 311 AND 37 C.F.R

2 TABLE OF CONTENTS Page I. CERTIFICATION PURSUANT TO 37 C.F.R (A) THE 108 PATENT MAY BE CONTESTED BY PETITIONER... 1 II. MANDATORY NOTICES 37 C.F.R. 42.8(A)(1)... 1 A. 37 C.F.R. 42.8(b)(1): Real Party-In-Interest... 1 B. 37 C.F.R. 42.8(b)(2): Related Matters... 1 C. 37 C.F.R. 42.8(b)(3) and (4): Lead and Back-Up Counsel and Service Information... 2 D. PAYMENT OF FEES 37 C.F.R III. IDENTIFICATION OF CHALLENGE 37 C.F.R (B)... 2 A. 37 C.F.R (b)(1): Claims for Which IPR Is Requested... 2 B. 37 C.F.R (b)(2): The Specific Art and Statutory Ground(s) on Which the Challenge Is Based... 2 C. 37 C.F.R (b)(3): Claim Construction... 3 i. non-volatile, long-term storage medium... 6 ii. a logical link between the previous logical data segment and the new data segment... 7 iii. file system... 9 iv. a path for sequentially accessing the data segments within the primary memory v. industry standard data storage format D. 37 C.F.R (b)(4): How the Claim is Unpatentable E. 37 C.F.R (b)(5): Evidence Supporting Challenge IV. THERE IS A REASONABLE LIKELIHOOD THAT CLAIM 1 IS UNPATENTABLE i-

3 TABLE OF CONTENTS (continued) Page A. Brief Description of the Technology at Issue B. Description of the Alleged Invention of Claim C. Prosecution History D. Claim-By-Claim Explanation of Grounds for Unpatentability and Claim Charts i. Claim 1 Is Obvious Over Yorimoto in View of Watanabe ii. Claim 1 Is Obvious Over Katayama iii. Claim 1 is Obvious Over Katayama in View of Normile ii-

4 Microsemi Corporation ( Microsemi ) requests inter partes review ( IPR ) of claim 1 of U.S. Patent No. 5,839,108 ( the 108 patent ) (Ex. 1004). I. CERTIFICATION PURSUANT TO 37 C.F.R (A) THE 108 PATENT MAY BE CONTESTED BY PETITIONER Microsemi hereby certifies that the 108 patent is available for IPR and Microsemi is not barred or estopped from requesting IPR of claim 1 on the grounds identified herein. Microsemi is not the owner of the 108 patent. Microsemi has not previously filed a civil action challenging the validity of any claims of the 108 patent. Microsemi submits this petition less than one year after first being served with a complaint alleging infringement of the 108 patent. 1 Microsemi also is the sole real party of interest of this petition, and is not in privity with any other party against whom the 108 patent has been asserted. The estoppel provisions of 35 U.S.C. 315(e)(1) do not prohibit this IPR. II. MANDATORY NOTICES 37 C.F.R. 42.8(A)(1) A. 37 C.F.R. 42.8(b)(1): Real Party-In-Interest Microsemi is the real party-in-interest for Petitioner. B. 37 C.F.R. 42.8(b)(2): Related Matters 1 Patent Owner e.digital mailed a request to waive service on March 17, 2015, Microsemi waived service on March 20, 2015 and e.digital filed the waiver on March 24, 2015.

5 e.digital Corporation ( e.digital ) has asserted the 108 patent in e.digital Corp. v. Microsemi Corp., 15-cv-0319 (S.D. Cal.). This case may affect, or be affected by, decisions in this proceeding. C. 37 C.F.R. 42.8(b)(3) and (4): Lead and Back-Up Counsel and Service Information Lead Counsel Mark Itri (Reg. No. 36,171) mitri@mwe.com McDERMOTT WILL & EMERY LLP 4 Park Plaza, Suite 1700 Irvine, CA Telephone: (949) Facsimile: (949) Back-up Counsel Gregory Yoder (Reg. No. 60,994) gyoder@mwe.com McDERMOTT WILL & EMERY LLP 4 Park Plaza, Suite 1700 Irvine, CA Telephone: (949) Facsimile: (949) Microsemi submits a Power of Attorney with this Petition. 37 C.F.R (b). D. PAYMENT OF FEES 37 C.F.R The undersigned authorizes the Office to charge the fee set forth in 37 C.F.R (a) for this Petition to Deposit Account No Review of one claim is requested, thus no excess claim fees are required. The undersigned authorizes payment for any additional fees that may be due in connection with this Petition to be charged to the above-referenced Deposit Account. III. IDENTIFICATION OF CHALLENGE 37 C.F.R (b) A. 37 C.F.R (b)(1): Claims for Which IPR Is Requested Microsemi requests IPR of claim 1 of the 108 patent ( Claim 1 ). B. 37 C.F.R (b)(2): The Specific Art and Statutory Ground(s) on Which the Challenge Is Based 2

6 IPR of Claim 1 is requested in view of the following references 2 : U.S. Pat. No. 4,748,320 to Yorimoto, et al. ( Yorimoto ) (Ex. 1005); filed: Oct. 27, 1986; issued: May 31, 1988; prior art under 35 U.S.C. 102(b). 3 U.S. Pat. No. 5,590,306 to Watanabe, et al. ( Watanabe ) (Ex. 1006); filed: Jul. 20, 1993; issued: Dec. 31, 1996; prior art under 35 U.S.C. 102(e). U.S. Patent No. 6,272,610, to Katayama, et al. ( Katayama ) (Ex. 1005); filed: Mar. 9, 1994; issued: Aug. 7, 2001; prior art under 102(e). Normile, A Tapeless Camcorder, POPULAR SCIENCE, (Feb. 1995), at 42 ( Normile ) (Ex. 1006); published: Feb. 1995; prior art under 102(b) Ground Proposed Statutory Rejections for the 108 patent 1 Claim 1 is obvious under 35 U.S.C. 103(a) over Yorimoto in view of Watanabe. 2 Claim 1 is obvious under 35 U.S.C. 103(a) over Katayama. 3 Claim 1 is obvious under 35 U.S.C. 103(a) over Katayama in view of Normile. C. 37 C.F.R (b)(3): Claim Construction 2 e.digital contends the 108 patent was conceived and reduced to practice no earlier than March 7, Citations to 35 U.S.C. 102 and 103 are to the pre-aia versions. 3

7 Claim 1 must be given its broadest reasonable construction [ BRI ] in light of the specification. 37 C.F.R (b). To determine the meaning of Claim 1, it is appropriate and necessary to consider the 108 patent as well as the specification and prosecution history of its parent U.S. Patent No. 5,787,445 ( the 445 patent ) (Ex. 1008) to which the 108 patent is a continuation-in-part. See, e.g., Omega Eng g, Inc., v. Raytek Corp., 334 F.3d 1314, 1333 (Fed. Cir. 2003) ( Our precedent holds... that an interpretation asserted in the prosecution of a parent application can also affect continuation applications, continuation-in-part applications, and even related continuation-in-part applications arising from the same parent. ); In re Rambus Inc., 694 F.3d 42, 48 (Fed. Cir. 2012) (applying Omega in a reexamination appeal); see also Tempo Lighting, Inc. v. Tivoli, LLC, 742 F.3d 973, 977 (Fed. Cir. 2014) ( [T]he prosecution history... serves as intrinsic evidence for purposes of claim construction. This remains true in construing patent claims before the PTO. ). First, the 108 patent s specification does not describe Claim 1 s subject matter; instead, the disclosures supporting Claim 1 can only be found in the 445 patent (if at all). For instance, the abstract, specification and figures for the 108 patent have no disclosure for key terms in Claim 1 such as cache memory, link(s), linking, and logical link(s). 4

8 Second, the claim terms in question here are also found in the claims of the 445 patent. See Omega, 334 F.3d at ( unless otherwise compelled... the same claim term in the same patent or related patents carries the same construed meaning and applying disclaimer from parent application to continuation-in-part because of a common term in dispute). With the exception of one limitation, 4 each and every element recited in Claim 1 is found in claim 1 of the 445 patent. Third, the patentees never evinced a desire to recapture any claim scope disclaimed in the 445 patent. See, e.g., Hakim v. Cannon Avent Grp., PLC, 479 F.3d 1313, (Fed. Cir. 2007) ( Although a disclaimer made during prosecution can be rescinded... the prosecution history must be sufficiently clear to inform the examiner that the previous disclaimer, and the prior art that it was made to avoid, may need to be re-visited. ). To the contrary, the evidence suggests that the patentees intended for the statements in the 445 patent s specification and prosecution history regarding claim scope to carry forward to the 108 patent with equal force. For instance, the 108 patent s specification endorses the disparagement of prior art found in the 445 patent s specification: The [ 445 patent] also addressed the drawbacks of other prior art methods of file management 4 Claim 1 adds one limitation concerning industry standard data storage format that does not appear in claim 1 of the 445 patent. 5

9 designed specifically for use with flash memory such as the system taught in U.S. Pat. No. 5,404,485 issued to Ban. (Ex at 1:55-58; see also id. at 1:58-2:41 and Ex at 2:41-3:21, wherein the 108 patent and 445 patent specifications identify, word-for-word, the same shortcomings in the prior art.) Furthermore, the patentees made no statements to the examiner during prosecution stating that Claim 1 should carry a broader, or otherwise different, scope than claim 1 of the 445 patent. As a result, the 108 patent was issued without an office action. Having made clear statements regarding the scope of the 445 patent, the patentees should be held to such statements in the construction of the claim in question here, which includes each and every limitation from claim 1 of the 445 patent. In light of the above, Microsemi submits, for purposes of this IPR only, that the BRI of Claim 1 is as follows: i. non-volatile, long-term storage medium The BRI of the term non-volatile, long-term storage medium is memory that holds its data without the need for ongoing power support. This is consistent with the plain and ordinary meaning of the phrase to one of ordinary skill in the art in view of the intrinsic record. Nothing in the intrinsic record limits this claim term to any specific type of non-volatile, long-term storage medium. (Ex at 6 ( [W]hile this invention was motivated by flash memory limitations, the principle is applicable to any type of long term memory medium, and therefore claim 1 has 6

10 not been limited only to flash memory. ).) 5 Instead, consistent with the plain meaning of the term, the 445 patent specification describes that long term media is media where withdrawal of applied power does not result in a loss of data stored therein (Ex at 1:34-35) and provides various examples of long-term storage media that include but are not limited to flash memory, hard disks, floppy disks, tape and CD-ROMs. (Id. at 1:31-33.) ii. a logical link between the previous logical data segment and the new data segment The BRI of the term a logical link between the previous logical data segment and the new data segment is a pointer written to the previous logical data segment that points to the physical location of the new data segment. This is consistent with the plain and ordinary meaning of the phrase to one of ordinary skill in the art in view of the specification, 6 and is supported by the intrinsic record. The 445 patent s specification supports this construction. For example, it equates a logical link to a pointer to the physical location of a data segment by stating that a path for sequentially accessing the data segments which, 5 For all quotes herein, emphases are added unless otherwise noted. 6 Pointers were well-known in the art in the mid-1990s as variables containing memory locations or addresses. (See, e.g., Ex ( pointer.... [A] variable that contains the memory location (address) of some data... ).) 7

11 according to Claim 1, is provided by logical link[s] between data segments is provided by pointers to absolute physical locations within flash memory. (Ex at 6:17-18.) The 445 patent s specification further discloses that the claimed invention requires the use of pointers to the physical location of data segments to provide logical linkage: [I]mplementation of the flash file system requires that each data segment have written to it a header. Within the header in predetermined fields, absolute physical addresses are saved. These addresses are physical locations within flash memory of the next logical data segment. * * * [T]he headers of the present invention are written so as to contain pointers which point to files which a user deems to be logically related to by subject. (Id. at 6:3-8, 17:49-51.) The patentees also made clear that in a write operation (i.e., writing a data segment to non-volatile memory), a logical link pointing to the subsequent data segment is created: In a write operation of a new data segment, a header is placed at the beginning of the segment.... The header also indicates the location of the next logically related and subsequent data segment. (Id. at 4:27-31.) 8

12 Microsemi s construction is further supported by relevant extrinsic evidence, which defines a linked list to be a data structure consisting of a group of nodes connected by pointers to locations in memory and a link to be a memory location or memory address: linked list In programming, a list of nodes or elements of a data structure connected by pointers. * * * link (pointer) A character or group of characters that indicates the storage of an item of data. Thus when a field of an item A in a data structure contains the address of another item B, i.e. of its first word in memory, it contains a link to B.... See also linked list. (Exs. 1010, 1011.) Importantly, neither the 445 patent nor the 108 patent discloses any mechanism for providing a logical link between two data segments other than through a pointer to the physical location from one of the data segments to the other (i.e., a linked list of data segments). Indeed, the patentees explicitly stated in the 445 patent file history that the only way to determine the location of data is to traverse the linked list of data segments. (Ex at 5.) Thus, Microsemi s construction of this term is correct under the BRI standard. iii. file system (1) The preamble of Claim 1 is limiting 9

13 The term file system appears in the preamble of Claim 1. Here, the preamble is limiting for a number of reasons. First, the patentees relied on the preamble during prosecution to distinguish the claimed invention from the prior art. Catalina Mktg. Int l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 808 (Fed. Cir. 2002) ( [C]lear reliance on the preamble during prosecution to distinguish the claimed invention from the prior art transforms the preamble into a claim limitation.... ). During prosecution of the 445 patent, the patentees distinguished prior art references cited by the examiner because they were applicable to data structures and not specifically to file structures : Jeffrey teaches data structures. In contrast, the present invention teaches an operating system using linked lists for file structures. The Office Action has seemingly failed to notice this distinction, and has failed to provide any motivation for treating files structures like data structures. (Ex at 8.) This distinction is captured by the preamble and particularly the preamble term file system indeed, the term file only appears in Claim 1 as part of the file system term. Thus, the patentees arguments to overcome prior art demonstrate their use of the preamble to define... the claimed invention as a method applicable to only file systems, transforming the preamble into a claim limitation. Catalina, 289 F.3d at

14 Consistent with the file history, the 445 patent s specification repeatedly makes clear that aspects of the file system are what differentiate the patent from the prior art: Ban is typical of previous methods of imitating RAM because Ban teaches that manipulation of data cannot be done in flash memory directly. Instead, data is always erased from flash memory, manipulated in RAM, and resaved to physically create a segment of manipulated data that appears in its complete and contiguous form. The present invention, however, realizes that data does not have to be contiguous in order to be readable in a logical or relational order. The present invention claims being able to manipulate data directly in flash memory because the flash file system of the present invention enables data to be read in a logical order regardless of how many segments the file is comprised of, and where these segments are saved in memory. (Ex at 5:55-6:3.) The present invention takes a very different approach to memory management. This new approach, embodied in a method and apparatus, overcomes the significant drawbacks of Ban. This is accomplished by taking advantage of the properties of flash memory, instead of treating them as a liability. To understand the new method, it is necessary to have an understanding of the arrangement of the underlying hardware. The 11

15 apparatus of the present invention is shown in block diagram form in FIG 3A. FIG. 3A is a block diagram of the components of a preferred embodiment of the present invention which utilizes the file system of the present invention. (Id. at 7:62-8:4; 4:53-55.) Second, the patentees repeatedly stress the importance of the file system to their alleged invention, further confirming that the term is limiting. See Rotatable Techs. LLC v. Motorola Mobility LLC, No , 2014 WL , *1 (Fed. Cir. June 27, 2014) ( The specification is replete with references to [preamble term] selectively rotating, underscoring the importance of the feature to the claimed invention. ). For instance, the specifications of the 445 and 108 patents highlight the importance of the term file system by repeatedly characterizing the object of the invention as providing a file system with certain allegedly unique characteristics: Another object of the present invention to provide a file system for non-volatile, long-term storage media which has a low processing overhead requirement, thus increasing data throughput. Another object of this invention to provide a file system which has particular application to the storage medium of flash memory. Another object of the present invention to provide a file system which is significantly fault tolerant. 12

16 (Ex at 3:34-43.) It is an object of the present invention to provide a file system for nonvolatile, long-term storage media which has a low processing overhead requirement, thus increasing data throughput. It is another object of this invention to provide a file system which has particular application to the storage medium of flash memory. It is yet another object of the present invention to provide a file system which is significantly fault tolerant, only losing data stored in a relatively small cache memory if power to the system is interrupted. It is a further object of the invention to provide a file system which does not require significant random access memory (RAM) resources. It is yet another object to provide a file system which further reduces RAM requirements by replacing a memory map with logically linked serial data segments. Another object is to provide a file system which efficiently and transparently erases flash memory in the background to further improve system performance.... Still another object is to provide a file system which uses absolute physical memory addresses to avoid the additional overhead created by memory mapping. (Ex at 3:33-59.) 13

17 The 445 patent s detailed description of the invention goes on to describe [t]he file system of the present invention (id. at 8:33) and that [t]he present invention also provides a file system which appears to have significant RAM resources. (Id. at 8:61-62.) In short, as repeatedly demonstrated in the 108 and 445 patent specifications, the file system term states the framework of the invention, On Demand Mach. Corp. v. Ingram Indus., Inc., 442 F.3d 1331, 1343 (Fed. Cir. 2006), and is thus limiting because it give[s] life, meaning, and vitality to the claims. 7 Catalina, 289 F.3d at 808; see also C.W. Zumbiel Co. v. Kappos, 702 F.3d 1371, 1385 (Fed. Cir. 2012) (applying Catalina under BRI to find the preamble limiting). Therefore, the Board should find the preamble of Claim 1, and specifically the file system term, limiting. (2) The patentees claimed to have invented a file system that does not use file allocation tables (FATs) or memory maps 7 Notably, the preamble of claim 1 of the 445 patent, which is identical to Claim 1, provides the only antecedent basis for the term file system in the bodies of dependent claims 3, 5, 7, and 8, further confirming this term is a limitation. See Catalina, 442 F.3d at 808 (relying on a preamble term for antecedent basis may limit claim scope because it indicates a reliance on both the preamble and claim body to define the claimed invention ). 14

18 The BRI of the term file system is system to organize and keep track of files without using file allocation tables (memory maps). A file system is a term commonly used in the art and generally means a system [] to organize and keep track of files. (Ex ) However, in the 108 and 445 patents, the patentees made clear that they are disclosing a file system that is different than the prior art by both defining it in the 445 patent s specification and clarifying this definition in statements made during prosecution. Consistent with Microsemi s proposed construction, the patentees unambiguously made clear that the file system of the present invention does not use memory maps or file allocation tables (FAT): 8 It is yet another object to provide a file system which further reduces RAM requirements by replacing a memory map with logically linked serial data segments. * * * 8 In re Abbott Diabetes Care Inc., 696 F.3d 1142, 1149 (Fed. Cir. 2012) (holding that, under BRI, the patentees disclaimed an electrochemical sensor with wires because the specification contains only disparaging remarks with respect to the external cables and wires of the prior-art sensors and every embodiment disclosed in the specification shows an electrochemical sensor without external cables or wires ). 15

19 Still another object is to provide a file system which uses absolute physical memory addresses to avoid the additional overhead created by memory mapping. (Ex at 3:47-49, 3:57-59.). Indeed, to illustrate the benefits of avoiding memory maps, the 445 patent s specification repeatedly disparages the teachings of the prior art reference U.S. Patent No. 5,404,485 ( Ban ), which used memory maps: The key feature to recognize is that Ban s method requires indirection through virtual mapping to compensate for the frequent movements of data. The technique apparently enables flash memory to imitate the look of RAM, but at the crippling overhead cost of significant data movement when any modification is made. * * * The objectives of the Ban patent are highly desirable, but implementation using the technique of virtual mapping leaves any system using the Ban method not only vulnerable to significant data loss, but tied to a method which inherently cripples itself with overhead requirements. * * * The present invention takes a very different approach to memory management.... [It] overcomes the significant drawbacks of Ban. (Ex at 7:20-25, 51-55, 62-65; see also Ex at 1:55-2:32 (distinguishing Ban for the same reasons).) 16

20 Furthermore, the patentees confirmed that their invention does not use a FAT (memory map) in statements to the Patent Office during prosecution of the 445 patent: The present invention enables the elimination of a FAT (memory map)... [T]he only way to determine the location of data is to traverse the linked list of data segments. * * * The FAT as described in Jeffrey is the same FAT (or virtual memory map) described in Ban... which the present invention has taken great pains from which to distinguish itself. * * * Unlike Ban, the present invention teaches how data can be manipulated directly... without having to use a FAT. (Ex at 5 (first emphasis original), 6, 8.) See Tempo Lighting, 742 F.3d at 977 (looking to prosecution history for the meaning of a disputed claim term on appeal of an inter partes reexamination, explaining that the prosecution history, while not literally within the patent document, serves as intrinsic evidence for purposes of claim construction and that [t]his remains true in construing patent claims before the PTO. ). Because the patentees made clear that their file system does not use file allocation tables (memory maps), Microsemi s proposed construction of file system, a system to organize and keep track of files without using file allocation tables (memory maps), is the BRI of the term. 17

21 iv. a path for sequentially accessing the data segments within the primary memory The BRI of the term a path for sequentially accessing the data segments within the primary memory is a linked list used instead of a file allocation table (memory map) for sequentially accessing data segments within the primary memory. As an initial matter, throughout the intrinsic record, the patentees made clear that a linked list of data segments is used instead of a FAT (memory map) and indeed enables the elimination of a FAT. See Section III.C.iii, supra. As described above, the patentees explained that logically linked serial data segments replace a memory map, (Ex at 3:47-49), and the linked list of data segments is the only way to determine the location of data (Ex at 5). See Section III.C.iii, supra. Because the linked list is the only way to determine the location of data, it is clearly used instead of a FAT (memory map). Furthermore, in computer science and engineering, elements, such as data segments, that are linked together are called a linked list. (See Ex ( linked list (chained list) A list representation in which items are not necessarily sequential in storage. Access is made possible by the use in every item of a link that contains the address of the next item in the list. ); see also Ex ( linked list In programming, a list of nodes or elements of a data structure connected by 18

22 pointers. ).) Indeed, this is how the patentees referred to the path of data segments in the 445 patent file history: To increase efficiency, the only way to determine the location of data is to traverse the linked list of data segments. The linked list not only tells where the related data segments are located for one file, but it also links the first data segment of all files together. * * * The first file contains an address not only of the next logical data segment, but to the address of the first logical data segment of the second file. Accordingly, the linked lists not only preserve continuity of discontiguous but logically related data segments, they also preserve continuity to previous and subsequent but unrelated files having their own discontiguous but logically related data segments. (Ex at 5-6, 9.) In other words, the patentees explicitly describe the logically connected data segments as a linked list of segments. Thus, consistent with the plain meaning and the intrinsic record, the path for sequentially accessing the data segments is a linked list. In light of the above, the BRI of a path for sequentially accessing the data segments within the primary memory is a linked list used instead of a file allocation table (memory map) for sequentially accessing data segments within the primary memory. v. industry standard data storage format 19

23 The BRI of the term industry standard data storage format is format in which data is stored that conforms to an industry standard. This is consistent with the plain and ordinary meaning of the phrase to one of ordinary skill in the art in view of the specification, and is supported by the 108 patent s specification. By way of example, the 108 patent discusses industry standard formats for recording or storing data in flash memory. (See, e.g., Ex at Abstract ( a flash memory module which can record data according to industry standard formats ), 3:19-21 ( Another object is to enable the flash memory to store data so as to appear readable to industry standard information storage and retrieval operating interfaces and operating systems. ).) The disclosure specifically points to MPEG-2, an industry standard format for storing audio and/or video information. (Id. at 10:53-56 ( The compression algorithm implemented in the present invention can vary as necessary and as technology changes. However, industry standards such as MPEG- 2 can presently be utilized. ).) Nothing in the intrinsic record limits this claim term to any specific type of hardware or interface for retrieving the stored data. Thus, the BRI for this term, in light of the specification, is format in which data is stored that conforms to an industry standard. D. 37 C.F.R (b)(4): How the Claim is Unpatentable An explanation of how construed Claim 1 is unpatentable is in Section III.C. E. 37 C.F.R (b)(5): Evidence Supporting Challenge 20

24 An Appendix of Exhibits is attached. Relevance of the evidence, including identification of the specific portions of the evidence that support the challenge, may be found in Section IV.B. Microsemi submits a declaration of Joseph McAlexander (Ex ) in support of this Petition. (37 C.F.R ) IV. THERE IS A REASONABLE LIKELIHOOD THAT CLAIM 1 IS UNPATENTABLE A. Brief Description of the Technology at Issue The 108 patent is directed generally to the field of audio recording devices using non-volatile memory, such as flash memory. (Ex at Abstract.) Claim 1 relates to a specific way for a file system to store data in non-volatile memory. (Ex ) Both the 108 patent and its parent, the 445 patent, contrast the claimed file system s memory management methods with those disclosed by Ban, which is prior art to the 108 and 445 patents and teaches creating a virtual memory map for converting virtual addresses to physical addresses. (Ex at 2:52-61.) According to the 108 and 445 patents, the use of this method of indirection in memory such as flash memory causes severe overhead burdens. (Id. at 2:50; Ex at 2:1-13.) To address this inefficiency, the 445 patent teaches a file system that logically links data segments by creating headers which contain pointers to absolute physical locations within flash memory. (Ex at 6:16-17.) In contrast to Ban, the alleged invention eliminates the use of memory maps and 21

25 instead uses logical links stored in the headers to provide a logical path to the data segments. (Id. at 6:18.) B. Description of the Alleged Invention of Claim 1 Claim 1 of the 108 patent is an independent method claim relating to the previously described memory management for a file system with three main steps. Claim 1 recites: 1. A method of memory management for a primary memory created from a non-volatile, long-term storage medium, said method enabling direct manipulation of contiguous and non-contiguous discrete data segments stored therein by a file system, and comprising the steps of: (a) creating the primary memory from a non-volatile, long-term storage medium, wherein the primary memory comprises a plurality of blocks in which the data segments are to be stored; (b) coupling a cache memory to the primary memory, said cache memory providing temporary and volatile storage for at least one of the data segments; (c) writing a new data segment from the cache memory to the primary memory by linking said new data segment to a sequentially previous logical data segment by the following steps: (1) receiving the new data segment in the cache memory; (2) moving the new data segment from the cache memory to a next available space within primary memory such that the new 22

26 data segment is stored in primary memory in non-used memory space; (3) identifying the previous logical data segment in primary memory; (4) creating a logical link between the previous logical data segment and the new data segment such that the logical link provides a path for sequentially accessing the data segments within the primary memory; (5) creating additional serial and logical links as subsequent new data segments are written to primary memory, said logical links providing the path for serially accessing the data segments regardless of contiguity of the data segments relative to each other within the primary memory; and (6) storing the data segments to primary memory in a manner consistent with an industry standard data storage format while retaining linking between data segments created in previous steps. Figure 3A of the 445 patent illustrates the relationship between the cache memory and the primary memory (e.g., the flash memory). 23

27 (Ex at Fig. 3A.) Data segments are received in cache memory and then moved to a next available space in primary memory. A link is then created in primary memory to link this new data segment to previous data segments. Figure 7A of the 445 patent, a diagram showing the data structure linkage of the alleged invention, further illustrates the claimed subject matter. The following excerpt of Figure 7A highlights the logical links created in the writing step that connect and provide an access path to the data segments. According to the patentees, these links are used to locate data in place of traditional tables or maps. (Ex at fig. 7A (annotated).) C. Prosecution History As discussed in Section III.C above, the 445 patent s prosecution history is highly relevant to Claim 1. During prosecution of the 445 patent, the PTO rejected claim 1 of that patent as obvious in view of U.S. Patent No. 5,586,291 and J. ESAKOV & T. WEISS, Data Structures An Advanced Approach Using C (1989). (Ex at 3-4.) The patentees traversed the rejection, arguing that the combination of cited references used a virtual memory map and thus taught away from the alleged invention. (Ex at 6.) The patentees explained that the 24

28 alleged invention obviated the need for a memory map and instead provided access to data through the use of a linked list file structure. In particular, [t]o increase efficiency, the only way [in the alleged invention] to determine the location of data is to traverse the linked list of data segments. (Id. at 5.) The patentees also distinguished the alleged invention from the cited prior art references and Ban because in the invention data can be manipulated directly in flash memory. (Id. at 8.) The patentees further distinguished the linked list of the alleged invention, which is a linked list for file structures, from prior art linked lists for data structures. (Id. ( Jeffrey teaches data structures. In contrast, the present invention teaches an operating system using linked lists for file structures. ) (original emphasis).) In other words, the patentees made clear their linked list is used in the specific context of a file system, and not for any data structure linkage. In light of these arguments, the claim was allowed. (See Ex ) D. Claim-By-Claim Explanation of Grounds for Unpatentability and Claim Charts Microsemi provides a detailed discussion of how each asserted prior art reference invalidates Claim 1. For each of the references, Microsemi underlines certain portions of the text and adds emphasis to figures presented in the following claim charts. Microsemi notes, however, that the surrounding text, though not underlined, is also relevant to Microsemi s challenge, as described herein. i. Claim 1 Is Obvious Over Yorimoto in View of Watanabe 25

29 Yorimoto teaches an integrated circuit (IC) card that contains electrically erasable programmable read-only memory (EEPROM), a type of non-volatile memory referred to by Yorimoto as data memory. (Ex at 1:5-13.) Yorimoto describes as objects of the invention providing an IC card in which, in the data memory, the new file can be easily prepared, and the existing file can be easily expanded and which provides an exact and quick access to the files in the data memory. (Ex at 1:60-66.) To accomplish this, the non-volatile EEPROM is segmented into several sectors, where each sector represents a plurality of bytes. (Id. at 1:57-66.) Figure 2 of Yorimoto illustrates the general structure of a data sector in the EEPROM memory: (Id. at fig. 2.) Each data sector includes a data field and pointers PS and SS, which store the numbers of the sectors preceding to and succeeding to that sector, i.e. the physical addresses in the EEPROM memory corresponding to the previous data sector (PS) and subsequent data sector (SS), respectively. (Id. at 3:45-48; see also id. at fig. 8, 4:65-5:6.) Claim 1, Preamble: Yorimoto discloses a method of memory management for a primary memory created from a non-volatile, long-term storage medium, said method enabling direct manipulation of contiguous and non- 26

30 contiguous discrete data segments stored therein by a file system. (See Ex ) Yorimoto teaches managing file data stored on non-volatile EEPROM memory. (Ex at 1:5-13; 5:24-29.) Data is managed and stored in both contiguous and noncontiguous data sectors on the EEPROM memory through the use of linked lists, thus allowing for direct manipulation of sectors. (Id. at fig. 8, 5:15-23.) Figures 7 and 8 of Yorimoto show how data sectors are stored: (Id. at figs. 7, 8 (annotated).) Figure 7 shows that file A (in red) consists of three data sectors with data fields a1, a2, and a3 (at sector numbers 3, 4, and 7, respectively). (Id. at 4:65-5:1.) Data sectors a1 and a2 are contiguous, while data sector a3 is not contiguous. The SS field (in yellow) of data sector a1 contains the physical address for data sector a2. Similarly, the SS field of data sector a2 contains the physical address for data sector a3. 27

31 Figure 7 also shows that file B (in blue) consists of one data sector at sector 5, with data field b1. (Id.) In figure 8, file B has been expanded by two data sectors (at sector numbers A and C) with data fields b2 and b3, with PS and SS fields to link together sectors b1, b2, and b3. (Id. at 5:7-12.) By using the PS and SS fields to link data sectors, Yorimoto s IC card allows a file that is made up of data sectors to be expanded or modified without modifying every data sector of the file, thus enabling direct manipulation without using a file allocation table. Step (a): Yorimoto discloses creating the primary memory from a nonvolatile, long-term storage medium, wherein the primary memory comprises a plurality of blocks in which the data segments are to be stored. (See Ex , 104.) Yorimoto discloses a non-volatile EEPROM memory (Ex at 1:5-13), which is segmented into 16 sectors. (Id. at 3:39-40, figs. 7, 8.) Step (b): Yorimoto in combination with Watanabe discloses coupling a cache memory to the primary memory, said cache memory providing temporary and volatile storage for at least one of the data segments. (See Ex , ) Like Yorimoto, Watanabe teaches an IC EEPROM memory card. (Ex at Abstract, 1:14-25.) Watanabe discloses that data is temporarily stored in [a] buffer before being written into... EEPROM. (Id. at 1:57-64.) Yorimoto discloses that its IC card contains a RAM memory for providing a working area when CPU 11 executes a program, but does not explicitly disclose that the RAM 28

32 provides temporary storage of data. (Ex at 3:8-10.) The 445 patent makes clear that the cache can be RAM: The present invention also provides a small cache, typically comprised of RAM. (Ex at 8:61-64) One of ordinary skill in the art would have been motivated to use the RAM memory disclosed in Yorimoto as a buffer to temporarily store data in the manner of Watanabe, thereby invalidating Claim 1. First, both Yorimoto and Watanabe relate to the same field of technology. Specifically, both disclose IC memory cards with non-volatile EEPROM memory, and relate to file systems for non-volatile memory. (Ex ; see, e.g., In re Hyon, 679 F.3d 1363, 1366 (Fed. Cir. 2012) (finding motivation to combine where the prior art references were directed to the same class of products ).) Moreover, Yorimoto can be improved by combining it with Watanabe. The time required to write data to the actual EEPROM is long, as disclosed in Watanabe. (Ex ) In particular, Watanabe notes that the buffer is needed because the IC memory card using the... EEPROM needs a complicated control for data writing... Hence, time required for data recording will become long. (Ex at 1:53-57.) Watanabe thus teaches a way to improve the speed of the overall system by using a buffer. (Ex ) One of ordinary skill would have appreciated that Yorimoto could be improved by using the RAM memory of the IC card for temporary storage of data in order to increase the speed of the system. (Ex ; see, e.g., 29

33 Sundance, Inc. v. DeMonte Fabricating Ltd., 550 F.3d 1356, 1367 (Fed. Cir. 2008) (finding a patent invalid as obvious where a combination of two prior art references would have resulted in a design having the same benefit and improvement over the first prior art reference as those disclosed by the second prior art reference); see ABS Global, Inc. v. XY, LLC, IPR , Paper 8 (Institution Decision) at (April 15, 2015) (finding motivation to combine references where teachings of first reference would be improved by teachings of second reference).) In short, Watanabe specifically teaches using a buffer in systems like Yorimoto and the advantages for doing so. Step (c): Yorimoto in combination with Watanabe discloses writing a new data segment from the cache memory to the primary memory by linking said new data segment to a sequentially previous logical data segment. (See Ex ) As explained in Step (b), Watanabe discloses writing data from a buffer to the primary EEPROM memory. Yorimoto discloses linking a new data sector to a sequentially previous logical sector: each data sector of the EEPROM memory contains a data field that contains a file segment, as well as PS and SS fields that store the address of the sectors for the previous and next file segments, respectively. (Ex at 3:45-48, 4:65-5:6.) The PS and SS fields are pointers to locations in memory of the previous and next file segments. (Ex ) 30

34 Step (c)(1): Yorimoto in combination with Watanabe discloses receiving the new data segment in the cache memory. (See Ex ) As described above in Step (b), Watanabe discloses a buffer to temporarily store data before it is written to the EEPROM memory. (Ex at 1:57-64.) Step (c)(2): Yorimoto in combination with Watanabe discloses moving the new data segment from the cache memory to a next available space within primary memory such that the new data segment is stored in primary memory in non-used memory space. (See Ex ) Watanabe discloses moving data from the buffer (i.e., cache memory ) to the EEPROM memory. (Ex at 1:57-64.) Yorimoto discloses that the file segment is stored in non-used memory space in the EEPROM memory: the system determine[s] whether or not [a] free sector remains, and the free sector is reserved as a new file area. (Ex at 6:58-64, 7:4-6; see also id. at figs. 11A, 11B, 13A, 13B, 8:6-12.) Step (c)(3): Yorimoto discloses identifying the previous logical data segment in primary memory. (See Ex ) Each data sector of the EEPROM memory contains a data field, as well as PS and SS fields that are pointers to locations in memory of the previous and next data sectors, respectively. (Ex at 3:45-48, 4:65-5:6.) For example, annotated figure 8 shows that file A is made up of three sectors linked together at sectors 3, 4, and 7: 31

35 (Id. at fig. 8 (Annotated to show data fields a1, a2, and a3 in green. Each data field has a corresponding SS field in orange, which points to the address of the next data sector e.g., data sector a1 has an SS field pointing to sector number 4, which contains data sector a2.).) File segments of a file are coupled together through the PS and SS fields. (Id. at 4:65-5:18.) Thus, when a new data sector (e.g., a3) is written to the EEPROM memory, the previous file segment (e.g., a2) must be identified. (Ex ) In another example, annotated figure 8 shows that file B is expanded with 9b and 9c (data fields of b2 and b3). (Ex at 5:9-10) When new data segment b2 is added in sector OA, the previous logical data segment (b1 in sector 05) is identified as shown in b2 s PS field identifying the previous data segment b1 in sector

36 Step (c)(4): Yorimoto discloses creating a logical link between the previous logical data segment and the new data segment such that the logical link provides a path for sequentially accessing the data segments within the primary memory. (See Ex , 115.) As described above for Step (c)(3), Yorimoto discloses creating a logical link between the new data sector and the previous data sector. The SS field of the previous sector contains the address of the new sector, thus linking the previous sector and the new sector. (Ex at fig. 8, 7:29-42.) The PS field of the new sector also contains the address of the previous file segment. (Id. at fig. 8, 4:65-5:18.) Step (c)(5): Yorimoto discloses creating additional serial and logical links as subsequent new data segments are written to primary memory, said logical links providing the path for serially accessing the data segments regardless of contiguity of the data segments relative to each other within the primary memory. (See Ex ) As discussed for Steps (c)(3) and (c)(4), Yorimoto discloses providing a path for serially accessing data sectors. As shown in figure 8, in Step(c)(3), Yorimoto discloses coupling additional data sectors together, such as chaining data sectors a1, a2, and a3. Figure 8 also shows chaining data sectors b1, b2, and b3 for file B. (Ex at 5:7-12.) The data sectors for a file do not have to be stored contiguously: for example, in figure 8, data sectors a1 and a2 are contiguous, while data sector a3 is not contiguous. (Id. at fig. 8, 5:15-23.) 33

37 Step (c)(6): Yorimoto in combination with Watanabe discloses storing the data segments to primary memory in a manner consistent with an industry standard data storage format while retaining linking between data segments created in previous steps. (See Ex , ) Like Yorimoto, Watanabe teaches an IC memory card that stores data in EEPROM memory. (Ex at Abstract, 1:14-25.) This IC memory card stores image or picture data from a camera. (Id. at 1:44-51.) In particular, Watanabe discloses that the EEPROM memory on the IC memory card stores data that represent[s] a frame of image, for example, by a standard format of picture signals. (Id. at 17:59-64.) Thus, Watanabe discloses storing image data in a standard format. (Ex ) The alleged invention of Claim 1 would have been obvious to one having ordinary skill in the art in view of the combined teachings of Yorimoto and Watanabe. (Ex ) While Yorimoto does not explicitly disclose what data storage formats can be stored in its flash memory device, Watanabe teaches storing data, e.g., an image, in a standard format. (Ex at 17:59-64.) Moreover, one of ordinary skill in the art would have been motivated to combine these references to arrive at the claimed invention. First, both Yorimoto and Watanabe disclose IC 34

38 cards that store data in EEPROM memory. 9 Second, the combination would have improved Yorimoto. Specifically, Yorimoto discloses a versatile IC card that is used for multi-purposes and thus stores a plurality of files. (Ex at 1:27-31.) Although Yorimoto does not disclose what types of files are stored on the IC card, Watanabe discloses storing image data in a standard format. (Ex at 17:59-64.) One of ordinary skill would have appreciated that the IC card disclosed in Yorimoto could store files similar to those stored in the IC card disclosed in Watanabe. 10 (Ex ) This adds to the versatility of Yorimoto s invention, 9 See, e.g., In re Hyon, 679 F.3d at 1366 (finding motivation to combine where the prior art references were directed to the same class of products ). Here, similar to the facts in In re Hyon, both Yorimoto and Watanabe are directed to the same class of products i.e. EEPROM memory for data storage. Thus, one of ordinary skill in the art would have found motivation to use the memory of Yorimoto to store standard format image data as disclosed in Watanabe. 10 See, e.g., Sundance, 550 F.3d at 1367 (finding the addition of a design of a second reference to a first prior art reference would give the resulting design exactly the same benefit as [taught by the second reference] and thus the patent in question represents the mere application of a known technique to a piece of prior art ready for the improvement. ) (citations omitted) (emphasis in original). Here, 35

39 which is supposed to have multiple purposes. 11 (Id.) The claim chart below demonstrates in detail how Claim 1 is obvious over Yorimoto in view of Watanabe. 108 Patent Claim 1 Yorimoto in view of Watanabe [1] A method of memory management for a primary memory created from a nonvolatile, long-term storage medium, said method enabling direct manipulation of contiguous and non- contiguous discrete data This invention relates to an IC (integrated circuit) card, and more particularly to an IC card which contains a rewritable semiconductor memory. An IC card with data processing function has recently been put into practical use. This IC card contains a central processing unit (CPU) and a rewritable data memory, such as an electrically erasable programmable read only memory (EEPROM), or a random access memory (RAM) which is backed up by the battery. (Ex at 1:5-13.) FIG. 7 is the memory map of the data memory when file applying the teachings of Watanabe to Yorimoto would similarly give the resulting combination the same benefit taught in Watanabe i.e. the storage of image data in a standard format in EEPROM memory. Thus, the 108 patent is nothing more than a mere application of the known technique of Watanabe to prior art (Yorimoto) ready for the improvement. 11 The 108 and 445 patents and prosecution history do not identify any secondary considerations of non-obviousness. Should e.digital put forth any allegations of secondary considerations of non-obviousness, Microsemi asks for an opportunity to respond. 36

40 108 Patent Claim 1 Yorimoto in view of Watanabe segments stored therein by a file system, and comprising the steps of: A consisting of three data sectors 8a, 8b and 8c (data fields of a1, a2,a3) and file B consisting of one data sector 9a (data field of b1) are formed anew in the IC card. In FIG. 7, the data is registered in directory sector 7a, which was a dummy in FIG. 6. In accordance with the generation of files, FTS, FLS and NFS in MCA are renewed. Further, data sectors in file A are coupled together, and the chain of the normal sectors are partially corrected. In the memory map illustrated in FIG. 8, file C is formed anew, which consists of a data sector 10a (data field of c1), and file B is expanded with 9b and 9c (data fields of b2 and b3). (Id. at 4:65-5:10.) FIG. 9 is a flowchart illustrating the accessing (read/write) operation to data memory 12. In step S10, the address included in the processing instruction which is supplied to third port 17 in IC card 10 via I/O line 21 from the external processing unit 20, is written into RAM 14. (Id. at 5:24-29.) [1a] (a) creating the primary memory from a non-volatile, long- term storage medium, wherein the primary memory comprises a plurality of blocks in which the data segments are to be stored; [1b] (b) coupling a cache memory to the primary memory, said cache memory See id. at figs. 7, 8. Data memory 12 is a rewritable memory such as an EEPROM or an RAM which is backed up by a battery. Its memory capacity is 192 bytes and the memory area is segmented into 16 sectors each of 12 bytes. (Ex at 2:67-3:3.) In each sector, first to eighth bytes are data fields. Ninth and tenth bytes are PS and SS fields which store the numbers of the sectors preceding to and succeeding to that sector. (Id. at 3:45-48.) Watanabe discloses coupling a cache memory (e.g., a buffer) to the primary memory (e.g., EEPROM), where the cache memory provides temporary and volatile storage for at least one of the data segments. 37

41 108 Patent Claim 1 Yorimoto in view of Watanabe providing temporary and volatile storage for at least one of the data segments; Further, the IC memory card using the above-mentioned EEPROM needs a complicated control for data writing, different from the IC memory card using the SRAM. Hence, time required for data recording will become long. In view of these matters, the IC memory card using the EEPROM is provided with a predetermined storage capacity of a buffer, and is so arranged that data, which are transferred from the IC memory card control device and temporarily stored in the buffer, are read out therefrom under the control of the controller provided on the IC memory card and then written into a flushing type of EEPROM. (Ex at 1:53-64.) [1c] (c) writing a new data segment from the cache memory to the primary memory by linking said new data segment to a sequentially previous logical data segment by the following steps: Data bus 18 and address bus 19 are also connected to program memory 13, RAM 14 and third port 17. Program memory 13 is a read only memory. RAM 14 is a memory for providing a working area when CPU 11 executes the program stored in program memory 13. (Ex at 3:6-10.) Further, the IC memory card using the above-mentioned EEPROM needs a complicated control for data writing, different from the IC memory card using the SRAM. Hence, time required for data recording will become long. In view of these matters, the IC memory card using the EEPROM is provided with a predetermined storage capacity of a buffer, and is so arranged that data, which are transferred from the IC memory card control device and temporarily stored in the buffer, are read out therefrom under the control of the controller provided on the IC memory card and then written into a flushing type of EEPROM. (Ex at 1:53-64.) In the data file and the directory file, each sector has a PS and an SS for sector chaining. Therefore, even if the chain between sectors has been disconnected for some reason, if the disconnection is only one, it is possible to find and 38

42 108 Patent Claim 1 Yorimoto in view of Watanabe repair the disconnection by tracing the sector chain, starting from TS and LS, while referring to SS and PS. (Ex at 4:25-31.) FIG. 7 is the memory map of the data memory when file A consisting of three data sectors 8a, 8b and 8c (data fields of a1, a2,a3) and file B consisting of one data sector 9a (data field of b1) are formed anew in the IC card. In FIG. 7, the data is registered in directory sector 7a, which was a dummy in FIG. 6. In accordance with the generation of files, FTS, FLS and NFS in MCA are renewed. Further, data sectors in file A are coupled together, and the chain of the normal sectors are partially corrected. In the memory map illustrated in FIG. 8, file C is formed anew, which consists of a data sector 10a (data field of c1), and file B is expanded with 9b and 9c (data fields of b2 and b3). Since file C is registered anew, the directory file, which consisted of one sector has now expanded to have two sectors 7a and 7b. The expanded directory file 7b is coupled directly with the existing directory file 7a. The data sectors included in file B are coupled with one another. With this coupling, the directory file of file B is also updated. (Id. at 4:65-5:18.) [1c1] (1) receiving the new data segment in the cache memory; [1c2] (2) moving the new data segment from the cache See Ex at figs. 2, 7, 8. [T]he IC memory card using the EEPROM is provided with a predetermined storage capacity of a buffer, and is so arranged that data, which are transferred from the IC memory card control device and temporarily stored in the buffer, are read out therefrom under the control of the controller provided on the IC memory card and then written into a flushing type of EEPROM. (Ex at 1:57-64.) [T]he IC memory card using the EEPROM is provided with a predetermined storage capacity of a buffer, and is memory space so arranged that data, which are transferred 39

43 108 Patent Claim 1 Yorimoto in view of Watanabe memory to a next available space within primary memory such that the new data segment is stored in primary memory in non-used memory space; from the IC memory card control device and temporarily stored in the buffer, are read out therefrom under the control of the controller provided on the IC memory card and then written into a flushing type of EEPROM. (Ex at 1:57-64.) FIGS. 11A and 11B cooperatively show a flowchart of a new file registration subroutine (step S160) in FIG. 10. In step S210, the NFS of MCA is read. In step S220, it is determined whether or not free sector remains. If it is determined that there is no free sector, the abnormal end flag is set in step S400, and control is returned to the main routine. If it is determined that a free sector is present, the top address of the free sector (FTS of MCA) is read in step S230. (Ex at 6:55-64.) [1c3] (3) identifying the previous logical data segment in primary memory; If the write error does not occur, FF is set in the SS of the free sector as obtained in step S230 in step S260, and this free file is reserved as a new file area. (Id. at 7:4-6.) (Ex at fig. 2.) In each sector, first to eighth bytes are data fields. Ninth and tenth bytes are PS and SS fields which store the numbers of the sectors preceding to and succeeding to that sector. (Id. at 3:45-48.) [T]he data as shown below, is written into the area as reserved as the directory preparation area, to register the directory file in step S350. File name: File name as designated by terminal device 20. TS: Sector number as reserved in step S260. LS: TS US: 1 40

44 108 Patent Claim 1 Yorimoto in view of Watanabe [1c4] (4) creating a logical link between the previous logical data segment and the new data segment such that the logical link provides a path for sequentially accessing the data segments within the primary memory; PS: Sector number of the sector preceding to and coupled with the sector. SS: FF (Id. at 7:31-42.) In each sector, first to eighth bytes are data fields. Ninth and tenth bytes are PS and SS fields which store the numbers of the sectors preceding to and succeeding to that sector. (Ex at 3:45-48.) FIG. 2 shows a layout of the data sector. Data field 30 is the field freely used by the user and the system. The application file is constructed by chaining a plurality of data sectors, if necessary. (Id. at 3:54-57.) In the data file and the directory file, each sector has a PS and an SS for sector chaining. Therefore, even if the chain between sectors has been disconnected for some reason, if the disconnection is only one, it is possible to find and repair the disconnection by tracing the sector chain, starting from TS and LS, while referring to SS and PS. (Id. at 4:25-31.) FIG. 7 is the memory map of the data memory when file A consisting of three data sectors 8a, 8b and 8c (data fields of a1, a2,a3) and file B consisting of one data sector 9a (data field of b1) are formed anew in the IC card. In FIG. 7, the data is registered in directory sector 7a, which was a dummy in FIG. 6. In accordance with the generation of files, FTS, FLS and NFS in MCA are renewed. Further, data sectors in file A are coupled together, and the chain of the normal sectors are partially corrected. In the memory map illustrated in FIG. 8, file C is formed anew, which consists of a data sector 10a (data field of c1), and file B is expanded with 9b and 9c (data fields of b2 and b3). Since file C is registered anew, the directory file, which consisted of one sector has now expanded to have two sectors 7a and 7b. The expanded directory file 7b is 41

45 108 Patent Claim 1 Yorimoto in view of Watanabe coupled directly with the existing directory file 7a. The data sectors included in file B are coupled with one another. With this coupling, the directory file of file B is also updated. (Id. at 4:65-5:18.) [1c5] (5) creating additional serial and logical links as subsequent new data segments are written to primary memory, said logical links providing the path for serially accessing the data segments regardless of contiguity of the data segments relative to each other within the primary memory; and [1c6] (6) storing the data segments to primary memory in a manner consistent with an industry standard data storage format while retaining linking between data segments created in previous steps. See also id. at figs. 2, 7, 8. The data sectors included in file B are coupled with one another. With this coupling, the directory file of file B is also updated. The coupling of the unused normal sectors is also partially corrected. Sector B has a write error when data b3 was expanded. Therefore, it is omitted from the sector chain, as a defective sector. The data is fed back to MCA of sector 0, and then FTS and NFS are updated. (Ex at 5:15-23.) See also id. at figs. 7, 8. An IC memory card control device, which controls recording and/or reading out various sorts of data in and/or from the above-mentioned IC memory card, is loaded into an electronic still camera, for example, so that information such as image or picture data obtained by means of photographing by this camera is recorded on the IC memory card which is detachably coupled with the memory card control apparatus. (Ex at 1:44-51.) In the second EEPROM cell 840 to which a data area 400 is assigned, there are formed the clusters #2-#2047. (Id. at 17:52-54.) In the clusters #2-#2047 of the data area 400, there are 42

46 108 Patent Claim 1 Yorimoto in view of Watanabe stored data which represent a frame of image, for example, by a standard format of picture signals, or picture data extended over and distributed in an appropriate plurality of clusters in a so-called packet format. (Id. at 17:59-64.) Recently, the IC card used for multi-purposes, called a multi-use type IC card has been proposed. In the multi- use type IC, a plurality of files are stored in the data memory, and the file access and file control must be controlled effectively. (Ex at 1:27-31.) ii. Claim 1 Is Obvious Over Katayama Katayama teaches a semiconductor file memory device that uses flash memory in place of traditional magnetic disk memory in conjunction with information processing systems. (Ex at 3:8-14.) The information processing systems that can be used with the flash memory storage medium can be personal computers, including portable devices such as PDAs and notebook computers. (Id. at 1:16-35.) The memory device in Katayama allows for writing concurrently to four memory groups comprising flash memory chips. (Id. at 4:53-55.) Figure 5B of Katayama, below, shows an example of the memory contents of the memory device. (Id. at 10:43-46.) 43

47 (Id. at fig. 5B.) In figure 5B, the symbol m-n indicates a file number m and a sector number n of the file; for example, data 4-7 in memory group 1 is sector number 7 of file number 4. (Ex at 10:46-48.) Data is chained, or logically-linked, together, as shown in figure 6: (Id. at fig. 6 (annotated).) Data 4-5 (representing sector 5 for file 4) has a corresponding chaining information that points to the physical address of the next sector of data, 4-6. (Id. at 14:53-57, 14:67-15:9.) Claim 1, Preamble: Katayama discloses a method of memory management for a primary memory created from a non-volatile, long-term storage medium, said method enabling direct manipulation of contiguous and noncontiguous discrete data segments stored therein by a file system. (See Ex ) Katayama teaches a semiconductor file memory device that uses flash memory. (Ex at Abstract.) Files are managed and stored in flash memory as 44

48 sets of file sectors that are chained together. (Id. at fig. 5B, fig. 6, 14:53-57, 14:67-15:9.) For example, figures 5A and 5B show how data is stored: (Id. at figs. 5A, 5B (annotated).) Figure 5A shows that file 4 is made up of five sectors, 4-1 through 4-5 (in red). File sectors such as 4-3, 4-4, and 4-5 are stored contiguously. (Id. at 13:17-24.) Figure 5B shows that file 4 has been expanded to add sectors 4-6 and 4-7. (Id. at 14:32-37.) File sector 4-7 is stored noncontiguously. (Id. at 15:14-16.) The file sectors are chained together using the chaining information, which points to the physical address of the next sector of the data file. (Id. at fig. 6, 14:53-57, 14:67-15:9.) Thus, the semiconductor file memory device of Katayama allows for continuous access to a file even if it is not stored in continuous locations. (Id. at 15:14-16.) By using the chaining information to link data sectors, Katayama s semiconductor memory device allows a file that is made up of data sectors to be expanded or modified without modifying every data sector of the file, thus enabling direct manipulation. 45

49 Step (a): Katayama discloses creating the primary memory from a nonvolatile, long-term storage medium, wherein the primary memory comprises a plurality of blocks in which the data segments are to be stored. (See Ex ) Katayama discloses a non-volatile flash memory (Ex at Abstract), which stores data in file sectors in the flash memory, as shown in figures 5A and 5B, above for the preamble. (Id. at figs. 5A, 5B; 13:17-19.) Step (b): Katayama discloses coupling a cache memory to the primary memory, said cache memory providing temporary and volatile storage for at least one of the data segments. (See Ex , ) Katayama discloses a write buffer that temporarily stores data before it is written to the flash memory. (Ex at fig. 4, 12:55-13:4.) As shown in figure 4 below, the memory device in Katayama includes a write buffer that is for holding write data temporarily so that write data from the system is held in the write buffer 72, and thereafter... written to the flash memory arrays 5. (Id. at 12:63-65, 13:1-4.) (Id. at fig. 4 (annotated to show the write buffer in red).) 46

50 Step (c): Katayama discloses writing a new data segment from the cache memory to the primary memory by linking said new data segment to a sequentially previous logical data segment. (See Ex , 143.) As explained above for step (b), Katayama discloses writing data from the write buffer to the flash memory. As explained further in Steps (c)(3) and (c)(4) below, Katayama also discloses linking a new file sector to a sequentially previous logical file sector, using chaining information. (Ex at fig. 6, 14:53-57, 14:67-15:9.) Step (c)(1): Katayama discloses receiving the new data segment in the cache memory. (See Ex ) As described in Step (b), Katayama discloses a write buffer that is for holding write data temporarily so that write data from the system is held in the write buffer 72, and thereafter... written to the flash memory arrays 5. (Ex at 12:63-65, 13:1-4.) Step (c)(2): Katayama discloses moving the new data segment from the cache memory to a next available space within primary memory such that the new data segment is stored in primary memory in non-used memory space. (See Ex ) Katayama discloses moving the new file sector from the write buffer to the flash memory. (Ex at 13:1-4.) The new file sector is written to a vacant sector. (Id. at 14:25-41; see also id. at figs. 5A, 5B (showing that new sectors 6-2, 4-6, 4-7, and 2-5 are written to vacant sectors).) 47

51 Step (c)(3): Katayama discloses identifying the previous logical data segment in primary memory. (See Ex , 148.) The flash memory stores files as a chain of file sectors. (Ex at fig. 6, 14:53-15:9.) Figure 6 below shows that the sectors of a file are chained together. Data 4-5 has corresponding chaining information that points to the physical address of the next sector of the data file, 4-6. (Id. at 14:53-57, 14:67-15:9.) (Id. at fig. 6 (annotated to show that data 4-5 is chained to data 4-6, which is chained to data 4-7, through the chaining information).) Thus, when a new file sector (e.g., data 4-7) is written to the flash memory, the previous file sector (e.g., data 4-6) must be identified. (Ex ) Step (c)(4): Katayama discloses creating a logical link between the previous logical data segment and the new data segment such that the logical link provides a path for sequentially accessing the data segments within the primary memory. (See Ex , 149.) As shown above in Step (c)(3), figure 6 shows that the sectors of a file are chained together. Data 4-5 includes chaining information that points [to] the physical address of the next sector of the file data. (Ex at 14:67-15:5.) The chaining information for data 4-5 is physical address 48

52 4 7. Figure 6 shows that data 4-6 is stored at that physical address. Thus, Katayama discloses creating a logical link between the new and previous file sectors. Step (c)(5): Katayama discloses creating additional serial and logical links as subsequent new data segments are written to primary memory, said logical links providing the path for serially accessing the data segments regardless of contiguity of the data segments relative to each other within the primary memory. (See Ex , ) As shown above in Step(c)(3), figure 6 discloses coupling additional file sectors together, such as chaining sectors 4-5, 4-6, and 4-7. (Ex at 14:53-57, 14:63-15:7.) Figure 5B shows that the file sectors can be stored non-contiguously: (Id. at fig. 5B (annotated); see also id. at 15:14-16.) For example, file sector 4-6 is stored non-contiguously to sector 4-5. Figure 6, above in Step (c)(3), shows that sectors 4-5 and 4-6 are nevertheless linked together using the chaining information. Thus, it becomes possible to make a continuous access to a file even if it is not stored in continuous locations. (Id. at 15:14-16.) Step (c)(6): Katayama renders obvious the limitation storing the data segments to primary memory in a manner consistent with an industry standard data 49