Ch 5: Designing a Single Cycle Datapath

Size: px
Start display at page:

Download "Ch 5: Designing a Single Cycle Datapath"

Transcription

1 Ch 5: esigning a Single Cycle path Computer Systems Architecture CS 365 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory path Input Output Today s Topic: esign a Single Cycle Processor machine design Arithmetic (Ch 3) inst set design (Ch 2) technology

2 The Big Picture: The Performance Perspective CPI Performance of a machine is determined by: count Clock cycle time Inst Count Cycle Time Clock cycles per instruction Processor design (path and control) will determine: Clock cycle time Clock cycles per instruction Today: Single cycle processor: Advantage: One clock cycle per instruction isadvantage: long cycle time How to esign a Processor: step-by-step Analyze instruction set => path requirements the meaning of each instruction is given by the register transfers path must include storage element for ISA registers possibly more path must support each register transfer 2 Select set of path components and establish clocking methodology 3 Assemble path meeting the requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic 2

3 The MIPS Formats All MIPS instructions are bits long The three instruction formats: R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I-type op rs rt immediate 6 bits 5 bits 5 bits 6 bits J-type 3 26 op target address 6 bits 26 bits The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction Step a: The MIPS-lite Subset 3 A, SUB, AN, OR add rd, rs, rt sub rd, rs, rt and rd, rs,rt or rd,rs,rt 3 LOA and STORE Word lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: 3 beq rs, rt, imm op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 3

4 Logical Register Transfers RTL gives the meaning of the instructions First step is to fetch the instruction from op rs rt rd shamt funct = MEM[ PC ] op rs rt Imm6 = MEM[ PC ] inst Register Transfers A R[rd] < R[rs] + R[rt]; PC < PC + 4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 OR R[rt] < R[rs] R[rt]; PC < PC + 4 LOA R[rt] < MEM[ R[rs] + sign_ext(imm6)]; PC < PC + 4 STORE MEM[ R[rs] + sign_ext(imm6) ] < R[rt]; PC < PC + 4 BEQ if ( R[rs] == R[rt] ) then PC < PC + sign_ext(imm6)] else PC < PC + 4 Step : Requirements of the Set Memory instruction & ( x ) read RS read RT RT or R PC Extender and Sub register or extended immediate 4 or extended immediate to PC 4

5 Step 2: Components of the path Combinational Elements Storage Elements Clocking methodology Abstract/Simplified View of path Register # PC ress Register # Register # ress Two types of functional units: elements that operate on values (combinational) elements that contain state (sequential) 5

6 Combinational Logic Elements (Basic Building Blocks) A er B er CarryIn Sum Carry MUX Selec t A Y B MUX A B O P Result State Elements: Review Unclocked vs Clocked Clocks used in synchronous logic when should an element that contains state be updated? falling edge cycle time rising edge 6

7 An unclocked state element The set-reset latch output depends on present inputs and also on past inputs R Q S _ Q Latches and Flip-flops Output is equal to the stored value inside the element (don't need to ask for permission to look at the value) Change of state (value) is based on the clock Latches: whenever the inputs change, and the clock is asserted Flip-flop: state changes only on a clock edge (edge-triggered methodology) "logically true", could mean electrically low A clocking methodology defines when signals can be read and written wouldn't want to read a signal at the same time it was being written 7

8 -latch Two inputs: the value to be stored () the clock signal (C) indicating when to read & store Two outputs: the value of the internal state (Q) and its complement C Q _ Q C Q flip-flop Output changes only on the clock edge Q latch C Q latch _ C Q Q _ Q C C Q 8

9 Our Implementation An edge triggered methodology Typical execution: read contents of some state elements, send values through some combinational logic write s to one or more state elements State element Combinational logic State element 2 Clock cycle State element Combinational logic Storage Element: Register (Basic Building Block) Register Enable Similar to the Flip Flop except In Out N-bit input and output N N Enable input Enable: Clk negated (): Out will not change asserted (): Out will become In 9

10 Register File Built using flip-flops register number register number 2 Register Register Register n Register n M u x register number register number 2 Register file register 2 M u x 2 Register File Note: we still use the clock to determine when to write Register number n-to- decoder n n C Register C Register Register C Register n C Register n

11 Storage Element: Register File Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: Enable busw Clk RWRARB bit RA (number) selects the register to put on busa () RB (number) selects the register to put on busb () RW (number) selects the register to be written via busw () when Enable is Clock input (CLK) The CLK input is a factor ONLY during write operation uring read operation, behaves as a combinational logic block: RA or RB valid => busa or busb valid after access time busa busb Storage Element: Idealized Memory Enable ress Memory (idealized) One input bus: In In Out One output bus: Out Memory word is selected by: Clk ress selects the word to put on Out Enable = : address selects the word to be written via the In bus Clock input (CLK) The CLK input is a factor ONLY during write operation uring read operation, behaves as a combinational logic block: ress valid => Out valid after access time

12 Clocking Methodology Clk Setup Hold on t Care Setup Hold All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest elay Path + Setup + Clock Skew Step 3 Register Transfer Requirements > path Assembly Fetch Operands and Execute Operation 2

13 3a: Overview of the Fetch Unit The common RTL operations Fetch the : mem[pc] Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- something else We don t know if instruction is a Branch/Jump or one of the other instructions until we have fetched and interpreted the instruction from So all instructions initially increment the PC address PC Sum a b Program counter c er 3

14 path for Fetch 4 PC address 3b: R-format instructions: add, sub, and, or, slt R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt register, register 2, and register come from instruction s rs, rt, and rd fields control and Reg: control logic after decoding the instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Register numbers control 5 3 register 5 register 2 Zero 5 register 2 Reg a b 4

15 path for R-format instructions register register 2 register 2 Reg 3 operation Zero Clk PC Rs, Rt, Rd, Op, Func ctr Register-Register Timing Old Value Clk-to-Q New Value Old Value Old Value Memory Access Time New Value elay through Control Logic New Value RegWr Old Value New Value Register File Access Time busa, B Old Value New Value elay busw Old Value New Value RegWr busw Clk Rd Rs Rt Rw Ra Rb -bit busa busb ctr Result Register Occurs Here 5

16 3d: Load & Store Operations R[rt] <- Mem[R[rs] + SignExt[imm6]] Example: lw rt, rs, imm6 Mem[ R[rs] + SignExt[imm6] <- R[rt] ] Example: sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits Mem ress 6 Sign extend Mem a unit b Sign-extension unit path for lw & sw register register 2 register Reg 2 3 operation Zero ress Mem 6 Sign extend Mem 6

17 3f: The Branch op rs rt immediate 6 bits 5 bits 5 bits 6 bits beq rs, rt, imm6 mem[pc] Fetch the instruction from Equal <- R[rs] == R[rt] Calculate the branch condition if (CON eq ) Calculate the next instruction s address PC <- PC ( SignExt(imm6) x 4 ) else PC <- PC + 4 path for branch instruction PC + 4 from instruction path Sum Branch target Shift left 2 register register 2 register Reg 2 6 Sign extend 3 operation Zero To branch control logic 7

18 Using multiplexors to stitch together the path for access and R-format instructions 4 PC address register register 2 register Reg 2 Src M ux 3 operation Zero ress Mem MemtoReg M ux 6 Sign extend Mem Putting it all together PCSrc PC 4 address register register 2 register 2 Reg 6 Sign extend Shift left 2 Src 3 operation Zero ress Mem Mem MemtoReg 8

19 Putting it all together cont d PCSrc 4 Reg Shift left 2 PC address [3 ] [25 2] [2 6] [5 ] Regst [5 ] register register 2 register 2 6 Sign extend Src control Zero Mem ress Mem MemtoReg [5 ] Op ing the control unit M ux 4 [3 26] Control Regst Branch Mem MemtoReg Op Mem Src Reg Shift left 2 PCSrc PC address [3 ] [25 2] [2 6] [5 ] [5 ] M ux register register 2 2 register 6 Sign extend M ux control Zero ress M ux [5 ] 9

20 An Abstract View of the Critical Path Register file and ideal : The CLK input is a factor ONLY during write operation uring read operation, behave as combinational logic: ress valid => Output valid after access time Next ress Ideal Memory ress Clk PC Rd 5 Clk Rs 5 Rt 5 Rw Ra Rb -bit Imm 6 A B Critical Path (Load Operation) = PC s Clk-to-Q + Memory s Access Time + Register File s Access Time + to Perform a -bit + Memory Access Time + Setup Time for Register File + Clock Skew ress In Clk Ideal Memory Single Cycle Implementation Calculate cycle time assuming negligible delays except: (2ns), and adders (2ns), register file access (ns) PCSrc 4 Reg Shift left 2 PC address [3 ] [25 2] [2 6] [5 ] Regst [5 ] register register 2 register 2 6 Sign extend Src control Zero Mem ress Mem MemtoReg [5 ] Op 2

361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath

361 datapath.1. Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath 361 datapath.1 Computer Architecture EECS 361 Lecture 8: Designing a Single Cycle Datapath Outline of Today s Lecture Introduction Where are we with respect to the BIG picture? Questions and Administrative

More information

ECE468 Computer Organization and Architecture. Designing a Single Cycle Datapath

ECE468 Computer Organization and Architecture. Designing a Single Cycle Datapath ECE468 Computer Organization and Architecture Designing a Single Cycle Datapath ECE468 datapath1 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Input Datapath

More information

The Big Picture: Where are We Now? EEM 486: Computer Architecture. Lecture 3. Designing a Single Cycle Datapath

The Big Picture: Where are We Now? EEM 486: Computer Architecture. Lecture 3. Designing a Single Cycle Datapath The Big Picture: Where are We Now? EEM 486: Computer Architecture Lecture 3 The Five Classic Components of a Computer Processor Input Control Memory Designing a Single Cycle path path Output Today s Topic:

More information

Outline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath

Outline. EEL-4713 Computer Architecture Designing a Single Cycle Datapath Outline EEL-473 Computer Architecture Designing a Single Cycle path Introduction The steps of designing a processor path and timing for register-register operations path for logical operations with immediates

More information

COMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath

COMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output The Big Picture: The

More information

CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath

CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath CPE 442 single-cycle datapath.1 Outline of Today s Lecture Recap and Introduction Where are we with respect to the BIG picture?

More information

UC Berkeley CS61C : Machine Structures

UC Berkeley CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 25 CPU Design: Designing a Single-cycle CPU Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia T-Mobile s Wi-Fi / Cell phone

More information

CS 61C: Great Ideas in Computer Architecture Datapath. Instructors: John Wawrzynek & Vladimir Stojanovic

CS 61C: Great Ideas in Computer Architecture Datapath. Instructors: John Wawrzynek & Vladimir Stojanovic CS 61C: Great Ideas in Computer Architecture Datapath Instructors: John Wawrzynek & Vladimir Stojanovic http://inst.eecs.berkeley.edu/~cs61c/fa15 1 Components of a Computer Processor Control Enable? Read/Write

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #19 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker CS61C L19 CPU Design : Designing a Single-Cycle CPU

More information

Review. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU

Review. N-bit adder-subtractor done using N 1- bit adders with XOR gates on input. Lecture #19 Designing a Single-Cycle CPU CS6C L9 CPU Design : Designing a Single-Cycle CPU () insteecsberkeleyedu/~cs6c CS6C : Machine Structures Lecture #9 Designing a Single-Cycle CPU 27-7-26 Scott Beamer Instructor AI Focuses on Poker Review

More information

CPU Organization (Design)

CPU Organization (Design) ISA Requirements CPU Organization (Design) Datapath Design: Capabilities & performance characteristics of principal Functional Units (FUs) needed by ISA instructions (e.g., Registers, ALU, Shifters, Logic

More information

CS61C : Machine Structures

CS61C : Machine Structures CS 61C L path (1) insteecsberkeleyedu/~cs61c/su6 CS61C : Machine Structures Lecture # path natomy: 5 components of any Computer Personal Computer -7-25 This week Computer Processor ( brain ) path ( brawn

More information

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I ! Nasty new windows vulnerability!

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I ! Nasty new windows vulnerability! inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 18 CPU Design: The Single-Cycle I CS61C L18 CPU Design: The Single-Cycle I (1)! 2010-07-21!!!Instructor Paul Pearce! Nasty new windows vulnerability!

More information

COMP303 Computer Architecture Lecture 9. Single Cycle Control

COMP303 Computer Architecture Lecture 9. Single Cycle Control COMP33 Computer Architecture Lecture 9 Single Cycle Control A Single Cycle Datapath We have everything except control signals (underlined) RegDst busw Today s lecture will look at how to generate the control

More information

ECE170 Computer Architecture. Single Cycle Control. Review: 3b: Add & Subtract. Review: 3e: Store Operations. Review: 3d: Load Operations

ECE170 Computer Architecture. Single Cycle Control. Review: 3b: Add & Subtract. Review: 3e: Store Operations. Review: 3d: Load Operations ECE7 Computer Architecture Single Cycle Control Review: 3a: Overview of the Fetch Unit The common operations Fetch the : mem[] Update the program counter: Sequential Code: < + Branch and Jump: < something

More information

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1 CS 61C: Great Ideas in Computer Architecture (Machine Structures) Lecture 28: Single- Cycle CPU Datapath Control Part 1 Guest Lecturer: Sagar Karandikar hfp://inst.eecs.berkeley.edu/~cs61c/ http://research.microsoft.com/apps/pubs/default.aspx?id=212001!

More information

CS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction

CS 61C: Great Ideas in Computer Architecture. MIPS CPU Datapath, Control Introduction CS 61C: Great Ideas in Computer Architecture MIPS CPU Datapath, Control Introduction Instructor: Alan Christopher 7/28/214 Summer 214 -- Lecture #2 1 Review of Last Lecture Critical path constrains clock

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17 Single Cycle CPU Datapath CPS today! 2005-10-31 There is one handout today at the front and back of the room! Lecturer PSOE, new dad

More information

361 control.1. EECS 361 Computer Architecture Lecture 9: Designing Single Cycle Control

361 control.1. EECS 361 Computer Architecture Lecture 9: Designing Single Cycle Control 36 control. EECS 36 Computer Architecture Lecture 9: Designing Single Cycle Control Recap: The MIPS Subset ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm6 3 3 26 2 6 op rs rt rd

More information

How to design a controller to produce signals to control the datapath

How to design a controller to produce signals to control the datapath ECE48 Computer Organization and Architecture Designing Single Cycle How to design a controller to produce signals to control the datapath ECE48. 2--7 Recap: The MIPS Formats All MIPS instructions are bits

More information

CSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade

CSE 141 Computer Architecture Summer Session Lecture 3 ALU Part 2 Single Cycle CPU Part 1. Pramod V. Argade CSE 141 Computer Architecture Summer Session 1 2004 Lecture 3 ALU Part 2 Single Cycle CPU Part 1 Pramod V. Argade Reading Assignment Announcements Chapter 5: The Processor: Datapath and Control, Sec. 5.3-5.4

More information

CS 110 Computer Architecture Single-Cycle CPU Datapath & Control

CS 110 Computer Architecture Single-Cycle CPU Datapath & Control CS Computer Architecture Single-Cycle CPU Datapath & Control Instructor: Sören Schwertfeger http://shtech.org/courses/ca/ School of Information Science and Technology SIST ShanghaiTech University Slides

More information

Major CPU Design Steps

Major CPU Design Steps Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected

More information

MIPS-Lite Single-Cycle Control

MIPS-Lite Single-Cycle Control MIPS-Lite Single-Cycle Control COE68: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview Single cycle

More information

EEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control

EEM 486: Computer Architecture. Lecture 3. Designing Single Cycle Control EEM 48: Computer Architecture Lecture 3 Designing Single Cycle The Big Picture: Where are We Now? Processor Input path Output Lec 3.2 An Abstract View of the Implementation Ideal Address Net Address PC

More information

CS3350B Computer Architecture Winter Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2)

CS3350B Computer Architecture Winter Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) CS335B Computer Architecture Winter 25 Lecture 5.7: Single-Cycle CPU: Datapath Control (Part 2) Marc Moreno Maza www.csd.uwo.ca/courses/cs335b [Adapted from lectures on Computer Organization and Design,

More information

The Processor: Datapath & Control

The Processor: Datapath & Control Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control Processor Design Step 3 Assemble Datapath Meeting Requirements Build the

More information

CENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu

CENG 3420 Computer Organization and Design. Lecture 06: MIPS Processor - I. Bei Yu CENG 342 Computer Organization and Design Lecture 6: MIPS Processor - I Bei Yu CEG342 L6. Spring 26 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified

More information

Instructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs61c/fa13. Fall Lecture #18. Warehouse Scale Computer

Instructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs61c/fa13. Fall Lecture #18. Warehouse Scale Computer /29/3 CS 6C: Great Ideas in Computer Architecture Building Blocks for Datapaths Instructor: Randy H. Katz hcp://inst.eecs.berkeley.edu/~cs6c/fa3 /27/3 Fall 23 - - Lecture #8 So5ware Parallel Requests Assigned

More information

Review: Abstract Implementation View

Review: Abstract Implementation View Review: Abstract Implementation View Split memory (Harvard) model - single cycle operation Simplified to contain only the instructions: memory-reference instructions: lw, sw arithmetic-logical instructions:

More information

CS359: Computer Architecture. The Processor (A) Yanyan Shen Department of Computer Science and Engineering

CS359: Computer Architecture. The Processor (A) Yanyan Shen Department of Computer Science and Engineering CS359: Computer Architecture The Processor (A) Yanyan Shen Department of Computer Science and Engineering Eecuting R-type Instructions 7 Instructions ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate:

More information

CPU Design Steps. EECC550 - Shaaban

CPU Design Steps. EECC550 - Shaaban CPU Design Steps 1. Analyze instruction set operations using independent RTN => datapath requirements. 2. Select set of datapath components & establish clock methodology. 3. Assemble datapath meeting the

More information

CPE 335 Computer Organization. Basic MIPS Architecture Part I

CPE 335 Computer Organization. Basic MIPS Architecture Part I CPE 335 Computer Organization Basic MIPS Architecture Part I Dr. Iyad Jafar Adapted from Dr. Gheith Abandah slides http://www.abandah.com/gheith/courses/cpe335_s8/index.html CPE232 Basic MIPS Architecture

More information

Recap: A Single Cycle Datapath. CS 152 Computer Architecture and Engineering Lecture 8. Single-Cycle (Con t) Designing a Multicycle Processor

Recap: A Single Cycle Datapath. CS 152 Computer Architecture and Engineering Lecture 8. Single-Cycle (Con t) Designing a Multicycle Processor CS 52 Computer Architecture and Engineering Lecture 8 Single-Cycle (Con t) Designing a Multicycle Processor February 23, 24 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://inst.eecs.berkeley.edu/~cs52/

More information

CS152 Computer Architecture and Engineering Lecture 10: Designing a Single Cycle Control. Recap: The MIPS Instruction Formats

CS152 Computer Architecture and Engineering Lecture 10: Designing a Single Cycle Control. Recap: The MIPS Instruction Formats CS52 Computer Architecture and Engineering Lecture : Designing a Single Cycle February 7, 995 Dave Patterson (patterson@cs) and Shing Kong (shing.kong@eng.sun.com) Slides available on http://http.cs.berkeley.edu/~patterson

More information

Lecture #17: CPU Design II Control

Lecture #17: CPU Design II Control Lecture #7: CPU Design II Control 25-7-9 Anatomy: 5 components of any Computer Personal Computer Computer Processor Control ( brain ) This week ( ) path ( brawn ) (where programs, data live when running)

More information

Adding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20)

Adding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20) Adding Support for jal to Single Cycle Datapath (For More Practice Exercise 5.20) The MIPS jump and link instruction, jal is used to support procedure calls by jumping to jump address (similar to j ) and

More information

Chapter 4. The Processor. Computer Architecture and IC Design Lab

Chapter 4. The Processor. Computer Architecture and IC Design Lab Chapter 4 The Processor Introduction CPU performance factors CPI Clock Cycle Time Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 34 Single Cycle CPU Control I 24-4-16 Lecturer PSOE Dan Garcia www.cs.berkeley.edu/~ddgarcia 1.5 Quake?! NBC movie on May 3 rd. Truth stranger

More information

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1 CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath Control Part 1 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs61c/ Review

More information

Lecture 6 Datapath and Controller

Lecture 6 Datapath and Controller Lecture 6 Datapath and Controller Peng Liu liupeng@zju.edu.cn Windows Editor and Word Processing UltraEdit, EditPlus Gvim Linux or Mac IOS Emacs vi or vim Word Processing(Windows, Linux, and Mac IOS) LaTex

More information

Computer Science 61C Spring Friedland and Weaver. The MIPS Datapath

Computer Science 61C Spring Friedland and Weaver. The MIPS Datapath The MIPS Datapath 1 The Critical Path and Circuit Timing The critical path is the slowest path through the circuit For a synchronous circuit, the clock cycle must be longer than the critical path otherwise

More information

EECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction

EECS150 - Digital Design Lecture 10- CPU Microarchitecture. Processor Microarchitecture Introduction EECS150 - Digital Design Lecture 10- CPU Microarchitecture Feb 18, 2010 John Wawrzynek Spring 2010 EECS150 - Lec10-cpu Page 1 Processor Microarchitecture Introduction Microarchitecture: how to implement

More information

Processor (I) - datapath & control. Hwansoo Han

Processor (I) - datapath & control. Hwansoo Han Processor (I) - datapath & control Hwansoo Han Introduction CPU performance factors Instruction count - Determined by ISA and compiler CPI and Cycle time - Determined by CPU hardware We will examine two

More information

University of California College of Engineering Computer Science Division -EECS. CS 152 Midterm I

University of California College of Engineering Computer Science Division -EECS. CS 152 Midterm I Name: University of California College of Engineering Computer Science Division -EECS Fall 996 D.E. Culler CS 52 Midterm I Your Name: ID Number: Discussion Section: You may bring one double-sided pages

More information

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2

CS 61C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2 CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs6c/ Review:

More information

Recap: The MIPS Subset ADD and subtract EEL Computer Architecture shamt funct add rd, rs, rt Single-Cycle Control Logic sub rd, rs, rt

Recap: The MIPS Subset ADD and subtract EEL Computer Architecture shamt funct add rd, rs, rt Single-Cycle Control Logic sub rd, rs, rt Recap: The MIPS Subset EEL-47 - Computer Architecture Single-Cycle Logic ADD and subtract add rd, rs, rt sub rd, rs, rt OR Imm: ori rt, rs, imm 2 rs rt rd shamt t bits 5 bits 5 bits 5 bits 5 bits bits

More information

ﻪﺘﻓﺮﺸﻴﭘ ﺮﺗﻮﻴﭙﻣﺎﻛ يرﺎﻤﻌﻣ MIPS يرﺎﻤﻌﻣ data path and ontrol control

ﻪﺘﻓﺮﺸﻴﭘ ﺮﺗﻮﻴﭙﻣﺎﻛ يرﺎﻤﻌﻣ MIPS يرﺎﻤﻌﻣ data path and ontrol control معماري كامپيوتر پيشرفته معماري MIPS data path and control abbasi@basu.ac.ir Topics Building a datapath support a subset of the MIPS-I instruction-set A single cycle processor datapath all instruction actions

More information

The Processor: Datapath & Control

The Processor: Datapath & Control Chapter Five 1 The Processor: Datapath & Control We're ready to look at an implementation of the MIPS Simplified to contain only: memory-reference instructions: lw, sw arithmetic-logical instructions:

More information

CS 61C: Great Ideas in Computer Architecture Lecture 12: Single- Cycle CPU, Datapath & Control Part 2

CS 61C: Great Ideas in Computer Architecture Lecture 12: Single- Cycle CPU, Datapath & Control Part 2 CS 6C: Great Ideas in Computer Architecture Lecture 2: Single- Cycle CPU, Datapath & Control Part 2 Instructor: Sagar Karandikar sagark@eecs.berkeley.edu hbp://inst.eecs.berkeley.edu/~cs6c Midterm Results

More information

Systems Architecture

Systems Architecture Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software

More information

Full Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI

Full Datapath. CSCI 402: Computer Architectures. The Processor (2) 3/21/19. Fengguang Song Department of Computer & Information Science IUPUI CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Full Datapath Branch Target Instruction Fetch Immediate 4 Today s Contents We have looked

More information

CENG 3420 Lecture 06: Datapath

CENG 3420 Lecture 06: Datapath CENG 342 Lecture 6: Datapath Bei Yu byu@cse.cuhk.edu.hk CENG342 L6. Spring 27 The Processor: Datapath & Control q We're ready to look at an implementation of the MIPS q Simplified to contain only: memory-reference

More information

Midterm I October 6, 1999 CS152 Computer Architecture and Engineering

Midterm I October 6, 1999 CS152 Computer Architecture and Engineering University of California, Berkeley College of Engineering Computer Science Division EECS Fall 1999 John Kubiatowicz Midterm I October 6, 1999 CS152 Computer Architecture and Engineering Your Name: SID

More information

1048: Computer Organization

1048: Computer Organization 48: Compter Organization Lectre 5 Datapath and Control Lectre5A - simple implementation (cwli@twins.ee.nct.ed.tw) 5A- Introdction In this lectre, we will try to implement simplified IPS which contain emory

More information

Computer and Information Sciences College / Computer Science Department The Processor: Datapath and Control

Computer and Information Sciences College / Computer Science Department The Processor: Datapath and Control Computer and Information Sciences College / Computer Science Department The Processor: Datapath and Control Chapter 5 The Processor: Datapath and Control Big Picture: Where are We Now? Performance of a

More information

Single Cycle Datapath

Single Cycle Datapath Single Cycle atapath Lecture notes from MKP, H. H. Lee and S. Yalamanchili Section 4.1-4.4 Appendices B.3, B.7, B.8, B.11,.2 ing Note: Appendices A-E in the hardcopy text correspond to chapters 7-11 in

More information

EECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer

EECS150 - Digital Design Lecture 9- CPU Microarchitecture. Watson: Jeopardy-playing Computer EECS150 - Digital Design Lecture 9- CPU Microarchitecture Feb 15, 2011 John Wawrzynek Spring 2011 EECS150 - Lec09-cpu Page 1 Watson: Jeopardy-playing Computer Watson is made up of a cluster of ninety IBM

More information

Single Cycle Datapath

Single Cycle Datapath Single Cycle atapath Lecture notes from MKP, H. H. Lee and S. Yalamanchili Section 4.-4.4 Appendices B.7, B.8, B.,.2 Practice Problems:, 4, 6, 9 ing (2) Introduction We will examine two MIPS implementations

More information

Single Cycle CPU Design. Mehran Rezaei

Single Cycle CPU Design. Mehran Rezaei Single Cycle CPU Design Mehran Rezaei What does it mean? Instruction Fetch Instruction Memory clk pc 32 32 address add $t,$t,$t2 instruction Next Logic to generate the address of next instruction The Branch

More information

Designing a Multicycle Processor

Designing a Multicycle Processor Designing a Multicycle Processor Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras Multicycle-

More information

CS Computer Architecture Spring Week 10: Chapter

CS Computer Architecture Spring Week 10: Chapter CS 35101 Computer Architecture Spring 2008 Week 10: Chapter 5.1-5.3 Materials adapated from Mary Jane Irwin (www.cse.psu.edu/~mji) and Kevin Schaffer [adapted from D. Patterson slides] CS 35101 Ch 5.1

More information

Topic #6. Processor Design

Topic #6. Processor Design Topic #6 Processor Design Major Goals! To present the single-cycle implementation and to develop the student's understanding of combinational and clocked sequential circuits and the relationship between

More information

Working on the Pipeline

Working on the Pipeline Computer Science 6C Spring 27 Working on the Pipeline Datapath Control Signals Computer Science 6C Spring 27 MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Imm6 Adder

More information

CSE140: Components and Design Techniques for Digital Systems

CSE140: Components and Design Techniques for Digital Systems CSE4: Components and Design Techniques for Digital Systems Tajana Simunic Rosing Announcements and Outline Check webct grades, make sure everything is there and is correct Pick up graded d homework at

More information

Midterm I March 3, 1999 CS152 Computer Architecture and Engineering

Midterm I March 3, 1999 CS152 Computer Architecture and Engineering University of California, Berkeley College of Engineering Computer Science Division EECS Spring 1999 John Kubiatowicz Midterm I March 3, 1999 CS152 Computer Architecture and Engineering Your Name: SID

More information

Mark Redekopp and Gandhi Puvvada, All rights reserved. EE 357 Unit 15. Single-Cycle CPU Datapath and Control

Mark Redekopp and Gandhi Puvvada, All rights reserved. EE 357 Unit 15. Single-Cycle CPU Datapath and Control EE 37 Unit Single-Cycle CPU path and Control CPU Organization Scope We will build a CPU to implement our subset of the MIPS ISA Memory Reference Instructions: Load Word (LW) Store Word (SW) Arithmetic

More information

CSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Today s Content

CSCI 402: Computer Architectures. Fengguang Song Department of Computer & Information Science IUPUI. Today s Content 3/6/8 CSCI 42: Computer Architectures The Processor (2) Fengguang Song Department of Computer & Information Science IUPUI Today s Content We have looked at how to design a Data Path. 4.4, 4.5 We will design

More information

Chapter 4. The Processor

Chapter 4. The Processor Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified

More information

UC Berkeley CS61C : Machine Structures

UC Berkeley CS61C : Machine Structures inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures The Internet is broken?! The Clean Slate team at Stanford wants to revamp the Internet, making it safer (from viruses), more reliable

More information

Midterm I March 12, 2003 CS152 Computer Architecture and Engineering

Midterm I March 12, 2003 CS152 Computer Architecture and Engineering University of California, Berkeley College of Engineering Computer Science Division EECS Spring 2003 John Kubiatowicz Midterm I March 2, 2003 CS52 Computer Architecture and Engineering Your Name: SID Number:

More information

Chapter 4. The Processor

Chapter 4. The Processor Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware 4.1 Introduction We will examine two MIPS implementations

More information

The MIPS Processor Datapath

The MIPS Processor Datapath The MIPS Processor Datapath Module Outline MIPS datapath implementation Register File, Instruction memory, Data memory Instruction interpretation and execution. Combinational control Assignment: Datapath

More information

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 19 CPU Design: The Single-Cycle II & Control !

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 19 CPU Design: The Single-Cycle II & Control ! inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture 9 CPU Design: The Single-Cycle II & Control 2-7-22!!!Instructor Paul Pearce! Dell may have shipped infected motherboards! Dell is warning

More information

Chapter 5: The Processor: Datapath and Control

Chapter 5: The Processor: Datapath and Control Chapter 5: The Processor: Datapath and Control Overview Logic Design Conventions Building a Datapath and Control Unit Different Implementations of MIPS instruction set A simple implementation of a processor

More information

CS222: Processor Design

CS222: Processor Design CS222: Processor Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Processor Design building blocks Outline A simple implementation: Single Cycle Data pathandcontrol

More information

CS 61C: Great Ideas in Computer Architecture Control and Pipelining

CS 61C: Great Ideas in Computer Architecture Control and Pipelining CS 6C: Great Ideas in Computer Architecture Control and Pipelining Instructors: Vladimir Stojanovic and Nicholas Weaver http://inst.eecs.berkeley.edu/~cs6c/sp6 Datapath Control Signals ExtOp: zero, sign

More information

The Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

The Processor: Datapath and Control. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University The Processor: Datapath and Control Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Introduction CPU performance factors Instruction count Determined

More information

Systems Architecture I

Systems Architecture I Systems Architecture I Topics A Simple Implementation of MIPS * A Multicycle Implementation of MIPS ** *This lecture was derived from material in the text (sec. 5.1-5.3). **This lecture was derived from

More information

Single Cycle Data Path

Single Cycle Data Path Single ycle ata Path S 365 Lecture 6 Prof. Yih Huang S365 1 MIPS Lite We're ready to look at an implementation of the MIPS Simplified to support only: memory-reference instructions: lw, sw arithmetic-logical

More information

CpE 442. Designing a Multiple Cycle Controller

CpE 442. Designing a Multiple Cycle Controller CpE 442 Designing a Multiple Cycle Controller CPE 442 multicontroller.. Outline of Today s Lecture Recap (5 minutes) Review of FSM control (5 minutes) From Finite State Diagrams to Microprogramming (25

More information

ECE468 Computer Organization and Architecture. Designing a Multiple Cycle Controller

ECE468 Computer Organization and Architecture. Designing a Multiple Cycle Controller ECE468 Computer Organization and Architecture Designing a Multiple Cycle Controller ECE468 multicontroller Review of a Multiple Cycle Implementation The root of the single cycle processor s problems: The

More information

Chapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations

Chapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations Chapter 4 The Processor Part I Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations

More information

UC Berkeley CS61C : Machine Structures

UC Berkeley CS61C : Machine Structures inst.eecs.berkeley.edu/~cs6c UC Berkeley CS6C : Machine Structures Lecture 26 Single-cycle CPU Control 27-3-2 Exhausted TA Ben Sussman www.icanhascheezburger.com Qutrits Bring Quantum Computers Closer:

More information

361 multipath..1. EECS 361 Computer Architecture Lecture 10: Designing a Multiple Cycle Processor

361 multipath..1. EECS 361 Computer Architecture Lecture 10: Designing a Multiple Cycle Processor 36 multipath.. EECS 36 Computer Architecture Lecture : Designing a Multiple Cycle Processor Recap: A Single Cycle Datapath We have everything except control signals (underline) Today s lecture will show

More information

The Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture

The Processor. Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut. CSE3666: Introduction to Computer Architecture The Processor Z. Jerry Shi Department of Computer Science and Engineering University of Connecticut CSE3666: Introduction to Computer Architecture Introduction CPU performance factors Instruction count

More information

Lecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang

Lecture 12: Single-Cycle Control Unit. Spring 2018 Jason Tang Lecture 12: Single-Cycle Control Unit Spring 2018 Jason Tang 1 Topics Control unit design Single cycle processor Control unit circuit implementation 2 Computer Organization Computer Processor Memory Devices

More information

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor

COMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 4. The Processor COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle

More information

The overall datapath for RT, lw,sw beq instrucution

The overall datapath for RT, lw,sw beq instrucution Designing The Main Control Unit: Remember the three instruction classes {R-type, Memory, Branch}: a) R-type : Op rs rt rd shamt funct 1.src 2.src dest. 31-26 25-21 20-16 15-11 10-6 5-0 a) Memory : Op rs

More information

Lecture 10: Simple Data Path

Lecture 10: Simple Data Path Lecture 10: Simple Data Path Course so far Performance comparisons Amdahl s law ISA function & principles What do bits mean? Computer math Today Take QUIZ 6 over P&H.1-, before 11:59pm today How do computers

More information

ELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control

ELEC 5200/6200 Computer Architecture and Design Spring 2017 Lecture 4: Datapath and Control ELEC 52/62 Computer Architecture and Design Spring 217 Lecture 4: Datapath and Control Ujjwal Guin, Assistant Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849

More information

If you didn t do as well as you d hoped

If you didn t do as well as you d hoped 7/3/5 CS 6C: Great Ideas in Computer Architecture Midterm Results Lecture 2: Single- Cycle CPU, path & Control Part 2 ructor: Sagar Karandikar sagark@eecsberkeleyedu hfp://insteecsberkeleyedu/~cs6c You

More information

Lecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1

Lecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1 Lecture 3: The Processor (Chapter 4 of textbook) Chapter 4.1 Introduction Chapter 4.1 Chapter 4.2 Review: MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions small number

More information

ECE260: Fundamentals of Computer Engineering

ECE260: Fundamentals of Computer Engineering Datapath for a Simplified Processor James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy Introduction

More information

ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller. Review of a Multiple Cycle Implementation

ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller. Review of a Multiple Cycle Implementation ECE 6 Computer Architecture Lecture : Designing a Multiple Cycle ler 6 multicontroller. Review of a Multiple Cycle Implementation The root of the single cycle processor s problems: The cycle time has to

More information

ECE473 Computer Architecture and Organization. Processor: Combined Datapath

ECE473 Computer Architecture and Organization. Processor: Combined Datapath Computer Architecture and Organization Processor: Combined path Lecturer: Prof. Yifeng Zhu Fall, 2014 Portions of these slides are derived from: Dave Patterson CB 1 Where are we? Want to build a processor

More information

CS 152 Computer Architecture and Engineering. Lecture 10: Designing a Multicycle Processor

CS 152 Computer Architecture and Engineering. Lecture 10: Designing a Multicycle Processor CS 152 Computer Architecture and Engineering Lecture 1: Designing a Multicycle Processor October 1, 1997 Dave Patterson (http.cs.berkeley.edu/~patterson) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/

More information

ECE369. Chapter 5 ECE369

ECE369. Chapter 5 ECE369 Chapter 5 1 State Elements Unclocked vs. Clocked Clocks used in synchronous logic Clocks are needed in sequential logic to decide when an element that contains state should be updated. State element 1

More information

LECTURE 5. Single-Cycle Datapath and Control

LECTURE 5. Single-Cycle Datapath and Control LECTURE 5 Single-Cycle Datapath and Control PROCESSORS In lecture 1, we reminded ourselves that the datapath and control are the two components that come together to be collectively known as the processor.

More information

CSE 141 Computer Architecture Summer Session I, Lecture 3 Performance and Single Cycle CPU Part 1. Pramod V. Argade

CSE 141 Computer Architecture Summer Session I, Lecture 3 Performance and Single Cycle CPU Part 1. Pramod V. Argade CSE 141 Computer Architecture Summer Session I, 2005 Lecture 3 Performance and Single Cycle CPU Part 1 Pramod V. Argade CSE141: Introduction to Computer Architecture Instructor: Pramod V. Argade (p2argade@cs.ucsd.edu)

More information