COMP303 - Computer Architecture Lecture 8. Designing a Single Cycle Datapath
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1 COMP33 - Computer Architecture Lecture 8 Designing a Single Cycle Datapath
2 The Big Picture The Five Classic Components of a Computer Processor Input Control Memory Datapath Output
3 The Big Picture: The Performance Perspective Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction Inst. Count CPI Cycle Time Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction Single cycle processor - one clock cycle per instruction Advantages: Simple design, low CPI Disadvantages: Long cycle time, which is limited by the slowest instruction.
4 How to Design a Processor: step-by-step Analyze instruction set => datapath requirements the meaning of each instruction is given by register transfers R[rd] < R[rs] + R[rt]; datapath must include storage element for ISA registers datapath must support each register transfer Select set of datapath components and establish clocking methodology Design datapath to meet the requirements Analyze implementation of each instruction to determine setting of control points that effects the register transfer. Design the control logic
5 Review: MIPS Instruction Formats All MIPS instructions are bits long. The three instruction formats are: R-type 6 bits op 5bits rs 5 bits rt 5 bits rd 5 bits shamt 6 bits funct I-type 6 bits op 5 bits rs 5 bits rt 16 bits immediate J-type 6 bits op 26 bits target address The different fields are: op : basic operation of the instruction (opcode) rs, rt, rd : source and destination register specifier shamt : shift amount funct : selects the variant of the operation in the op field immediate : address offset or immediate value target address : target address of the jump instruction
6 Step 1a: The MIPS Subset for Today R-Type: add rd, rs, rt sub rd, rs, rt and rd, rs, rt or rd, rs, rt slt rd, rs, rt LOAD and STORE: lw rt, rs, imm16 sw rt, rs, imm16 BRANCH: beq rs, rt, imm op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 16 bits op rs rt immediate 6 bits 5 bits 5 bits 16 bits
7 Register Transfer Logic (RTL) RTL gives the meaning of the instructions All instructions start by fetching the instruction op rs rt rd shamt funct = MEM[ PC ] op rs rt Imm16 = MEM[ PC ] inst Register Transfers add R[rd] R[rs] + R[rt]; PC PC + 4 sub R[rd] R[rs] R[rt]; PC PC + 4 load R[rt] MEM[ R[rs] + sign_ext(imm16)]; PC PC + 4 store MEM[ R[rs] + sign_ext(imm16) ] R[rt]; PC PC + 4 beq if ( R[rs] == R[rt] ) then PC PC sign_ext(imm16)] else PC PC + 4
8 Step 1: Requirements of the Instruction Set Memory instruction & data Registers ( x ) read rs read rt write rt or rd PC Sign extender Add and sub register or extended immediate Add 4 and/or shifted extended immediate to PC
9 Step 2: Components of the Datapath Adder MUX A B Adder Select CarryIn Sum Carry ALU A B A B MUX ALU OP 3 Y Result Combinational Logic: Does not use a clock
10 Storage Element: Register (Basic Building Blocks) Register Similar to the D Flip Flop except N-bit input and output Write enable input Write Enable: negated (): Data Out will not change Data In N Write Enable asserted (1): Data Out will become Data In on the falling edge of the clock Data Out N
11 Storage Element: Register File Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: RA (number) selects the register to put on busa (data) RB (number) selects the register to put on busb (data) RW (number) selects the register to be written via busw (data) when Write Enable is 1 Clock input (CLK) RW RA RB Write Enable busw -bit Registers busa busb The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: RA or RB valid => busa or busb valid after access time.
12 Read from Register File
13 Write to Register File
14 Storage Element: Memory Memory One input bus: Data In One output bus: Data Out Memory word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus Clock input (CLK) Write Enable Address Data In DataOut The CLK input is a factor ONLY during write operation During read operation, memory behaves as a combinational logic block: Address valid => Data Out valid after access time.
15 Step 3 Register Transfer Requirements > Datapath Design Instruction Fetch Decode instructions and Read Operands Execute Operation Write back the result
16 3a: Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[pc] Update the program counter: Sequential Code: PC PC + 4 Branch and Jump: PC something else PC Next Address Logic Address Instruction Memory Instruction Word
17 3b: R-Type Instructions R[rd] R[rs] op R[rt] Example: add rd, rs, rt Ra, Rb, and Rw come from instruction s rs, rt, and rd fields ALUctr and RegWr: control logic after decoding the instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits RegWr busw Rd Rs Rw Ra Rb -bit Registers Rt busa busb ALUctr 3 ALU Result
18 3c: Load Operations R[rt] Mem[R[rs] + SignExt[imm16] Example: lw rt, rs, imm16 busw 31 RegDst Rd Rt Rs Rt RegWr imm16 Rw Ra Rb -bit Registers op rs rt immediate 6 bits 5 bits 5 bits rd 16 bits busb Sign Extender busa ALUSrc ALUctr 3 ALU Data In MemWr WrEn 11 Adr Data Memory MemtoReg MemRd
19 3d: Store Operations Mem[R[rs]+SignExt[imm16]] R[rt] 31 Example: sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits 16 bits RegDst Rd Rt ALUctr MemWr MemtoReg busw RegWr imm Rs 5 Rw Ra Rb -bit Registers 16 Rt busb Sign Extender busa 3 ALU Data In WrEn Adr Data Memory ALUSrc MemRd
20 3e: The Branch Instruction op rs rt immediate 6 bits 5 bits 5 bits 16 bits 16 beq rs, rt, imm16 mem[pc] Fetch the instruction from memory Equal R[rs] == R[rt] Calculate the branch condition if (Equal && Branch Instr.) Calculate the next instruction s address PC PC ( SignExt(imm16) x 4 ) else PC PC + 4
21 Datapath for Branch Operations beq rs, rt, imm op rs rt immediate 6 bits 5 bits 5 bits 16 bits Branch Inst Address imm16 4 npc_sel Adder Adder PC Ext 1 PC busw RegWr Rs Rw Ra Rb -bit Registers Rt busa busb Equal ALU
22 Putting it All Together: A Single Cycle Datapath Inst Memory Adr <21:25> <16:2> <11:15> <:15> Instruction<31:> Rs Rt Rd Imm16 npc_sel RegDst Rd Rt Equal ALUctr MemWr MemtoReg RegWr 5 5 Rs 5 Rt imm16 PC Ext Adder Adder PC busw imm16 Rw Ra Rb -bit Registers 16 busa busb Sign Extende r 1 = Data In ALU WrEn Adr Data Memory 1 ALUSrc MemRd
23 Different View of Same Implementation (From Book) 4 Add RegDst Branch Shift left 2 Add ALU result M u x 1 Instruction [31-26] Control MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite PC Read Address Instruction [31-] Instruction memory Instruction [25-21] Instruction [2-16] Instruction [15-11] M u x 1 Read reg 1 Read reg 2 Write register Write data Read data 1 Registers Read data 2 M u x 1 ALU zero ALU result Address Write data Read data Data memory 1 M u x Instruction [15-] 16 Sign extend ALU control Instruction [5-]
24 Step 4: Given Datapath: RTL Control Instruction<31:> Inst Memory Adr Op <26:31> Fun <:5> Control npc_sel RegWr RegDst ALUSrc ALUctr MemWr MemRd MemtoReg Equal DATA PATH
25 Meaning of the Control Signals Rs, Rt, Rd and Imm16 hardwired into datapath npc_sel: => PC PC + 4; 1 => PC PC SignExt(Im16) npc_sel 4 imm16 PC Ext Adder Adder PC 1 Inst Memory Adr
26 Meaning of the Control Signals ALUsrc: => regb; 1 => immed MemRd: read memory MemWr: write memory ALUctr: add, sub, and, or, set less than RegDst Rd Rt Equal ALUctr MemWr MemtoReg 1 3 RegWr Rs Rt busa busw Rw Ra Rb = -bit Registers busb WrEn Adr 1 Data In imm16 Data 16 Memory 1 Sign Extender RegWr: write dest register MemtoReg: => ALU; 1 => Mem RegDst: ALU => rt ; 1 => rd ALUSrc MemRd
27 Example: Load Instruction Inst Memory Adr Rs <21:25> <:15> <11:15> <16:2> Rt Rd Imm16 Instruction<31:> imm16 4 PC Ext Adder Adder npc_sel +4 1 PC RegDst rt RegWr busw 1 imm16 Rd Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 16 Rt busa busb Sign Extende r Equal 1 ext ALUctr add = ALU MemWr WrEn Adr Data In Data Memory MemtoReg 1 ALUSrc MemRd
28 An Abstract View of the Implementation Next Address Ideal Instruction Memory Instruction Address PC Rd 5 Instruction Rs 5 Rt 5 Rw Ra Rb -bit Registers A B Control Control Signals ALU Conditions Data Address Data In Ideal Data Memory Data Out Datapath
29 Summary 5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Design datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Design the control logic MIPS makes it easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Single cycle datapath => CPI=1, CCT => long Next time: implementing control
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