Altera 器件高级特性与应用 内容安排 时钟管理 时钟管理 片内存储器 数字信号处理 高速差分接口 高速串行收发器. 时钟偏斜 (skew): 始终分配到系统中到达各个时钟末端 ( 器件内部触发器的时钟输入端 ) 的时钟相位不一致的现象 抖动 : 时钟边沿的输出位置和理想情况存在一定的误差

Transcription

1 4-E Altera 器件高级特性与应用 西安电子科技大学雷达信号处理重点实验室罗丰 内容安排 时钟管理 片内存储器 数字信号处理 高速差分接口 高速串行收发器 2 时钟管理 时钟偏斜 (skew): 始终分配到系统中到达各个时钟末端 ( 器件内部触发器的时钟输入端 ) 的时钟相位不一致的现象 抖动 : 时钟边沿的输出位置和理想情况存在一定的误差 3 1

2 全局时钟网络 到达各个目的点的偏斜最小 Global Clock Networks CLK[15..12] 高扇出的控制信号 : 可以减小大扇出数对路径延时的影响, 大大提高设计的性能, 而且能够节省逻辑资源, 防止综合与布线工具对逻辑的复制 CLK[3..0] CLK[7..4] CLK[11..8] 4 Quartus 中全局时钟的设置选项 高扇出时钟设置到全局时钟 高扇出触发信号设置到全局时钟 5 单个节点不选择全局时钟网络 6 2

3 锁相环的应用 PLLs provide clock synthesis and management for on-chip clocks, external system clocks, and high-speed I/O interfaces reference clock PFD CP LF VCO phase taps feedback clock m PLLs align input reference clock to feedback clock using phasefrequency detector (PFD) circuit loop filter (LF) and charge pump (CP) use output signals from PFD to bias voltage controlled oscillator (VCO) VCO bias determines its operational frequency 7 锁相环的应用 Stratix II PLL Locations Enhanced PLLs CLK[12..15] 5 11 FPLL7CLK 7 RCLK[14-15] RCLK[12-13] 10 FPLL10CLK RCLK[0-1] GCLK[12-15] RCLK[10-11] Fast PLLs CLK[0..3] 1 2 GCLK[0-3] Q1 Q4 Q2 Q3 GCLK[8-11] 4 3 CLK[8..11] Fast PLLs RCLK[2-3] GCLK[4-7] RCLK[8-9] FPLL8CLK 8 RCLK[4-5] RCLK[6-7] 9 FPLL9CLK 6 12 CLK[4..7] Enhanced PLLs 8 增强型锁相环内部结构图 9 3

4 锁相环的工作模式 PLL Mode EPLL FPL L Description Normal (default) CLKx pin in phase with internal clock network Phase offset will exist on PLLx_OUT pin (if used) Zero Delay Buffer Input clock aligned with dedicated external clock output Must use external PLLx_OUT pin CLKx pin in phase with PLLx_OUT pin External Feedback Input clock aligned with external feedback input for synchronizing multi-chip systems Stratix: use external PLLx_OUT and PLLx_FB pins Stratix II: feed any output to the inputs No Compensation No compensation for best jitter performance Source Synchronous Clock-to-data relationship at input pin (setup/hold) maintained at the IOE register (Stratix II only) 10 Normal Mode Clock at Input Pin Aligned with Clock at IOE or Core Register, such that Clock Delay is 0 11 Zero Delay Buffer Mode External Dedicated Clock Output Aligned With Reference Input Clock (output clock tco is 0) Ideal for System Clock Generation & Synthesis (1) The internal clock output can lead or lag the PLL clock output signals 12 4

5 External Feedback Mode External Feedback Input is Aligned With Reference Input Clock 13 No Compensation Mode Clock Delay Within the FPGA is Not Compensated Provides Best Jitter Performance 14 Source Synchronous Mode Clock Delay is Matched with Data Delay to IOE Input Register Ideal for Source Synchronous Transfers W/O SERDES Data pin clk[] pin Data at register port Clock-to-Data Relationship Maintained Clock at register port 15 5

6 Generating PLLs Select the ALTPLL Megafunction for Stratix, Stratix II 16 Generating PLLs Input Clock Frequency Device Family PLL Type Operating Modes 17 ALTPLL Megafunction Modify Bandwidth of EPLL Spread Spectrum Settings 18 6

7 ALTPLL Megafunction Configure Each Output Tap Output Parameter Settings 19 PLL 的电源设计 20 片内存储器 Altera 的 FPGA 有 3 种内嵌的 RAM 块, 分别是 512bit 的 M512,4kbit 的 M4K, 以及 512kbit 的 M-RAM Device EP2S15 Total RAM Bits 419,328 M-RAM Blocks 0 M4K Blocks 78 M512 Blocks 104 EP2S30 1,369, EP2S60 2,544, EP2S90 4,520, EP2S130 6,747, EP2S180 9,383,

8 Single-Port RAM Single-Port RAM Read & Write Address Are the Same Port Supports Non- Simultaneous Read or Write Operation All Inputs Registered Clocking Options Single Port Clocking Mode address[ ] data[ ] wren inclock inclocken inaclr Single-Port RAM q[ ] outclock outclocken outaclr 22 Simple Dual-Port RAM( 伪双端口 RAM) Simple Dual-Port RAM Separate Read & Write Ports Supports Simultaneous Read and Write data[ ] All Inputs Registered wren Clocking Options inaclr Input/Output Clock Mode Read/Write Clock Mode Simple Dual-Port RAM wraddress[ ] inclock inclocken rdaddress[ ] rden q[ ] outclock outclocken outaclr 23 True Dual-Port RAM True Dual-Port RAM Port A & Port B Supports Simultaneous Read and Write On Either Address All Inputs Registered Clocking Options Input/Output Clock Mode Independent Clock Mode data A [ ] address A [ ] wren A clock A clocken A aclr A q A [ ] True Dual-Port RAM A B data B [ ] address B [ ] wren B clock B clocken B aclr B q B [ ] 24 8

9 FIFO First in First Out Memory Ideal for Rate Changing All Inputs Are Registered Outputs Are All Combinational Clocking Options Single Clock Read/Write Clock Mode 25 ROM Read Only Memory All Inputs Are Registered Clocking Options Single Clock Input/Output Clock M512/M4K Blocks Only for Stratix 26 Shift Register Mode Example : 8 Bit Bus, 4 Bits per Tap, 4 Taps M=4 Bus Data Stream W=8 8 Tap1 Outputs Feedback to Input 8 8 Tap2 Tap3 N=4 8 Tap4 M512/M4K Block 27 9

10 RAM 实现固定系数乘法 28 DSP 资源 Input Register Pipeline Register Output Mux Output Register 4 个 个 99 + clk[0..3] aclr[0..3] clk_en[0..3] Add/Sub/Acc Summation Unit 用上 2 个加法单元和 1 个求和总单元 3636 的乘法器 29 DSP 块几种工作模式 简单的乘法器模式 乘累加模式 乘加模式 30 10

11 Simple Multiplier (18x18) Input Register Pipeline Register Output Mux Output Register + Functional Flow Only Unavailable 31 Simple Multiplier (36x36) Input Register Pipeline Register Output Mux A[17:0] B[17:0] A[35:18] B[35:18] + A[35:18] B[17:0] A[17:0] B[35:18] Output Register Functional Flow Only Partial Product Summation 32 Multiply Accumulate (18x18) Input Register Pipeline Register Output Mux Output Register + Functional Flow Only Unavailable 33 11

12 Two Multiplier Adder (18x18) Input Register Pipeline Register Output Mux Output Register + Functional Flow Only Subtract Unavailable 34 Four Multipliers Adder (18x18) Input Register Pipeline Register Output Mux Output Register + Functional Flow Only 35 Software Implementation Quartus II Support for DSP Blocks Includes: ALTMULT_ADD Supports Multipliers/adders ALTMULT_ACCUM(MAC) Multiply-accumulate Function ALTFP_MULT Floating Point Multiply ALTMEMMULT Puts Multipliers In Memory Blocks Configurable via MegaWizard 36 12

13 Located In Arithmetic Folder 37 ALTMULT_ADD Select # of Multipliers Data Widths Signed vs. Unsigned 38 ALTMULT_ADD Serial Shift Out Implementation Add/Subtract/Dynamic Control 39 13

14 典型应用 FIR Filter Equation and Architecture: y( n) = h( k)* x( n) = N 1 k= 0 h( k) x( n k) Input Time Samples x(n) Z -1 x(n-1) Z -1 x(n-n+2) Z -1 x(n-n+1) h(0) h(1) h(n-2) h(n-1) y(n) 40 FIR Filtering in DSP Block x(n) h(1) x(n)*h(1) A h(2) A x(n-1)*h(2) DSP Block 1 DSP Block 2 h(3) x(n-2)*h(3) A h(3) x(n-3)*h(4) 41 高速差分接口 APE 20KE/20KC 840 Mbps 16 High-Speed Channels LVDS I/O Standard APE II 1 Gbps 36 High-Speed Channels LVDS, LVPECL, PCML, HyperTransport Flexible-LVDS Solution Clock-Data Synchronization (CDS) Stratix 840 Mbps Up to 136 High-Speed Channels Differential I/O Support: LVDS, LVPECL, PCML, HyperTransport Flexible-LVDS Solution Data Realignment Stratix II 1 Gbps Up to 156 Tx and 152 Rx High-Speed Channels Differential I/O Support: LVDS, HyperTransport Data Realignment on per channel basis Dynamic Phase Alignment (DPA) Stratix G 1 Gbps Up to 45 High-Speed Channels Differential I/O Support: LVDS, LVPECL, PCML, HyperTransport Data Realignment on per channel basis Dynamic Phase Alignment (DPA) 42 14

15 On-Chip Differential Termination On-Chip 100Ω, Differential Termination Supports LVDS and HyperTransport Driving LVDS Device Z 0 = 50Ω External Termination Resistor Receiving Stratix II Device Z 0 = 50 Ω No Longer Required LVDS Buffer On-Chip Differential Termination 43 Dynamic Phase Alignment DPA Generates Several Phases of the Clock & Uses Optimum Phase for Each Channel Without DPA With DPA Clk D0 D1 Sample Too Close to Edge Sample At Optimum Point 44 DPA 电路原理 Fast PLL 输出的 8 个不同相位的高速时钟对输入的数据分别采样 判断出该数据翻转的位置, 选出一个位与有效数据中部的时钟来采样数据 Data D0 D1 D2 D3 D4 Dn T VCO 0.125T VCO 45 15

16 高速 LVDS 收发器 Supports x1 output clocks Clock generated by the PLL can be divided down Logic is automatically generated by Quartus II MegaWizard Stratix II Logic Array Transmitter Circuit Parallel Series Txout+ Txout- P L L xw TLOADEN Example: Divide x10 Output Clock 46 MegaWizard ALTLVDS 47 LVDS Transmitter Selection changes with SerDes Factor and Data Rate Select External PLL Here Input and Output Phase Alignment Options 48 16

17 Transmit Phase Alignment Single PLL can be used to compensate for input clock-data alignment as well as output clock-data alignment Input Data Output Data.. Input Clock Output Clock. S K E W Down Stream Device 49 Why Serial? Parallel Interface Worked for Short Distances & Slow Data Rates Longer Distances and Faster Data Rates Create Timing Difficulties Tight Skew & Timing Budget Wider Interfaces Introduce Host Of Issues Higher Pin Count, Increased Power, Wider Connectors, More Complex Layout Simultaneous Switching Noise and EMI Higher Skew and Tight Timing Budget Serialization Solves Most of These Problems 50 Stratix G Transceiver Channel Optional Equalization Serial-to- Parallel Clock Recovery Unit Pattern Detector & Word Aligner Recovered Clock to Core Rate Matcher & Channel Aligner 8B/10B Decoder Synchronizer Rx PLL Receive Transmit Tx PLL Optional Pre-Emphasis Parallelto-Serial 8B/10B Encoder Synchcronizer 51 17

18 Backplane Example Backplane: 30 Trace (FR-4) Stratix G Board: 5 on Both Sides Data Rate: Gbps Point A Point B Stratix G Device 40 Daughter Card Drawing Not To Scale Connector Backplane 52 Pre-Emphasis Opens the Eye Length: 40 Data Rate: Gbps Output Voltage: 400 mv (Differential) Point A Point B Pre-emphasis OFF Scope Photo Scope Photo 53 Pre-Emphasis Opens the Eye Length: 40 Data Rate: Gbps Output Voltage: 400 mv (Differential) Point A Point B Pre-emphasis Set To 1 Scope Photo Good Scope Photo 54 18

19 Pre-Emphasis Opens the Eye Length: 40 Data Rate: Gbps Output Voltage: 400 mv (Differential) Point A Point B Pre-emphasis Set To 2 Scope Photo Better Scope Photo 55 Pre-Emphasis Opens the Eye Length: 40 Data Rate: Gbps Output Voltage: 400 mv (Differential) Point A Point B Pre-emphasis Set To 3 Best Scope Photo Scope Photo 56 Equalizer Opens the Eye Length: 40 Data Rate: Gbps Output Voltage: 400 mv (Differential) Point A 200 mv Point B 100 mv 0 mv -100 mv Pre-emphasis OFF -200 mv Equalizer OFF Scope Photo Simulation Results 57 19

20 Equalizer Opens the Eye Length: 40 Data Rate: Gbps Output Voltage: 400 mv (Differential) Point A 200 mv Point B 100 mv 0 mv -100 mv Pre-emphasis OFF -200 mv Equalizer Set to 4 Scope Photo Simulation Results 58 20