基于 Davinci 平台的视频应用开发 沈燕飞

Transcription

1 基于 Davinci 平台的视频应用开发 沈燕飞

2 DaVinci 技术发布里程图 2

3 达芬奇五大类平台及目标应用 3

4 TMS320DM6446/3 处理器构架 4

5 TMS320DM643x 处理器构架 5

6 DM355 实现便携式应用的创新 6

7 TMS320DM648/DM647 处理器 7

8 TMS320DM6467 芯片内部框图 8

9 实现多格式高清转码功能解决方案 9

10 DVSDK 工具链 } 完整的开发系统 参考设计以及全面的 ARM/DSP 系统级集成开发环境, 可加速任何数字视频应用的设计与开发 } Digital Video Software Development Kit(DVSDK) } expressdsp Configuration Kit } TMS320DM644x SoCAnalyzer } MontaVista s Linux } Digital Video Evaluation Module } TI third party development boards 10

11 DVSDK 工具链 } expressdsp Configuration Kit } TI svideo, imaging, speech and audio codecs } Custom codecsthat comply with TI sexpressdsp Digital } Media (xdm) algorithm standard } TI scodec engine framework } DSP/BIOS real-time kernel } TI sdsp/bios Link inter-processor communication } technology } TMS320DM644x SoC Analyzer } system interaction } load distribution } bottlenecks in data throughput } other types of behavior 11

12 DVSDK 工具链 DVEVM 允许开发者为 ARM 编写即将投入生产的应用程序代码和使用 DaVinci API 访问 DSP 内核, 从而立即开始针对 DM6443 和 DM6446 器件的应用开发 12

13 DM6467 Block Diagram PCI-32 (33MHz) OR UHPI-32 OR ATA (Parallel) AND UHPI-16 ARM INTC ARM926-EJS (297 MHz) I-Cache 16K TCM RAM 32K ARM SS ARM9 ICECrusher D-Cache 8K Boot ROM 8K L1 I-Cache 32K DSP SS C64x+ (594 MHz) L1 D-Cache 32K L2 Cache 128K HDVICP0 SS ARM968-ES (150/300 MHz) TCM RAM ME IPE MC LF CALC ECD HDVICP1 SS ARM968-ES (150/300 MHz) TCM RAM MC LF CALC ECD SCR 150 MHz GPIO McASP 1-channel McASP 4-channel I2C SPI PWM x2 Timer64 x3 IP Reuse Minor Changes New IP OR AEMIF 16-bit NAND UART x3 OR AEMIF 16-bit SCR 297 / MHz DDR2 DDR2 PHY / DLL / IOs 300 MHz PHY USB 2.0 CPGMAC (10/100/1000) VLYNQ 2.0 TC2 TC3 TC0 TC1 CC EDMA SS PLL PLL VDCE H Anti-alias Filt H-Scaler V-Scaler 4:2:0 <-> 4:2:2 Menu Overlay Shared Mem TSIF VPIF Video Out 2x 8-bit BT.656 or 16-bit BT.1120 Video In 2x 8-bit BT.656 or 16-bit BT.1120 or Raw Cap ICEPick PSC PLL CTRL PLL CTRL JTAG 27 MHz 24 MHz 13

14 DM6467 vs. DM6446 v Addition to DM6447 v PCI (32bit and 33Mhz) v UHPI (16/32 bit mode) New New New New New v Video Port v Video Data Conversion Engine (VDCE) v Transport Stream Interfaces (TSIF) v Clock Reference Generator (CRGEN) v 2 HDVICP not covered here v 2 McASP v 3 UART vchanged/improved v ARM (32KB RAM, 8KB ROM, 16KB I-Cache, and 8 KB D-Cache) vgem (64KB L1P ROM, 32KB L2D, and 128KB L2) v SCR (297 MhzVBUSM, MHz VBUSP and CFG bus) v DDR2 (297 MHz) v 1Gbit Ethernet Mac v EDMA (4 TC) v Same as DM6446 v USB v ATA v GPIO v PWM v TIMER v SPI v VLYNQ v Removed (DM6446 has them but DM6467 does not) v ASP Replaced by McASP v MMC/SD v VICP Replaced by HDVICP v VPSS Replace by VPIF and VDCE 14

15 目标应用 Trans Code MPEG2 HD H.264 HD MPEG2 HD VC-1 HD MPEG2 SD H.264 SD MPEG2 SD VC-1 SD MPEG2 HD H.264 SD MPEG2 HD VC-1 SD HD Decode MPEG2 HD H.264 HD VC-1 HD Trans Rate H.264 HD H.264 HD VC-1 HD VC-1 HD SD Encode/Decode MPEG2 SD H.264 SD VC-1 SD 15

16 VISA 的基本概念 16

17 使用 VISA 的优点 17

18 基于 DaVinCi 平台的软件开发流程 18

19 基于 DaVinCi 平台的软件开发流程 19

20 基于 DaVinCi 平台的软件开发流程 20

21 xdais 和 xdm 算法接口标准 21

22 Video Acceleration Strategies Energy Efficiency GP/DSP With Coprocessors Time to Market DSP (C64+, StarCore, CEVA, Trimedia) General Processor (Intel/ARM) Flexibility Programmable Accelerators Reconfigurable Accelerators (Stretch) Hard-wired ASIC (MPEG-2 Decoders) System Cost Efficiency 22

23 Summary of TI Video Processing Past Today DSP+VICP DSP+HDVICP Higher performance, higher efficiency Future DSP+IVA-HD Improved DSP Core Multiple DSP with programmable acceleration 23 DSP Higher Frequency DSPswith Prog. acceleration Higher performance, fully programmable

24 HDVICP Overview } Architecture } Algorithm-specific hardware accelerators } Multi-format } All fixed kernel functions accelerated } All programmable functions in DSP } High-BW DMA data exchange } Performance } Full HD Decoding (all profile) } 720p single-silicon encoding (baseline profile) } Multi-silicon scalability } Minimum processing delay variation } Programming } Full API support } Command-driven, no assembler needed } Configurable via register control } MB-level codec control } Scalability } Multi-format support } Multi-channel support for sub-hd video } High-BW DMA access to MB-level processing buffers for codec expansion We Are Here Fixed Kernel Functions HDVICP Fixed Kernel Functions Fixed HDVICP Kernel Functions Codec DSP Header Processing Header Processing Header Processing Codec Codec Codec Software DSP Codec Software Codec Software DSP Coding Parameter Controls Coding Parameter Controls Coding Parameter Controls 24

25 HDVICP Capability (based on DM6467 Implementation) HDTV (full 1080i) Decoding MPEG2 (MP) H.264 (BP) VC1 (AP), WMV9 fps HD Encoding MPEG2 (MP) H.264 (BP) VC1 (AP), WMV H.263, MPEG-4 (SP/ASP) SDTV Simultaneous Encode/Decode MPEG2 (MP) H.264 (MP) VC1 (AP), WMV H.263, MPEG4 (SP/ASP) Transcoder H.264 HP Level4, VC1 H.264 MP Level3, VC1 H.264 MP Level3, VC1 H.264 HP Level4, VC1 H.264 Encode (ME= [+/-32,+-24] forward and backward): SD 720p BP 30fps H.264 High Profile Decode SD 1080i 60 fields per sec MPEG2->H.264 Transcoding DSP Load (MCPS) (I) 230(P) DSP Load (MCPS) 34(I) 49(P) 58(B) 204(I) 275(P) 348(B) DSP Load (MCPS)

26 Supported Standards } MPEG1/2 } ISO/IEC } ISO/IEC } MPEG4/H.263 } ISO/IEC } H.264 } ITU-T Rec.H.264 /ISO/IEC , Part 10 } VC1/WMV9 } SMPTE 421M 26

27 Existing VICP Acceleration for < SD Resolution (Davinci) Fn ++ + DSP+iMX Transform Quantization DSP Entropy VLCD Coding NAL - F n-x Reference Frame Inverse DSP Quantization Motion_Est DSP+iMX MC DSP+iMX Inverse DSP+iMX Transform Intra_decision DSP+iMX DSP+iMX Intra_pred ++ F n Reconstructed Deblocking DSP+iMX DSP 27

28 HDVICP Acceleration - Encoder Fn + Transform CALC Quantization CALC CALC Entropy ECD Coding NAL - F n-x Reference Frame Inverse CALC Quantization Motion_Est ME MC Inverse CALC Transform Intra_decision IPE Intra_pred CALC CALC ++ F n Reconstructed Deblocking LPF BS 28

29 HDVICP Acceleration - Decoder Entropy ECD DEC NAL F n-x Ref Frame MC Inverse CALC Quantization Inverse CALC Transform Intra_pred CALC CALC ++ F n Recon Frame Deblocking LPF BS 29

30 Review: VICP Fn ++ + DSP+iMX Transform Quantization DSP Entropy VLCD Coding NAL - F n-x Reference Frame Inverse DSP Quantization Motion_Est DSP+iMX MC DSP+iMX Inverse DSP+iMX Transform Intra_decision DSP+iMX DSP+iMX Intra_pred ++ F n Reconstructed Deblocking DSP+iMX DSP 30

31 华清远见 Davinci 课程介绍 } TI 达芬奇 (DaVinCi) 开发高级培训班 } 本课程面向准备使用达芬奇系列 DSP 的软件与系统工程师, 介绍如何运用 TI 提供的各种软件驱动程序与框架组件 快速构建各种应用系统 31

32 Q&A 32

33 33