Cache memories The course that gives CMU its Zip! Cache Memories Oct 11, General organization of a cache memory

Size: px
Start display at page:

Download "Cache memories The course that gives CMU its Zip! Cache Memories Oct 11, General organization of a cache memory"

Transcription

1 5-23 The course that gies CMU its Zip! Cache Memories Oct, 2 Topics Generic cache memory organization Direct mapped caches Set associatie caches Impact of caches on performance Cache memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in L, then in L2, then in main memory. Typical bus structure: CPU chip register file L ALU cache cache bus system bus memory bus L2 cache bus interface I/O bridge main memory 2 Inserting an L cache between the CPU and main memory The transfer unit between the CPU register file and the cache is a 4-byte block. line line The transfer unit between the cache and main memory is a 4-word block (6 bytes). block block 2 block 3 a b c d... p q r s... w x y z... 3 The tiny, ery fast CPU register file has room for four 4-byte words. The small fast L cache has room for two 4-word blocks. The big slow main memory has room for many 4-word blocks. General organization of a cache memory Cache is an array of sets. Each set contains one or more lines. Each line holds a block of data. S = 2 s sets set : set : set S-: bit per line t bits per line B = 2 b bytes per B Cache size: C = B x E x S data bytes 4 B B B B B E lines per set

2 Addressing caches Address A: t bits s bits b bits Direct-mapped cache Simplest kind of cache Characterized by exactly one line per set. set : B B m- <> <set index> <block offset> set : set S-: B B B B The word at address A is in the cache if the bits in one of the <> lines in set <set index> match <>. The word contents begin at offset <block offset> bytes from the beginning of the block. set : set : set S-: E= lines per set 5 6 Accessing direct-mapped caches Set selection Use the set index bits to determine the set of interest. Accessing direct-mapped caches Line matching and word selection find a line in the selected set with a matching (line matching) then extract the word (word selection) set : =? () The bit must be set m- t bits selected set s bits b bits set index block offset set : set S-: selected set (i): (2) The bits in the cache line must match the bits in the address m- t bits w w w 2 w 3 =? (3) If () and (2), then cache hit, and block offset s bits b bits i set index block offset selects starting byte. 7 8

3 Direct-mapped cache simulation t= s=2 b= x xx x () (3) M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [] [] 3 [] 8 [] [] [] (miss) data m[] m[] 8 [] (miss) data m[9] m[8] 9 (2) (4) 3 [] (miss) data m[] m[] m[3] m[2] [] (miss) data m[] m[] m[3] m[2] Why use middle bits as index? High-Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle-Order Bit Indexing Consecutie memory lines map to different cache lines Can hold C-byte region of address space in cache at one time 4-line Cache High-Order Bit Indexing Middle-Order Bit Indexing Set associatie caches Characterized by more than one line per set Accessing set associatie caches Set selection identical to direct-mapped cache set : E=2 lines per set set : set : Selected set set : set S-: m- t bits s bits b bits set index block offset set S-: 2

4 Accessing set associatie caches Line matching and word selection must compare the in each line in the selected set. =? () The bit must be set. Multi-leel caches Options: separate data and instruction caches, or a unified cache Processor TLB selected set (i): w w w 2 w 3 regs L Dcache L Icache L2 Cache Memory disk disk (2) The bits in one of the cache lines must match the bits in the address m- =? t bits s bits b bits i set index block offset (3) If () and (2), then cache hit, and block offset selects starting byte. size: speed: $/Mbyte: line size: 2 B 3 ns 8-64 KB 3 ns 8 B 32 B larger, slower, cheaper -4MB SRAM 6 ns $/MB 32 B 28 MB DRAM 6 ns $.5/MB 8 KB 3 GB 8 ms $.5/MB larger line size, higher associatiity, more likely to write back 3 4 Intel Pentium cache hierarchy Regs. L Data cycle latency 6KB 4-way assoc Write-through 32B lines L Instruction 6KB, 4-way 32B lines Processor Chip L2 Unified 28KB--2 MB 4-way assoc Write-back Write allocate 32B lines Main Memory Up to 4GB Cache performance metrics Miss Rate fraction of memory references not found in cache (misses/references) Typical numbers: Hit Time 3-% for L can be quite small (e.g., < %) for L2, depending on size, etc. time to delier a line in the cache to the processor (includes time to determine whether the line is in the cache) Typical numbers: clock cycle for L 3-8 clock cycles for L2 Miss Penalty additional time required because of a miss Typically 25- cycles for main memory 5 6

5 Writing cache friendly code Repeated references to ariables are good (temporal locality) Stride- reference patterns are good (spatial locality) Example cold cache, 4-byte words, 4-word s The Memory Mountain Read throughput (read bandwidth) Number of bytes read from memory per second (MB/s) Memory mountain Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance. int sumarrayrows(int a[m][n]) { int i, j, sum = ; int sumarraycols(int a[m][n]) { int i, j, sum = ; for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum; for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum; Miss rate = Miss rate = 7 8 Memory mountain test function /* The test function */ oid test(int elems, int stride) { int i, result = ; olatile int sink; for (i = ; i < elems; i += stride) result += data[i]; sink = result; /* So compiler doesn't optimize away the loop */ /* Run test(elems, stride) and return read throughput (MB/s) */ double run(int size, int stride, double Mhz) { double cycles; int elems = size / sizeof(int); test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, ); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* conert cycles to MB/s */ Memory mountain main routine /* mountain.c - Generate the memory mountain. */ #define MINBYTES ( << ) /* Working set size ranges from KB */ #define MAXBYTES ( << 23) /*... up to 8 MB */ #define MAXSTRIDE 6 /* Strides range from to 6 */ #define MAXELEMS MAXBYTES/sizeof(int) int data[maxelems]; /* The array we'll be traersing */ int main() { int size; /* Working set size (in bytes) */ int stride; /* Stride (in array elements) */ double Mhz; /* Clock frequency */ init_data(data, MAXELEMS); /* Initialize each element in data to */ Mhz = mhz(); /* Estimate the clock frequency */ for (size = MAXBYTES; size >= MINBYTES; size >>= ) { for (stride = ; stride <= MAXSTRIDE; stride++) printf("%.f\t", run(size, stride, Mhz)); printf("\n"); exit(); 9 2

6 read throughput (MB/s) Slopes of Spatial Locality s The Memory Mountain s3 stride (words) s5 s7 s9 s s3 mem s5 xe 8m L2 2m 52k 28k L 32k 8k 2k Pentium III Xeon 55 MHz 6 KB on-chip L d-cache 6 KB on-chip L i-cache 52 KB off-chip unified L2 cache Ridges of Tem poral Locality working set size (bytes) Ridges of temporal locality Slice through the memory mountain with stride= illuminates read throughputs of different caches and memory read througput (MB/s) m main memory region 4m 2m 24k 52k 256k L2 cache region 28k 64k 32k working set size (bytes) 6k 8k L cache region 4k 2k k 2 22 A slope of spatial locality Slice through memory mountain with size=256kb shows size. read throughput (MB/s) one access per cache line s s2 s3 s4 s5 s6 s7 s8 s9 s s s2 s3 s4 s5 s6 stride (words) 23 Matrix multiplication example Major Cache Effects to Consider Total cache size Exploit temporal locality and keep the working set small (e.g., by using blocking) Block size /* /* ijk ijk */ */ Variable sum for Exploit spatial locality for (i=; (i=; i<n; i<n; i++) i++) { held in register for for (j=; (j=; j<n; j<n; j++) j++) { sum sum =.;.; for for (k=; (k=; k<n; k<n; k++) k++) sum sum += += a[i][k] a[i][k] * b[k][j]; b[k][j]; Multiply N x N matrices c[i][j] c[i][j] = sum; sum; O(N 3 ) total operations Accesses Description: N reads per source element N alues summed per destination» but may be able to hold in register 24

7 Miss rate analysis for matrix multiply Assume: Line size = 32B (big enough for 4 64-bit words) Matrix dimension (N) is ery large Approximate /N as. Cache is not een big enough to hold multiple rows Analysis Method: Look at access pattern of inner loop i k A k j B i j C Layout of arrays in memory C arrays allocated in row-major order each row in contiguous memory locations Stepping through columns in one row: for (i = ; i < N; i++) sum += a[][i]; accesses successie elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B Stepping through rows in one column: for (i = ; i < n; i++) sum += a[i][]; accesses distant elements no spatial locality! compulsory miss rate = (i.e. %) Matrix multiplication (ijk) Matrix multiplication (jik) /* /* ijk ijk */ */ for for (i=; (i=; i<n; i<n; i++) i++) { for for (j=; (j=; j<n; j<n; j++) j++) { sum sum =.;.; for for (k=; (k=; k<n; k<n; k++) k++) sum sum += += a[i][k] * b[k][j]; c[i][j] = sum; sum;.25.. (i,*) (*,j) (i,j) Row-wise /* /* jik jik */ */ for for (j=; (j=; j<n; j<n; j++) j++) { for for (i=; (i=; i<n; i<n; i++) i++) { sum sum =.;.; for for (k=; (k=; k<n; k<n; k++) k++) sum sum += += a[i][k] * b[k][j]; c[i][j] = sum sum.25.. Row-wise (i,*) (*,j) Columnwise Columnwise (i,j) 27 28

8 Matrix multiplication (kij) Matrix multiplication (ikj) /* kij */ for (k=; k<n; k++) { for (i=; i<n; i++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; (i,k) (k,*) (i,*) /* ikj */ for (i=; i<n; i++) { for (k=; k<n; k++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; (i,k) (k,*) (i,*) Row-wise Row-wise Row-wise Row-wise Matrix multiplication (jki) Matrix multiplication (kji) /* jki */ for (j=; j<n; j++) { for (k=; k<n; k++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r;... (*,k) (k,j) (*,j) Column - wise /* kji */ for (k=; k<n; k++) { for (j=; j<n; j++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r;... (*,k) (k,j) (*,j) Columnwise Columnwise Columnwise 3 32

9 Summary of matrix multiplication ijk (& jik): 2 loads, stores misses/iter =.25 kij (& ikj): 2 loads, store misses/iter =.5 jki (& kji): 2 loads, store misses/iter = 2. Pentium matrix multiply performance Notice that miss rates are helpful but not perfect predictors. Code scheduling matters, too. 6 for (i=; i<n; i++) { for (k=; k<n; k++) { for (j=; j<n; j++) { 5 for (j=; j<n; j++) { for (i=; i<n; i++) { for (k=; k<n; k++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; Cycles/iteration kji jki kij ikj jik ijk Array size (n) 34 Improing temporal locality by blocking Example: Blocked matrix multiplication block (in this context) does not mean. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 A A2 B B2 C C2 X = A2 A22 B2 B22 C2 C22 Key idea: Sub-blocks (i.e., A xy ) can be treated just like scalars. C = A B + A 2 B 2 C 2 = A B 2 + A 2 B 22 C 2 = A 2 B + A 22 B 2 C 22 = A 2 B 2 + A 22 B 22 Blocked matrix multiply (bijk) for (jj=; jj<n; jj+=bsize) { for (i=; i<n; i++) for (j=jj; j < min(jj+bsize,n); j++) c[i][j] =.; for (kk=; kk<n; kk+=bsize) { for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; c[i][j] += sum; 35 36

10 Blocked matrix multiply analysis Innermost loop pair multiplies a X bsize slier of A by a bsize X bsize block of B and accumulates into X bsize slier of C Loop oer i steps through n row sliers of A & C, using same B for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; Innermost c[i][j] += sum; Loop Pair kk jj jj i row slier accessed bsize times block reused n times in succession 37 kk i Update successie elements of slier Pentium blocked matrix multiply performance Blocking (bijk and bikj) improes performance by a factor of two oer unblocked ersions (ijk and jik) Cycles/iteration relatiely insensitie to array size Array size (n) kji jki kij ikj jik ijk bijk (bsize = 25) bikj (bsize = 25) Concluding obserations Programmer can optimize for cache performance How data structures are organized How data accessed Nested loop structure Blocking (see text) is a general technique All machines like cache friendly code Getting absolute optimum performance ery platform specific Cache sizes, line sizes, associatiities, etc. Can get most of the adane with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality) 39

Cache Memories. Cache Memories Oct. 10, Inserting an L1 Cache Between the CPU and Main Memory. General Org of a Cache Memory

Cache Memories. Cache Memories Oct. 10, Inserting an L1 Cache Between the CPU and Main Memory. General Org of a Cache Memory 5-23 The course that gies CMU its Zip! Topics Cache Memories Oct., 22! Generic cache memory organization! Direct mapped caches! Set associatie caches! Impact of caches on performance Cache Memories Cache

More information

ν Hold frequently accessed blocks of main memory 2 CISC 360, Fa09 Cache is an array of sets. Each set contains one or more lines.

ν Hold frequently accessed blocks of main memory 2 CISC 360, Fa09 Cache is an array of sets. Each set contains one or more lines. Topics CISC 36 Cache Memories Dec, 29 ν Generic cache memory organization ν Direct mapped caches ν Set associatie caches ν Impact of caches on performance Cache Memories Cache memories are small, fast

More information

CISC 360. Cache Memories Nov 25, 2008

CISC 360. Cache Memories Nov 25, 2008 CISC 36 Topics Cache Memories Nov 25, 28 Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance Cache Memories Cache memories are small, fast SRAM-based

More information

Giving credit where credit is due

Giving credit where credit is due CSCE 23J Computer Organization Cache Memories Dr. Steve Goddard goddard@cse.unl.edu http://cse.unl.edu/~goddard/courses/csce23j Giving credit where credit is due Most of slides for this lecture are based

More information

Cache Memories. EL2010 Organisasi dan Arsitektur Sistem Komputer Sekolah Teknik Elektro dan Informatika ITB 2010

Cache Memories. EL2010 Organisasi dan Arsitektur Sistem Komputer Sekolah Teknik Elektro dan Informatika ITB 2010 Cache Memories EL21 Organisasi dan Arsitektur Sistem Komputer Sekolah Teknik Elektro dan Informatika ITB 21 Topics Generic cache memory organization Direct mapped caches Set associative caches Impact of

More information

Cache Memories October 8, 2007

Cache Memories October 8, 2007 15-213 Topics Cache Memories October 8, 27 Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance The memory mountain class12.ppt Cache Memories Cache

More information

Systems I. Optimizing for the Memory Hierarchy. Topics Impact of caches on performance Memory hierarchy considerations

Systems I. Optimizing for the Memory Hierarchy. Topics Impact of caches on performance Memory hierarchy considerations Systems I Optimizing for the Memory Hierarchy Topics Impact of caches on performance Memory hierarchy considerations Cache Performance Metrics Miss Rate Fraction of memory references not found in cache

More information

Memory Hierarchy. Announcement. Computer system model. Reference

Memory Hierarchy. Announcement. Computer system model. Reference Announcement Memory Hierarchy Computer Organization and Assembly Languages Yung-Yu Chuang 26//5 Grade for hw#4 is online Please DO submit homework if you haen t Please sign up a demo time on /6 or /7 at

More information

Cache Memories. Topics. Next time. Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance

Cache Memories. Topics. Next time. Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance Cache Memories Topics Generic cache memory organization Direct mapped caches Set associative caches Impact of caches on performance Next time Dynamic memory allocation and memory bugs Fabián E. Bustamante,

More information

The course that gives CMU its Zip! Memory System Performance. March 22, 2001

The course that gives CMU its Zip! Memory System Performance. March 22, 2001 15-213 The course that gives CMU its Zip! Memory System Performance March 22, 2001 Topics Impact of cache parameters Impact of memory reference patterns memory mountain range matrix multiply Basic Cache

More information

Last class. Caches. Direct mapped

Last class. Caches. Direct mapped Memory Hierarchy II Last class Caches Direct mapped E=1 (One cache line per set) Each main memory address can be placed in exactly one place in the cache Conflict misses if two addresses map to same place

More information

211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 211: Computer Architecture Summer 2016 Liu Liu Topic: Assembly Programming Storage - Assembly Programming: Recap - Call-chain - Factorial - Storage: - RAM - Caching - Direct - Mapping Rutgers University

More information

Cache memories are small, fast SRAM based memories managed automatically in hardware.

Cache memories are small, fast SRAM based memories managed automatically in hardware. Cache Memories Cache memories are small, fast SRAM based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in caches (e.g., L1, L2, and

More information

Today Cache memory organization and operation Performance impact of caches

Today Cache memory organization and operation Performance impact of caches Cache Memories 1 Today Cache memory organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal locality

More information

Example. How are these parameters decided?

Example. How are these parameters decided? Example How are these parameters decided? Comparing cache organizations Like many architectural features, caches are evaluated experimentally. As always, performance depends on the actual instruction mix,

More information

Agenda Cache memory organization and operation Chapter 6 Performance impact of caches Cache Memories

Agenda Cache memory organization and operation Chapter 6 Performance impact of caches Cache Memories Agenda Chapter 6 Cache Memories Cache memory organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal

More information

Denison University. Cache Memories. CS-281: Introduction to Computer Systems. Instructor: Thomas C. Bressoud

Denison University. Cache Memories. CS-281: Introduction to Computer Systems. Instructor: Thomas C. Bressoud Cache Memories CS-281: Introduction to Computer Systems Instructor: Thomas C. Bressoud 1 Random-Access Memory (RAM) Key features RAM is traditionally packaged as a chip. Basic storage unit is normally

More information

Computer Organization: A Programmer's Perspective

Computer Organization: A Programmer's Perspective Computer Architecture and The Memory Hierarchy Oren Kapah orenkapah.ac@gmail.com Typical Computer Architecture CPU chip PC (Program Counter) register file AL U Main Components CPU Main Memory Input/Output

More information

Today. Cache Memories. General Cache Concept. General Cache Organization (S, E, B) Cache Memories. Example Memory Hierarchy Smaller, faster,

Today. Cache Memories. General Cache Concept. General Cache Organization (S, E, B) Cache Memories. Example Memory Hierarchy Smaller, faster, Today Cache Memories CSci 2021: Machine Architecture and Organization November 7th-9th, 2016 Your instructor: Stephen McCamant Cache memory organization and operation Performance impact of caches The memory

More information

Carnegie Mellon. Cache Memories. Computer Architecture. Instructor: Norbert Lu1enberger. based on the book by Randy Bryant and Dave O Hallaron

Carnegie Mellon. Cache Memories. Computer Architecture. Instructor: Norbert Lu1enberger. based on the book by Randy Bryant and Dave O Hallaron Cache Memories Computer Architecture Instructor: Norbert Lu1enberger based on the book by Randy Bryant and Dave O Hallaron 1 Today Cache memory organiza7on and opera7on Performance impact of caches The

More information

Memory Hierarchy. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University

Memory Hierarchy. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University Memory Hierarchy Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Time (ns) The CPU-Memory Gap The gap widens between DRAM, disk, and CPU speeds

More information

Cache Memories /18-213/15-513: Introduction to Computer Systems 12 th Lecture, October 5, Today s Instructor: Phil Gibbons

Cache Memories /18-213/15-513: Introduction to Computer Systems 12 th Lecture, October 5, Today s Instructor: Phil Gibbons Cache Memories 15-213/18-213/15-513: Introduction to Computer Systems 12 th Lecture, October 5, 2017 Today s Instructor: Phil Gibbons 1 Today Cache memory organization and operation Performance impact

More information

Memory Hierarchy. Computer Systems Organization (Spring 2017) CSCI-UA 201, Section 3. Instructor: Joanna Klukowska

Memory Hierarchy. Computer Systems Organization (Spring 2017) CSCI-UA 201, Section 3. Instructor: Joanna Klukowska Memory Hierarchy Computer Systems Organization (Spring 2017) CSCI-UA 201, Section 3 Instructor: Joanna Klukowska Slides adapted from Randal E. Bryant and David R. O Hallaron (CMU) Mohamed Zahran (NYU)

More information

CS 33. Caches. CS33 Intro to Computer Systems XVIII 1 Copyright 2017 Thomas W. Doeppner. All rights reserved.

CS 33. Caches. CS33 Intro to Computer Systems XVIII 1 Copyright 2017 Thomas W. Doeppner. All rights reserved. CS 33 Caches CS33 Intro to Computer Systems XVIII 1 Copyright 2017 Thomas W. Doeppner. All rights reserved. Cache Performance Metrics Miss rate fraction of memory references not found in cache (misses

More information

Memory Hierarchy. Cache Memory Organization and Access. General Cache Concept. Example Memory Hierarchy Smaller, faster,

Memory Hierarchy. Cache Memory Organization and Access. General Cache Concept. Example Memory Hierarchy Smaller, faster, Memory Hierarchy Computer Systems Organization (Spring 2017) CSCI-UA 201, Section 3 Cache Memory Organization and Access Instructor: Joanna Klukowska Slides adapted from Randal E. Bryant and David R. O

More information

Carnegie Mellon. Cache Memories

Carnegie Mellon. Cache Memories Cache Memories Thanks to Randal E. Bryant and David R. O Hallaron from CMU Reading Assignment: Computer Systems: A Programmer s Perspec4ve, Third Edi4on, Chapter 6 1 Today Cache memory organiza7on and

More information

High-Performance Parallel Computing

High-Performance Parallel Computing High-Performance Parallel Computing P. (Saday) Sadayappan Rupesh Nasre Course Overview Emphasis on algorithm development and programming issues for high performance No assumed background in computer architecture;

More information

Cache Memories. Andrew Case. Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron

Cache Memories. Andrew Case. Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron Cache Memories Andrew Case Slides adapted from Jinyang Li, Randy Bryant and Dave O Hallaron 1 Topics Cache memory organiza3on and opera3on Performance impact of caches 2 Cache Memories Cache memories are

More information

Cache Memories. From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6.

Cache Memories. From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6. Cache Memories From Bryant and O Hallaron, Computer Systems. A Programmer s Perspective. Chapter 6. Today Cache memory organization and operation Performance impact of caches The memory mountain Rearranging

More information

Cache Memories : Introduc on to Computer Systems 12 th Lecture, October 6th, Instructor: Randy Bryant.

Cache Memories : Introduc on to Computer Systems 12 th Lecture, October 6th, Instructor: Randy Bryant. Cache Memories 15-213: Introduc on to Computer Systems 12 th Lecture, October 6th, 2016 Instructor: Randy Bryant 1 Today Cache memory organiza on and opera on Performance impact of caches The memory mountain

More information

Memory Hierarchy. Instructor: Adam C. Champion, Ph.D. CSE 2431: Introduction to Operating Systems Reading: Chap. 6, [CSAPP]

Memory Hierarchy. Instructor: Adam C. Champion, Ph.D. CSE 2431: Introduction to Operating Systems Reading: Chap. 6, [CSAPP] Memory Hierarchy Instructor: Adam C. Champion, Ph.D. CSE 2431: Introduction to Operating Systems Reading: Chap. 6, [CSAPP] Motivation Up to this point we have relied on a simple model of a computer system

More information

Lecture 12. Memory Design & Caches, part 2. Christos Kozyrakis Stanford University

Lecture 12. Memory Design & Caches, part 2. Christos Kozyrakis Stanford University Lecture 12 Memory Design & Caches, part 2 Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements HW3 is due today PA2 is available on-line today Part 1 is due on 2/27

More information

Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory

Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in caches (e.g., L1, L2, and

More information

CSCI-UA.0201 Computer Systems Organization Memory Hierarchy

CSCI-UA.0201 Computer Systems Organization Memory Hierarchy CSCI-UA.0201 Computer Systems Organization Memory Hierarchy Mohamed Zahran (aka Z) mzahran@cs.nyu.edu http://www.mzahran.com Programmer s Wish List Memory Private Infinitely large Infinitely fast Non-volatile

More information

Cache Memories. Lecture, Oct. 30, Bryant and O Hallaron, Computer Systems: A Programmer s Perspective, Third Edition

Cache Memories. Lecture, Oct. 30, Bryant and O Hallaron, Computer Systems: A Programmer s Perspective, Third Edition Cache Memories Lecture, Oct. 30, 2018 1 General Cache Concept Cache 84 9 14 10 3 Smaller, faster, more expensive memory caches a subset of the blocks 10 4 Data is copied in block-sized transfer units Memory

More information

Chapter 6 Caches. Computer System. Alpha Chip Photo. Topics. Memory Hierarchy Locality of Reference SRAM Caches Direct Mapped Associative

Chapter 6 Caches. Computer System. Alpha Chip Photo. Topics. Memory Hierarchy Locality of Reference SRAM Caches Direct Mapped Associative Chapter 6 s Topics Memory Hierarchy Locality of Reference SRAM s Direct Mapped Associative Computer System Processor interrupt On-chip cache s s Memory-I/O bus bus Net cache Row cache Disk cache Memory

More information

CISC 360. Cache Memories Exercises Dec 3, 2009

CISC 360. Cache Memories Exercises Dec 3, 2009 Topics ν CISC 36 Cache Memories Exercises Dec 3, 29 Review of cache memory mapping Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. ν Hold frequently

More information

Roadmap. Java: Assembly language: OS: Machine code: Computer system:

Roadmap. Java: Assembly language: OS: Machine code: Computer system: Roadmap C: car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c); Assembly language: Machine code: get_mpg: pushq movq... popq ret %rbp %rsp, %rbp %rbp 0111010000011000

More information

Systems Programming and Computer Architecture ( ) Timothy Roscoe

Systems Programming and Computer Architecture ( ) Timothy Roscoe Systems Group Department of Computer Science ETH Zürich Systems Programming and Computer Architecture (252-0061-00) Timothy Roscoe Herbstsemester 2016 AS 2016 Caches 1 16: Caches Computer Architecture

More information

Lecture 15: Caches and Optimization Computer Architecture and Systems Programming ( )

Lecture 15: Caches and Optimization Computer Architecture and Systems Programming ( ) Systems Group Department of Computer Science ETH Zürich Lecture 15: Caches and Optimization Computer Architecture and Systems Programming (252-0061-00) Timothy Roscoe Herbstsemester 2012 Last time Program

More information

CSCI 402: Computer Architectures. Performance of Multilevel Cache

CSCI 402: Computer Architectures. Performance of Multilevel Cache CSCI 402: Computer Architectures Memory Hierarchy (5) Fengguang Song Department of Computer & Information Science IUPUI Performance of Multilevel Cache Main Memory CPU L1 cache L2 cache Given CPU base

More information

EE108B Lecture 13. Caches Wrap Up Processes, Interrupts, and Exceptions. Christos Kozyrakis Stanford University

EE108B Lecture 13. Caches Wrap Up Processes, Interrupts, and Exceptions. Christos Kozyrakis Stanford University EE108B Lecture 13 Caches Wrap Up Processes, Interrupts, and Exceptions Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Lab3 and PA2.1 are due ton 2/27 Don t forget

More information

211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Direct - Mapping - Fully Associated - 2-way Associated - Cache Friendly Code Rutgers University Liu

More information

Locality. CS429: Computer Organization and Architecture. Locality Example 2. Locality Example

Locality. CS429: Computer Organization and Architecture. Locality Example 2. Locality Example Locality CS429: Computer Organization and Architecture Dr Bill Young Department of Computer Sciences University of Texas at Austin Principle of Locality: Programs tend to reuse data and instructions near

More information

Announcements. EE108B Lecture 13. Caches Wrap Up Processes, Interrupts, and Exceptions. Measuring Performance. Memory Performance

Announcements. EE108B Lecture 13. Caches Wrap Up Processes, Interrupts, and Exceptions. Measuring Performance. Memory Performance Announcements EE18B Lecture 13 Caches Wrap Up Processes, Interrupts, and Exceptions Lab3 and PA2.1 are due ton 2/27 Don t forget to study the textbook Don t forget the review sessions Christos Kozyrakis

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: April 5, 2018 at 13:55 CS429 Slideset 19: 1 Cache Vocabulary Much

More information

Lecture 17: Memory Hierarchy and Cache Coherence Concurrent and Mul7core Programming

Lecture 17: Memory Hierarchy and Cache Coherence Concurrent and Mul7core Programming Lecture 17: Memory Hierarchy and Cache Coherence Concurrent and Mul7core Programming Department of Computer Science and Engineering Yonghong Yan yan@oakland.edu www.secs.oakland.edu/~yan 1 Parallelism

More information

Cache Performance II 1

Cache Performance II 1 Cache Performance II 1 cache operation (associative) 111001 index offset valid tag valid tag data data 1 10 1 00 00 11 AA BB tag 1 11 1 01 B4 B5 33 44 = data (B5) AND = AND OR is hit? (1) 2 cache operation

More information

CS3350B Computer Architecture

CS3350B Computer Architecture CS3350B Computer Architecture Winter 2015 Lecture 3.1: Memory Hierarchy: What and Why? Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design, Patterson

More information

CS 240 Stage 3 Abstractions for Practical Systems

CS 240 Stage 3 Abstractions for Practical Systems CS 240 Stage 3 Abstractions for Practical Systems Caching and the memory hierarchy Operating systems and the process model Virtual memory Dynamic memory allocation Victory lap Memory Hierarchy: Cache Memory

More information

Problem: Processor- Memory Bo<leneck

Problem: Processor- Memory Bo<leneck Storage Hierarchy Instructor: Sanjeev Se(a 1 Problem: Processor- Bo

More information

Memory hierarchies: caches and their impact on the running time

Memory hierarchies: caches and their impact on the running time Memory hierarchies: caches and their impact on the running time Irene Finocchi Dept. of Computer and Science Sapienza University of Rome A happy coincidence A fundamental property of hardware Different

More information

Problem: Processor Memory BoJleneck

Problem: Processor Memory BoJleneck Today Memory hierarchy, caches, locality Cache organiza:on Program op:miza:ons that consider caches CSE351 Inaugural Edi:on Spring 2010 1 Problem: Processor Memory BoJleneck Processor performance doubled

More information

Computer Organization - Overview

Computer Organization - Overview Computer Organization - Overview Hyunyoung Lee CSCE 312 1 Course Overview Topics: Theme Five great realities of computer systems Computer system overview Summary NOTE: Most slides are from the textbook

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Warren Hunt, Jr. and Bill Young Department of Computer Sciences University of Texas at Austin Last updated: August 26, 2014 at 08:54 CS429 Slideset 20: 1 Cache

More information

CS 261 Fall Caching. Mike Lam, Professor. (get it??)

CS 261 Fall Caching. Mike Lam, Professor. (get it??) CS 261 Fall 2017 Mike Lam, Professor Caching (get it??) Topics Caching Cache policies and implementations Performance impact General strategies Caching A cache is a small, fast memory that acts as a buffer

More information

write-through v. write-back write-through v. write-back write-through v. write-back option 1: write-through write 10 to 0xABCD CPU RAM Cache ABCD: FF

write-through v. write-back write-through v. write-back write-through v. write-back option 1: write-through write 10 to 0xABCD CPU RAM Cache ABCD: FF write-through v. write-back option 1: write-through 1 write 10 to 0xABCD CPU Cache ABCD: FF RAM 11CD: 42 ABCD: FF 1 2 write-through v. write-back option 1: write-through write-through v. write-back option

More information

Measurement tools and techniques

Measurement tools and techniques Measuring Performance Measurement tools and techniques Fundamental strategies Interval timers & cycle counters Program profiling Tracing Indirect measurement 2 1 Events Most measurement tools based on

More information

How to Write Fast Numerical Code

How to Write Fast Numerical Code How to Write Fast Numerical Code Lecture: Memory hierarchy, locality, caches Instructor: Markus Püschel TA: Daniele Spampinato & Alen Stojanov Left alignment Attractive font (sans serif, avoid Arial) Calibri,

More information

Introduction to Computer Systems

Introduction to Computer Systems CSCE 230J Computer Organization Introduction to Computer Systems Dr. Steve Goddard goddard@cse.unl.edu http://cse.unl.edu/~goddard/courses/csce230j Giving credit where credit is due Most of slides for

More information

Introduction to Computer Systems

Introduction to Computer Systems CSCE 230J Computer Organization Introduction to Computer Systems Dr. Steve Goddard goddard@cse.unl.edu Giving credit where credit is due Most of slides for this lecture are based on slides created by Drs.

More information

Advanced Caching Techniques

Advanced Caching Techniques Advanced Caching Approaches to improving memory system performance eliminate memory operations decrease the number of misses decrease the miss penalty decrease the cache/memory access times hide memory

More information

Caches Concepts Review

Caches Concepts Review Caches Concepts Review What is a block address? Why not bring just what is needed by the processor? What is a set associative cache? Write-through? Write-back? Then we ll see: Block allocation policy on

More information

How to Write Fast Numerical Code

How to Write Fast Numerical Code How to Write Fast Numerical Code Lecture: Memory hierarchy, locality, caches Instructor: Markus Püschel TA: Alen Stojanov, Georg Ofenbeck, Gagandeep Singh Organization Temporal and spatial locality Memory

More information

CS356: Discussion #9 Memory Hierarchy and Caches. Marco Paolieri Illustrations from CS:APP3e textbook

CS356: Discussion #9 Memory Hierarchy and Caches. Marco Paolieri Illustrations from CS:APP3e textbook CS356: Discussion #9 Memory Hierarchy and Caches Marco Paolieri (paolieri@usc.edu) Illustrations from CS:APP3e textbook The Memory Hierarchy So far... We modeled the memory system as an abstract array

More information

+ Random-Access Memory (RAM)

+ Random-Access Memory (RAM) + Memory Subsystem + Random-Access Memory (RAM) Key features RAM is traditionally packaged as a chip. Basic storage unit is normally a cell (one bit per cell). Multiple RAM chips form a memory. RAM comes

More information

Advanced Caching Techniques

Advanced Caching Techniques Advanced Caching Approaches to improving memory system performance eliminate memory accesses/operations decrease the number of misses decrease the miss penalty decrease the cache/memory access times hide

More information

Computer Systems. Memory Hierarchy. Han, Hwansoo

Computer Systems. Memory Hierarchy. Han, Hwansoo Computer Systems Memory Hierarchy Han, Hwansoo Random-Access Memory (RAM) Key features RAM is traditionally packaged as a chip. Basic storage unit is normally a cell (one bit per cell). Multiple RAM chips

More information

Memory Hierarchy & Caching. CS 351: Systems Programming Michael Saelee

Memory Hierarchy & Caching. CS 351: Systems Programming Michael Saelee Memory Hierarchy & Caching CS 351: Systems Programming Michael Saelee Motivation CPU instr data results Memory I/O again, recall the Von Neumann architecture a stored-program computer with

More information

SE-292 High Performance Computing. Memory Hierarchy. R. Govindarajan Memory Hierarchy

SE-292 High Performance Computing. Memory Hierarchy. R. Govindarajan Memory Hierarchy SE-292 High Performance Computing Memory Hierarchy R. Govindarajan govind@serc Memory Hierarchy 2 1 Memory Organization Memory hierarchy CPU registers few in number (typically 16/32/128) subcycle access

More information

Memories. CPE480/CS480/EE480, Spring Hank Dietz.

Memories. CPE480/CS480/EE480, Spring Hank Dietz. Memories CPE480/CS480/EE480, Spring 2018 Hank Dietz http://aggregate.org/ee480 What we want, what we have What we want: Unlimited memory space Fast, constant, access time (UMA: Uniform Memory Access) What

More information

Caches Spring 2016 May 4: Caches 1

Caches Spring 2016 May 4: Caches 1 May 4: Caches 1 Roadmap C: car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c); Assembly language: Machine code: Computer system: get_mpg: pushq movq... popq ret

More information

Copyright 2012, Elsevier Inc. All rights reserved.

Copyright 2012, Elsevier Inc. All rights reserved. Computer Architecture A Quantitative Approach, Fifth Edition Chapter 2 Memory Hierarchy Design 1 Introduction Programmers want unlimited amounts of memory with low latency Fast memory technology is more

More information

CS377P Programming for Performance Single Thread Performance Caches I

CS377P Programming for Performance Single Thread Performance Caches I CS377P Programming for Performance Single Thread Performance Caches I Sreepathi Pai UTCS September 21, 2015 Outline 1 Introduction 2 Caches 3 Performance of Caches Outline 1 Introduction 2 Caches 3 Performance

More information

L2 cache provides additional on-chip caching space. L2 cache captures misses from L1 cache. Summary

L2 cache provides additional on-chip caching space. L2 cache captures misses from L1 cache. Summary HY425 Lecture 13: Improving Cache Performance Dimitrios S. Nikolopoulos University of Crete and FORTH-ICS November 25, 2011 Dimitrios S. Nikolopoulos HY425 Lecture 13: Improving Cache Performance 1 / 40

More information

Computer Architecture and System Software Lecture 09: Memory Hierarchy. Instructor: Rob Bergen Applied Computer Science University of Winnipeg

Computer Architecture and System Software Lecture 09: Memory Hierarchy. Instructor: Rob Bergen Applied Computer Science University of Winnipeg Computer Architecture and System Software Lecture 09: Memory Hierarchy Instructor: Rob Bergen Applied Computer Science University of Winnipeg Announcements Midterm returned + solutions in class today SSD

More information

Random-Access Memory (RAM) CISC 360. The Memory Hierarchy Nov 24, Conventional DRAM Organization. SRAM vs DRAM Summary.

Random-Access Memory (RAM) CISC 360. The Memory Hierarchy Nov 24, Conventional DRAM Organization. SRAM vs DRAM Summary. CISC 36 Random-ccess Memory (RM) The Memory Hierarchy Nov 24, 29 class12.ppt 2 CISC 36 Fa9 SRM vs DRM Summary Conventional DRM Organization Tran. ccess per bit time Persist?Sensitive? Cost pplications

More information

CS241 Computer Organization Spring Principle of Locality

CS241 Computer Organization Spring Principle of Locality CS241 Computer Organization Spring 2015 Principle of Locality 4-21 2015 Outline! Optimization! Memory Hierarchy Locality temporal spatial Cache Readings: CSAPP2: Chapter 5, sections 5.1-5.6; 5.13 CSAPP2:

More information

Cache Memories. Lecture 14 Cache Memories. Inserting an L1 Cache Between the CPU and Main Memory. General Org of a Cache Memory

Cache Memories. Lecture 14 Cache Memories. Inserting an L1 Cache Between the CPU and Main Memory. General Org of a Cache Memory Topcs Lecture 4 Cache Memores Generc cache memory organzaton Drect mapped caches Set assocate caches Impact of caches on performance Cache Memores Cache memores are small, fast SRAM-based memores managed

More information

Advanced Architecture

Advanced Architecture Advanced Architecture Computer Organization and Assembly Languages g Yung-Yu Chuang with slides by S. Dandamudi, Peng-Sheng Chen, Kip Irvine, Robert Sedgwick and Kevin Wayne Basic architecture Basic microcomputer

More information

Lecture 2. Memory locality optimizations Address space organization

Lecture 2. Memory locality optimizations Address space organization Lecture 2 Memory locality optimizations Address space organization Announcements Office hours in EBU3B Room 3244 Mondays 3.00 to 4.00pm; Thurs 2:00pm-3:30pm Partners XSED Portal accounts Log in to Lilliput

More information

A Crash Course in Compilers for Parallel Computing. Mary Hall Fall, L2: Transforms, Reuse, Locality

A Crash Course in Compilers for Parallel Computing. Mary Hall Fall, L2: Transforms, Reuse, Locality A Crash Course in Compilers for Parallel Computing Mary Hall Fall, 2008 1 Overview of Crash Course L1: Data Dependence Analysis and Parallelization (Oct. 30) L2 & L3: Loop Reordering Transformations, Reuse

More information

Advanced Memory Organizations

Advanced Memory Organizations CSE 3421: Introduction to Computer Architecture Advanced Memory Organizations Study: 5.1, 5.2, 5.3, 5.4 (only parts) Gojko Babić 03-29-2018 1 Growth in Performance of DRAM & CPU Huge mismatch between CPU

More information

Donn Morrison Department of Computer Science. TDT4255 Memory hierarchies

Donn Morrison Department of Computer Science. TDT4255 Memory hierarchies TDT4255 Lecture 10: Memory hierarchies Donn Morrison Department of Computer Science 2 Outline Chapter 5 - Memory hierarchies (5.1-5.5) Temporal and spacial locality Hits and misses Direct-mapped, set associative,

More information

Memory Hierarchy. Reading. Sections 5.1, 5.2, 5.3, 5.4, 5.8 (some elements), 5.9 (2) Lecture notes from MKP, H. H. Lee and S.

Memory Hierarchy. Reading. Sections 5.1, 5.2, 5.3, 5.4, 5.8 (some elements), 5.9 (2) Lecture notes from MKP, H. H. Lee and S. Memory Hierarchy Lecture notes from MKP, H. H. Lee and S. Yalamanchili Sections 5.1, 5.2, 5.3, 5.4, 5.8 (some elements), 5.9 Reading (2) 1 SRAM: Value is stored on a pair of inerting gates Very fast but

More information

CS3350B Computer Architecture

CS3350B Computer Architecture CS335B Computer Architecture Winter 25 Lecture 32: Exploiting Memory Hierarchy: How? Marc Moreno Maza wwwcsduwoca/courses/cs335b [Adapted from lectures on Computer Organization and Design, Patterson &

More information

CS 33. Architecture and Optimization (3) CS33 Intro to Computer Systems XVI 1 Copyright 2018 Thomas W. Doeppner. All rights reserved.

CS 33. Architecture and Optimization (3) CS33 Intro to Computer Systems XVI 1 Copyright 2018 Thomas W. Doeppner. All rights reserved. CS 33 Architecture and Optimization (3) CS33 Intro to Computer Systems XVI 1 Copyright 2018 Thomas W. Doeppner. All rights reserved. Hyper Threading Instruction Control Instruction Control Retirement Unit

More information

Cache Memory and Performance

Cache Memory and Performance Cache Memory and Performance Cache Performance 1 Many of the following slides are taken with permission from Complete Powerpoint Lecture Notes for Computer Systems: A Programmer's Perspective (CS:APP)

More information

Princeton University. Computer Science 217: Introduction to Programming Systems. The Memory/Storage Hierarchy and Virtual Memory

Princeton University. Computer Science 217: Introduction to Programming Systems. The Memory/Storage Hierarchy and Virtual Memory Princeton University Computer Science 27: Introduction to Programming Systems The Memory/Storage Hierarchy and Virtual Memory Goals of this Lecture Help you learn about: Locality and caching The memory

More information

CSF Cache Introduction. [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005]

CSF Cache Introduction. [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005] CSF Cache Introduction [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005] Review: The Memory Hierarchy Take advantage of the principle of locality to present the user with as much

More information

F28HS Hardware-Software Interface: Systems Programming

F28HS Hardware-Software Interface: Systems Programming F28HS Hardware-Software Interface: Systems Programming Hans-Wolfgang Loidl School of Mathematical and Computer Sciences, Heriot-Watt University, Edinburgh Semester 2 2016/17 0 No proprietary software has

More information

CS24: INTRODUCTION TO COMPUTING SYSTEMS. Spring 2014 Lecture 14

CS24: INTRODUCTION TO COMPUTING SYSTEMS. Spring 2014 Lecture 14 CS24: INTRODUCTION TO COMPUTING SYSTEMS Spring 2014 Lecture 14 LAST TIME! Examined several memory technologies: SRAM volatile memory cells built from transistors! Fast to use, larger memory cells (6+ transistors

More information

CS/ECE 250 Computer Architecture

CS/ECE 250 Computer Architecture Computer Architecture Caches and Memory Hierarchies Benjamin Lee Duke University Some slides derived from work by Amir Roth (Penn), Alvin Lebeck (Duke), Dan Sorin (Duke) 2013 Alvin R. Lebeck from Roth

More information

Caches III. CSE 351 Spring Instructor: Ruth Anderson

Caches III. CSE 351 Spring Instructor: Ruth Anderson Caches III CSE 351 Spring 2017 Instructor: Ruth Anderson Teaching Assistants: Dylan Johnson Kevin Bi Linxing Preston Jiang Cody Ohlsen Yufang Sun Joshua Curtis Administrivia Office Hours Changes check

More information

Key Point. What are Cache lines

Key Point. What are Cache lines Caching 1 Key Point What are Cache lines Tags Index offset How do we find data in the cache? How do we tell if it s the right data? What decisions do we need to make in designing a cache? What are possible

More information

Memory Hierarchy. ENG3380 Computer Organization and Architecture Cache Memory Part II. Topics. References. Memory Hierarchy

Memory Hierarchy. ENG3380 Computer Organization and Architecture Cache Memory Part II. Topics. References. Memory Hierarchy ENG338 Computer Organization and Architecture Part II Winter 217 S. Areibi School of Engineering University of Guelph Hierarchy Topics Hierarchy Locality Motivation Principles Elements of Design: Addresses

More information

CS 61C: Great Ideas in Computer Architecture. Direct Mapped Caches

CS 61C: Great Ideas in Computer Architecture. Direct Mapped Caches CS 61C: Great Ideas in Computer Architecture Direct Mapped Caches Instructor: Justin Hsia 7/05/2012 Summer 2012 Lecture #11 1 Review of Last Lecture Floating point (single and double precision) approximates

More information

Caches. Han Wang CS 3410, Spring 2012 Computer Science Cornell University. See P&H 5.1, 5.2 (except writes)

Caches. Han Wang CS 3410, Spring 2012 Computer Science Cornell University. See P&H 5.1, 5.2 (except writes) Caches Han Wang CS 3410, Spring 2012 Computer Science Cornell University See P&H 5.1, 5.2 (except writes) This week: Announcements PA2 Work-in-progress submission Next six weeks: Two labs and two projects

More information

CS 201 The Memory Hierarchy. Gerson Robboy Portland State University

CS 201 The Memory Hierarchy. Gerson Robboy Portland State University CS 201 The Memory Hierarchy Gerson Robboy Portland State University memory hierarchy overview (traditional) CPU registers main memory (RAM) secondary memory (DISK) why? what is different between these

More information

Textbook: Burdea and Coiffet, Virtual Reality Technology, 2 nd Edition, Wiley, Textbook web site:

Textbook: Burdea and Coiffet, Virtual Reality Technology, 2 nd Edition, Wiley, Textbook web site: Textbook: Burdea and Coiffet, Virtual Reality Technology, 2 nd Edition, Wiley, 2003 Textbook web site: www.vrtechnology.org 1 Textbook web site: www.vrtechnology.org Laboratory Hardware 2 Topics 14:332:331

More information