CS 406/534 Compiler Construction Instruction Selection and Global Register Allocation

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1 CS 406/534 Compiler Construction Instruction Selection and Global Register Allocation Prof. Li Xu Dept. of Computer Science UMass Lowell Fall 2004 Part of the course lecture notes are based on Prof. Keith Cooper, Prof. Ken Kennedy and Dr. Linda Torczon s teaching materials at Rice University. All rights reserved. 1

2 What We Did Last Time Instruction Scheduling beyond basic blocks Code shape and code generation CS406/534 Fall 2004, Prof. Li Xu 2 2

3 Today s Goals Continue our tour of the back-end Automated instruction selection through pattern matching Peephole matching Tree pattern matching Global register allocation CS406/534 Fall 2004, Prof. Li Xu 3 3

4 The Problem Modern computers (still) have many ways to do things Consider register-to-register copy in ILOC Obvious operation is i2ir i r j Many others exist addi r i,0 r j multir i,1 r j ori r i,0 r j subir i,0 r j divi r i,1 r j xorir i,0 r j lshiftir i,0 r j rshiftir i,0 r j and others Human would ignore all of these Algorithm must look at all of them & find low-cost encoding Take context into account (busy functional unit?) CS406/534 Fall 2004, Prof. Li Xu 4 4

5 The Goal Want to automate generation of instruction selectors: retargetable compilers Front End Middle End Back End Infrastructure Machine description Back-end Generator Tables Pattern Matching Engine Description-based retargeting Machine description should also help with scheduling & allocation CS406/534 Fall 2004, Prof. Li Xu 5 5

6 Automated Pattern Matching Tree-oriented IR suggests pattern matching on trees Tree-patterns as input, matcher as output Each pattern maps to a target-machine instruction sequence Use dynamic programming or bottom-up rewrite systems Linear IR suggests using some sort of string matching Strings as input, matcher as output Each string maps to a target-machine instruction sequence Peephole matching CS406/534 Fall 2004, Prof. Li Xu 6 6

7 Basic idea Peephole Matching Compiler can discover local improvements locally Look at a small set of adjacent operations Move a peephole over code & search for improvement Store followed by load Original code Improved code storeai r 1 r 0,8 storeai r 1 r 0,8 loadai r 0,8 r 15 i2i r 1 r 15 CS406/534 Fall 2004, Prof. Li Xu 7 7

8 Basic idea Peephole Matching Compiler can discover local improvements locally Look at a small set of adjacent operations Move a peephole over code & search for improvement Store followed by load Simple algebraic identities Original code Improved code addi r 2,0 r 7 mult r 4,r 7 r 10 mult r 4,r 2 r 10 CS406/534 Fall 2004, Prof. Li Xu 8 8

9 Basic idea Peephole Matching Compiler can discover local improvements locally Look at a small set of adjacent operations Move a peephole over code & search for improvement Store followed by load Simple algebraic identities Jump to a jump Original code Improved code jumpi L 10 L 10 : jumpi L 11 L 10 : jumpi L 11 CS406/534 Fall 2004, Prof. Li Xu 9 9

10 Implementing it Peephole Matching Early systems used limited set of hand-coded patterns Window size ensured quick processing Modern peephole instruction selectors Break problem into three tasks (Davidson) IR Expander LLIR Simplifier LLIR Matcher ASM IR LLIR LLIR LLIR LLIR ASM Apply symbolic interpretation & simplification systematically CS406/534 Fall 2004, Prof. Li Xu 10 10

11 Expander Peephole Matching Turns IR code into a low-level IR (LLIR) such as RTL Operation-by-operation, template-driven rewriting LLIR form includes all direct effects (e.g., setting cc) Significant, albeit constant, expansion of size IR Expander LLIR Simplifier LLIR Matcher ASM IR LLIR LLIR LLIR LLIR ASM CS406/534 Fall 2004, Prof. Li Xu 11 11

12 Simplifier Peephole Matching Looks at LLIR through window and rewrites Uses forward substitution, algebraic simplification, local constant propagation, and dead-effect elimination Performs local optimization within window IR Expander LLIR Simplifier LLIR Matcher ASM IR LLIR LLIR LLIR LLIR ASM This is the heart of the peephole system Benefit of peephole optimization shows up in this step CS406/534 Fall 2004, Prof. Li Xu 12 12

13 Matcher Peephole Matching Compares simplified LLIR against a library of patterns Picks low-cost pattern that captures effects Must preserve LLIR effects, may add new ones (e.g., set cc) Generates the assembly code output IR Expander LLIR Simplifier LLIR Matcher ASM IR LLIR LLIR LLIR LLIR ASM CS406/534 Fall 2004, Prof. Li Xu 13 13

14 Example Original IR Code OP Arg 1 Arg 2 Result mult 2 y sub x t 1 t 1 w Expand LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 CS406/534 Fall 2004, Prof. Li Xu 14 14

15 Example LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 Simplify MEM(r 0 r 18 LLIR Code r 13 MEM(r 0 r 14 2 x r 13 r 17 MEM(r 0 r 18 r 17 -r 14 CS406/534 Fall 2004, Prof. Li Xu 15 15

16 Example MEM(r 0 r 18 LLIR Code r 13 MEM(r 0 r 14 2 x r 13 r 17 MEM(r 0 r 18 r 17 -r 14 Match ILOC Code loadai r 0,@y r 13 multi 2 x r 13 r 14 loadai r 0,@x r 17 sub r 17 -r 14 r 18 storeai r 18 r 0,@w Introduced all memory operations & temporary names Turned out pretty good code CS406/534 Fall 2004, Prof. Li Xu 16 16

17 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 r 10 2 r r 12 + r 11 MEM(r 20 ) r 18 CS406/534 Fall 2004, Prof. Li Xu 17 17

18 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 10 2 r r 12 + r 11 r 10 2 r 12 r 13 MEM(r 12 ) CS406/534 Fall 2004, Prof. Li Xu 18 18

19 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 10 2 r 12 r 13 MEM(r 12 ) r 10 2 r 13 MEM(r 0 r 14 r 10 x r 13 CS406/534 Fall 2004, Prof. Li Xu 19 19

20 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 10 2 r 13 MEM(r 0 r 14 r 10 x r 13 r 13 MEM(r 0 r 14 2 x r 13 r CS406/534 Fall 2004, Prof. Li Xu 20 20

21 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 r 13 MEM(r 0 r 14 2 x r 13 r 1 st op it has rolled out of window r 14 2 x r 13 r r 16 + r 15 MEM(r 20 ) r 18 CS406/534 Fall 2004, Prof. Li Xu 21 21

22 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 14 2 x r 13 r r 16 + r 15 r 14 2 x r 13 r 16 r 17 MEM(r 16 ) CS406/534 Fall 2004, Prof. Li Xu 22 22

23 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 14 2 x r 13 r 16 r 17 MEM(r 16 ) r 14 2 x r 13 r 17 MEM(r 0 +@x) r 18 r 17 -r 14 CS406/534 Fall 2004, Prof. Li Xu 23 23

24 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 14 2 x r 13 r 17 MEM(r 0 +@x) r 18 r 17 -r 14 r 17 MEM(r 0 +@x) r 18 r 17 -r 14 r CS406/534 Fall 2004, Prof. Li Xu 24 24

25 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 17 MEM(r 0 +@x) r 18 r 17 -r 14 r r 18 r 17 -r 14 r r 20 + r 19 CS406/534 Fall 2004, Prof. Li Xu 25 25

26 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 18 r 17 -r 14 r r 20 + r 19 r 18 r 17 -r 14 r 20 MEM(r 20 ) r 18 CS406/534 Fall 2004, Prof. Li Xu 26 26

27 Steps of the Simplifier (3-op window) LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 r 18 r 17 -r 14 r 20 MEM(r 20 ) r 18 r 18 r 17 -r 14 MEM(r 0 r 18 CS406/534 Fall 2004, Prof. Li Xu 27 27

28 Example LLIR Code r 10 2 r r 12 + r 11 r 13 MEM(r 12 ) r 14 r 10 x r 13 r r 16 + r 15 r 17 MEM(r 16 ) r 18 r 17 -r 14 r r 20 + r 19 MEM(r 20 ) r 18 Simplify MEM(r 0 r 18 LLIR Code r 13 MEM(r 0 r 14 2 x r 13 r 17 MEM(r 0 r 18 r 17 -r 14 CS406/534 Fall 2004, Prof. Li Xu 28 28

29 Details Making It All Work LIR is largely machine independent (RTL) Target machine described as LLIR ASM pattern Actual pattern matching Use a hand-coded pattern matcher (GCC) Turn patterns into grammar & use LR parser (VPO) Several compilers use this technology It seems to produce good portable instruction selectors Key strength appears to be late low-level optimization CS406/534 Fall 2004, Prof. Li Xu 29 29

30 Tree-Pattern Matching Many compilers use tree-structured IRs Abstract syntax trees generated in the parser Trees or DAGs for expressions These systems might well use trees to represent target ISA Match these pattern trees against IR trees CS406/534 Fall 2004, Prof. Li Xu 30 30

31 The Concept Low-level AST for w x - 2 * y + - ARP: r arp NUM: constant LAB: ASM label VAL ARP NUM 4 REF REF NUM 2 * REF w: at ARP+4 x: at ARP-26 Y: + + VAL ARP NUM -26 NUM 12 CS406/534 Fall 2004, Prof. Li Xu 31 31

32 Notation To describe these trees, we need a concise notation + GETS - -(REF(REF(+(VAL 2,NUM 2 ))), *(NUM 3,(REF(+(LAB 1,NUM 3 )))))) VAL ARP NUM 4 REF * *(NUM 3,(REF(+(LAB 1,NUM 3 )))))) (+(VAL 1,NUM 1 ) REF NUM 2 REF (REF(REF(+(VAL 2,NUM 2 ))) + + VAL ARP NUM -26 NUM 12 GETS(+(VAL 1,NUM 1 ), -(REF(REF(+(VAL 2,NUM 2 ))), *(NUM 3,(REF(+(LAB 1,NUM 3 )))))) CS406/534 Fall 2004, Prof. Li Xu 32 32

33 Tree-Pattern Matching Goal is to tile AST with operation trees A tiling is collection of <ast, op > pairs ast is a node in the AST op is an operation tree <ast, op > means that op could implement the subtree at ast A tiling implements an AST if it covers every node in the AST and the overlap between any two trees is limited to a single node <ast, op> tiling means ast is also covered by a leaf in another operation tree in the tiling, unless it is the root Where two operation trees meet, they must be compatible (expect the value in the same location) CS406/534 Fall 2004, Prof. Li Xu 33 33

34 Tiling the Tree VAL ARP + Tile 1 NUM 4 GETS Tile 6 REF REF - Tile 5 * Tile 4 NUM 2 REF Each tile corresponds to a sequence of operations Emitting those operations in an appropriate order implements the tree. VAL ARP + Tile 2 NUM Tile 3 NUM 12 CS406/534 Fall 2004, Prof. Li Xu 34 34

35 Given a tiled tree Tiling the Tree Postorder treewalk, with node-dependent order for children Right child of GETS before its left child Might impose most demanding first rule (Sethi ) Emit code sequence for tiles, in order Tie boundaries together with register names Tile 6 uses registers produced by tiles 1 & 5 Tile 6 emits store r tile 5 r tile 1 Can incorporate a real allocator or can use NextRegister++ CS406/534 Fall 2004, Prof. Li Xu 35 35

36 Tiling the Tree Finding the matches to tile the tree Compiler writer connects operation trees to AST subtrees Provide a set of rewrite rules Encode tree syntax, in linear form Associate each rule with a code template CS406/534 Fall 2004, Prof. Li Xu 36 36

37 Rewrite rules: AST into ILOC Rule Cost Template 1 Goal Assign 0 2 Assign GETS(Reg 1,Reg 2 ) 1 store r 2 r 1 3 Assign GETS(+(Reg 1,Reg 2 ),Reg 3 ) 1 storea O r 3 r 1,r 2 4 Assign GETS(+(Reg 1,NUM 2 ),Reg 3 ) 1 storeai r 3 r 1,n 2 5 Assign GETS(+(NUM 1,Reg 2 ),Reg 3 ) 1 storeai r 3 r 2,n 1 6 Reg LAB 1 1 loadi l 1 r new 7 Reg VAL Reg NUM 1 1 loadi n 1 r new 9 Reg REF(Reg 1 ) 1 load r 1 r new 10 Reg REF(+ (Reg 1,Reg 2 )) 1 loada O r 1,r 2 r new 11 Reg REF(+ (Reg 1,NUM 2 )) 1 loadai r 1,n 2 r new 12 Reg REF(+ (NUM 1,Reg 2 )) 1 loadai r 2,n 1 r new CS406/534 Fall 2004, Prof. Li Xu 37 37

38 Rewrite rules: AST into ILOC Rule Cost Template 13 Reg + (Reg 1,Reg 2 ) 1 add r 1,r 2 r new 14 Reg + (Reg 1,NUM 2 ) 1 addi r 1,n 2 r new 15 Reg + (NUM 1,Reg 2 ) 1 addi r 2,n 1 r new 16 Reg -(Reg 1,Reg 2 ) 1 sub r 1,r 2 r new 17 Reg -(Reg 1,NUM 2 ) 1 subi r 1,n 2 r new 18 Reg -(NUM 1,Reg 2 ) 1 rsubi r 2,n 1 r new 19 Reg x (Reg 1,Reg 2 ) 1 mult r 1,r 2 r new 20 Reg x (Reg 1,NUM 2 ) 1 multir 1,n 2 r new 21 Reg x (NUM 1,Reg 2 ) 1 multir 2,n 1 r new A real set of rules would cover more than signed integers CS406/534 Fall 2004, Prof. Li Xu 38 38

39 Tiling the Tree Need an algorithm to match AST subtrees with the rules Consider tile 3 in our example REF + What rules match tile 3? NUM 12 CS406/534 Fall 2004, Prof. Li Xu 39 39

40 Tiling the Tree Need an algorithm to match AST subtrees with the rules Consider tile 3 in our example REF What rules match tile 3? 6: Reg LAB 1 tiles the lower left node + 6 NUM 12 CS406/534 Fall 2004, Prof. Li Xu 40 40

41 Tiling the Tree Need an algorithm to match AST subtrees with the rules Consider tile 3 in our example REF What rules match tile 3? 6: Reg LAB 1 tiles the lower left node 8: Reg NUM 1 tiles the bottom right node NUM 12 CS406/534 Fall 2004, Prof. Li Xu 41 41

42 Tiling the Tree Need an algorithm to match AST subtrees with the rules Consider tile 3 in our example REF NUM 12 What rules match tile 3? 6: Reg LAB 1 tiles the lower left node 8: Reg NUM 1 tiles the bottom right node 13: Reg + (Reg 1,Reg 2 ) tiles the + node CS406/534 Fall 2004, Prof. Li Xu 42 42

43 Tiling the Tree Need an algorithm to match AST subtrees with the rules Consider tile 3 in our example 9 REF NUM 12 What rules match tile 3? 6: Reg LAB 1 tiles the lower left node 8: Reg NUM 1 tiles the bottom right node 13: Reg + (Reg 1,Reg 2 ) tiles the + node 9: Reg REF(Reg 1 ) tiles the REF CS406/534 Fall 2004, Prof. Li Xu 43 43

44 Tiling the Tree Need an algorithm to match AST subtrees with the rules Consider tile 3 in our example 9 REF NUM 12 What rules match tile 3? 6: Reg LAB 1 tiles the lower left node 8: Reg NUM 1 tiles the bottom right node 13: Reg + (Reg 1,Reg 2 ) tiles the + node 9: Reg REF(Reg 1 ) tiles the REF We denote this match as <6,8,13,9> CS406/534 Fall 2004, Prof. Li Xu 44 44

45 Finding Matches Many Sequences Match Our Subtree Cost Sequences REF 2 3 6,11 6,8,10 8,12 8,6,10 6,14,9 8,15, ,8,13,9 8,6,13,9 NUM 12 In general, we want the low cost sequence Each unit of cost is an operation (1 cycle) We should favor short sequences CS406/534 Fall 2004, Prof. Li Xu 45 45

46 Low Cost Matches Finding Matches REF Sequences with Cost of 2 + NUM 12 6: Reg LAB 1 11: Reg REF(+(Reg 1,NUM 2 )) 8: Reg NUM 1 12: Reg REF(+(NUM 1,Reg 2 )) G r i loadai r i,12 r j loadi 12 r i loadai r i,@g r j These two are equivalent in cost 6,11 might be better, may be longer than the immediate field CS406/534 Fall 2004, Prof. Li Xu 46 46

47 Tiling the Tree Tile(n) Label(n) Ø if n has two children then Tile (left child of n) Tile (right child of n) for each rule r that implements n if (left(r) Label(left(n)) and (right(r) Label(right(n)) then Label(n) Label(n) {r} else if n has one child Tile(child of n) for each rule r that implements n if (left(r) Label(child(n)) then Label(n) Label(n) {r} else /* n is a leaf */ Label(n) {all rules that implement n } Match binary nodes against binary rules Match unary nodes against unary rules Handle leaves with lookup in rule table CS406/534 Fall 2004, Prof. Li Xu 47 47

48 Tiling the Tree Tile(n) Label(n) Ø if n has two children then Tile (left child of n) Tile (right child of n) for each rule r that implements n if (left(r) Label(left(n)) and (right(r) Label(right(n)) then Label(n) Label(n) {r} else if n has one child Tile(child of n) for each rule r that implements n if (left(r) Label(child(n)) then Label(n) Label(n) {r} else /* n is a leaf */ Label(n) {all rules that implement n } This algorithm Finds all matches in rule set Labels node n with that set Can keep lowest cost match at each point Leads to a notion of local optimality lowest cost at each point Spends its time in the two matching loops CS406/534 Fall 2004, Prof. Li Xu 48 48

49 Summary Tree patterns represent AST and ASM Can use matching algorithms to find low-cost tiling of AST Can turn a tiling into code using templates for matched rules Techniques (& tools) exist to do this efficiently CS406/534 Fall 2004, Prof. Li Xu 49 49

50 Global Register Allocation Taking a global approach Abandon the distinction between local & global Make systematic use of registers or memory Adopt a general scheme to approximate a good allocation Graph coloring paradigm (Lavrov & (later) Chaitin ) 1 Build an interference graph G I for the procedure Computing live ranges in the global scope Computing overlap of live ranges (interference) 2 Construct a k-coloring of interference graph Minimal coloring is NP-Complete Spilling and splitting live ranges if necessary 3 Map colors onto physical registers CS406/534 Fall 2004, Prof. Li Xu 50 50

51 Web-based Live Ranges Starting Point: def-use chains (DU chains) Connect definition to all reachable uses Join defs and uses into same web Def and all reachable uses must be in same web All defs that reach same use must be in same web Use a union-find algorithm CS406/534 Fall 2004, Prof. Li Xu 51 51

52 Example l1 def x def y def y def x use y l4 use x use y l3 use x def x l2 use x CS406/534 Fall 2004, Prof. Li Xu 52 52

53 Interference Two liveranges interfere if they overlap (have a nonemtpy intersection) Interference captures the conflicts for storage allocation If two liveranges interfere, values must be stored in different registers or memory locations If two liveranges do not interfere, can store values in same register or memory location CS406/534 Fall 2004, Prof. Li Xu 53 53

54 Example l1 def x def y def y def x use y l4 use x use y l3 l2 use x def x use x l3 l1 l4 l2 CS406/534 Fall 2004, Prof. Li Xu 54 54

55 Graph Coloring (A Background Digression) The problem A graph G is said to be k-colorable iff the nodes can be labeled with integers 1 k so that no edge in G connects two nodes with the same label Examples 2-colorable 3-colorable Each color can be mapped to a distinct physical register CS406/534 Fall 2004, Prof. Li Xu 55 55

56 Interference Graph The interference graph, G I Nodes in G I represent values, or live ranges Edges in G I represent individual interferences For x, y G I, <x,y> iff x and y interfere A k-coloring of G I can be mapped into an allocation to k registers CS406/534 Fall 2004, Prof. Li Xu 56 56

57 Building the Interference Graph To build the interference graph 1 Discover live ranges > Modern compilers use SSA form 2 Compute LIVE sets for each block > Use data flow analysis 3 Iterate over each block > Track the current LIVE set > At each operation, add appropriate edges & update LIVE Edge from result to each value in LIVE Remove result from LIVE Edge from each operand to each value in LIVE CS406/534 Fall 2004, Prof. Li Xu 57 57

58 Observation on Coloring for Register Allocation Suppose we have k registers look for a k coloring Any vertex n that has fewer than k neighbors in the interference graph (n < k) can always be colored! Pick any color not used by its neighbors there must be one CS406/534 Fall 2004, Prof. Li Xu 58 58

59 Chaitin s Algorithm 1. While vertices with < k neighbors in G I > Pick any vertex n such that n < k and put it on the stack > Remove that vertex and all edges incident to it from G I This will lower the degree of n s neighbors 2. If G I is non-empty (all vertices have k or more neighbors) then: > Pick a vertex n (using some heuristic) and spill the live range associated with n > Remove vertex n from G I, along with all edges incident to it and put it on the stack > If this causes some vertex in G I to have fewer than k neighbors, then go to step 1; otherwise, repeat step 2 3. If no spill, successively pop vertices off the stack and color them in the lowest color not used by some neighbor; otherwise, insert spill code, recompute G I and start from step 1 CS406/534 Fall 2004, Prof. Li Xu 59 59

60 Chaitin s Algorithm in Practice 3 Registers Stack CS406/534 Fall 2004, Prof. Li Xu 60 60

61 Chaitin s Algorithm in Practice 3 Registers Stack CS406/534 Fall 2004, Prof. Li Xu 61 61

62 Chaitin s Algorithm in Practice 3 Registers Stack CS406/534 Fall 2004, Prof. Li Xu 62 62

63 Chaitin s Algorithm in Practice 3 Registers Stack CS406/534 Fall 2004, Prof. Li Xu 63 63

64 Chaitin s Algorithm in Practice 3 Registers Colors: : 2: 3: Stack CS406/534 Fall 2004, Prof. Li Xu 64 64

65 Chaitin s Algorithm in Practice 3 Registers Colors: 5 1: : 3: Stack CS406/534 Fall 2004, Prof. Li Xu 65 65

66 Chaitin s Algorithm in Practice 3 Registers Colors: 5 1: : 3: Stack CS406/534 Fall 2004, Prof. Li Xu 66 66

67 Chaitin s Algorithm in Practice 3 Registers Colors: 4 5 1: : 3: Stack CS406/534 Fall 2004, Prof. Li Xu 67 67

68 Chaitin s Algorithm in Practice 3 Registers 1 Stack Colors: 1: 2: 3: CS406/534 Fall 2004, Prof. Li Xu 68 68

69 Chaitin s Algorithm in Practice 3 Registers Colors: 1: 2: 3: Stack CS406/534 Fall 2004, Prof. Li Xu 69 69

70 Improvement in Coloring Scheme Optimistic Coloring (Briggs, Cooper, Kennedy, and Torczon) Instead of stopping at the end when all vertices have at least k neighbors, put each on the stack according to some priority When you pop them off they may still color! 2 Registers: CS406/534 Fall 2004, Prof. Li Xu 70 70

71 Improvement in Coloring Scheme Optimistic Coloring (Briggs, Cooper, Kennedy, and Torczon) Instead of stopping at the end when all vertices have at least k neighbors, put each on the stack according to some priority When you pop them off they may still color! 2 Registers: 2-colorable CS406/534 Fall 2004, Prof. Li Xu 71 71

72 Chaitin-Briggs Algorithm 1. While vertices with < k neighbors in G I > Pick any vertex n such that n < k and put it on the stack > Remove that vertex and all edges incident to it from G I This may create vertices with fewer than k neighbors 2. If G I is non-empty (all vertices have k or more neighbors) then: > Pick a vertex n (using some heuristic condition), push n on the stack and remove n from G I, along with all edges incident to it > If this causes some vertex in G I to have fewer than k neighbors, then go to step 1; otherwise, repeat step 2 3. Successively pop vertices off the stack and color them in the lowest color not used by some neighbor > If some vertex cannot be colored, then pick an uncolored vertex to spill, spill it, and restart at step 1 CS406/534 Fall 2004, Prof. Li Xu 72 72

73 Chaitin Allocator renumber Build SSA, build live ranges, rename build Build the interference graph coalesce spill costs simplify select Fold unneeded copies LR x LR y, and < LR x,lr y > G I combine LR x & LR y Estimate cost for spilling each live range Remove nodes from the graph While stack is non-empty pop n, insert n into G, I & try to color it while N is non-empty if n with n < k then push n onto stack else pick n to spill push n onto stack remove n from G I spill Spill uncolored definitions & uses Chaitin s algorithm CS406/534 Fall 2004, Prof. Li Xu 73 73

74 Chaitin Allocator renumber Build SSA, build live ranges, rename build Build the interference graph coalesce Fold unneeded copies LR x LR y, and < LR x,lr y > G I combine LR x & LR y W at c h this edge spill costs simplify select spill Estimate cost for spilling each live range Remove nodes from the graph While stack is non-empty pop n, insert n into G, I & try to color it Spill uncolored definitions & uses Chaitin s algorithm while N is non-empty if n with n < k then push n onto stack else pick n to spill push n onto stack remove n from G I CS406/534 Fall 2004, Prof. Li Xu 74 74

75 Chaitin-Briggs Allocator renumber Build SSA, build live ranges, rename build Build the interference graph coalesce spill costs simplify select Fold unneeded copies LR x LR y, and < LR x,lr y > G I combine LR x & LR y Estimate cost for spilling each live range Remove nodes from the graph While stack is non-empty pop n, insert n into G, I & try to color it while N is non-empty if n with n < k then push n onto stack else pick n to spill push n onto stack remove n from G I spill Spill uncolored definitions & uses Briggs algorithm (1989) CS406/534 Fall 2004, Prof. Li Xu 75 75

76 Picking a Spill Candidate When n G I, n k, simplify must pick a spill candidate Chaitin s heuristic Minimize spill cost current degree If LR x has a negative spill cost, spill it pre-emptively Cheaper to spill it than to keep it in a register If LR x has an infinite spill cost, it cannot be spilled No value dies between its definition & its use No more than k definitions since last value died (safety valve) Spill cost is weighted cost of loads & stores needed to spill x Bernstein et al. Suggest repeating simplify, select, & spill with several different spill choice heuristics & keeping the best CS406/534 Fall 2004, Prof. Li Xu 76 76

77 Other Improvements to Chaitin-Briggs Spilling partial live ranges Bergner introduced interference region spilling Limits spilling to regions of high demand for registers Splitting live ranges Simple idea break up one or more live ranges Allocator can use different registers for distinct subranges Allocator can spill subranges independently (use 1 spill location) Conservative coalescing Combining LR x LR y to form LR xy may increase register pressure Limit coalescing to case where LR xy < k Iterative form tries to coalesce before spilling CS406/534 Fall 2004, Prof. Li Xu 77 77

78 Results are pretty good Performance Simple procedures allocate without spills There is some room for improvement Long blocks, regions of high pressure Many implementation issues Many people have looked at improving Chaitin-Briggs Better allocations Better coloring Softer coalescing Better spilling Spilling partial live ranges Better implementations Faster graph construction Faster coalescing CS406/534 Fall 2004, Prof. Li Xu 78 78

79 Rematerialization Never-killed values can be rematerialized (rather than spilled) Operands are always available Computed in a single operation Cheaper to recompute than to store & reload (the classic spill ) Allocator must Discover & mark never-killed LRs Reflect rematerialization in spill costs Use all this knowledge to generate right spills Chaitin rematerialized LRs that were entirely never-killed We can do partial LRs CS406/534 Fall 2004, Prof. Li Xu 79 79

80 Bibliography Briggs, Cooper, & Torczon, Improvements to Graph Coloring Register Allocation, ACM TOPLAS 16(3), May, Bernstein, Goldin, Golumbic, Krawczyk, Mansour, Nashon, & Pinter, Spill Code Minimization Techniques for Optimizing Compilers, Proceedings of PLDI 89, SIGPLAN Notices 24(7), July George & Appel, Iterated Register Coalescing, ACM TOPLAS 18(3), May, Bergner, Dahl, Engebretsen, & O Keefe, Spill Code Minimization via Interference Region Spilling, Proceedings of PLDI 97, SIGPLAN Notices 32(6), June Cooper, Harvey, & Torczon, How to Build an Interference Graph, Software Practice and Experience, 28(4), April, 1998 Cooper & Simpson, Live-range splitting in a graph coloring register allocator, Proceedings of the 1998 International Conference on Compiler Construction, LNCS 1381 (Springer), March/April CS406/534 Fall 2004, Prof. Li Xu 80 80

81 Instruction selection Summary Global register allocation CS406/534 Fall 2004, Prof. Li Xu 81 81

82 Next Class Optimization Data-flow analysis SSA CS406/534 Fall 2004, Prof. Li Xu 82 82

Instruction Selection, II Tree-pattern matching

Instruction Selection, II Tree-pattern matching Copyright 2003, Keith D. Cooper, Ken Kennedy & Linda Torczon, all rights reserved. Students enrolled in Comp 4 at Rice University have explicit permission