LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS. Gary D. Hachtel University of Colorado. Fabio Somenzi University of Colorado.
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1 LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS by Gary D. Hachtel University of Colorado Fabio Somenzi University of Colorado Springer
2 Contents I Introduction 1 1 Introduction VLSI: Opportunity and Challenge Manufacturing Technology Design technology Why VLSI VLSI Processes Design Styles Design Decomposition Logic (Circuit) Design Styles Overview of Optimal Logic Synthesis Area-Time Tradeoff Curves The Technology Independent View A Bit-Serial Full Adder Circuit The Technology Dependent View Technology Mapping Testing Is What I Fabricated What I Wanted? Graph Models and Finite State Machines Successors and Predecessors Graph Algorithms and Complexity Complexity Computing the Product of Sets of Sets Longest Paths Backtracing Complexity of Computing the Longest Path Asymptotic Complexity (or just complexity) Worst Case Asymptotic Upper Bound Complexity Complexity of Algorithms Practical Complexities Brief Summary of MOS Device Behavior Notes Summary Problems 39
3 2 A Quick Tour of Logic Synthesis with the Help of a Simple Example A Simple Case Conversion Circuit First Refinement The Transform Block The CC Block An Optimized Transform Block The Command Interpreter Checking for Equality Optimizing the Command Interpreter Technology Mapping Problems co Oo II Two Level Logic Synthesis 73 3 Boolean Algebras * 3.1 Sets, Relations, and Functions Sets '' \' ''' ''''' Relations Reflexive Binary Relations Functions Partial Orders Partially Ordered Sets of Hasse Diagrams ]. [ [ " ' ' ' * The Meet and Join Operations..." Totallv OrrWn «* «,. ^_,, '."' V ' 8 R7 ' Induction Definition of Boolean Algebras.'.'.'.'.'.".'.'." ].".".' " ' _" " [ ^ 3.3 ^ ^ Boolean Formulae ' ' ' ' ' Boolean Functions ::^ J.5.1 i n c o m p l e t e l v «r, ^ : c. i «... _ Notes.. &pecmed Boolean Functions Summary Problems
4 ix 4 Synthesis of Two-Level Circuits Design Optimality Two-Level Logic Cost Functions for Two-Level Implementations Minimality and Testability Sums of Products and Products of Sums Implicants and Prime Implicants Quine's Prime Implieant Theorem Iterated Consensus Consensus and Implications: A Digression The Tabular Method of Computing the Prime Implicants Iterated Consensus in General Recursive Computation of Prime Implicants Selecting a Subset of Primes The Unate Covering Problem Reduction Techniques Essential Columns or Variables Row or Constraint Dominance Column or Variable Dominance Systematically Exploring the Search Space Computation of the Lower Bound The Branch-and-Bound Algorithm Choice of the Splitting Variable Examples of Splitting and Lower Bounding The Unate Covering Problem as an Integer Linear Program Multiple Output Functions Multiple-Output Primes Formulating the Covering Problem Incompletely Specified Multiple-Output Functions Notes Summary Problems Heuristic Minimization of Two-Level Circuits Local Search Local Search Applied to Logic Minimization A Simple Local Search Algorithm for Logic Minimization Checking for Equivalence and Tautology Unate Functions Additional Speed-Up Techniques for Tautology Checking Examples of Tautology Checks Choosing the Right Direction Recursive Complementation Using the OFF-set in the Expansion Identifying Essential Primes Multiple-Valued Logics 204
5 5.6 Notes Summary Problems Binary Decision Diagrams (BDDs) Representing Logic Functions with BDDs Binary Decision Diagrams by Way of Examples Formal Definition of BDDs How to Build the BDD for / Reduced BDDs Why Ordering is Important Design Considerations for a BDD Package Algorithms The ITE Algorithm Complement Edges The Computed Table Conditioning of the ITE Calls The ITE.GONSTANT Algorithm Notes Summary Problems 244 III Models of Sequential Systems Models of Sequential Systems 7.1 Introduction to Finite State Machines Synthesis of Finite State Machines FSMs: Definitions, Notation, and Examples Examples Incomplete Specification FSM Minimization for Completely Specified Machines Identifying the Equivalent States of an FSM State Equivalence Checking: the Partition/Refinement Approach Finding the Reduced Machine 2T Moore Machines and DFAs The Iterative Collapsing Approach Summary of State Equivalence Checking Methods Graph Algorithms for FSM Traversal Graphs, Subgraphs, and Components Graph Traversal Breadth First Search Traversal Depth First Search Finding the SCCs of a Directed Graph Shortest Paths Models of Sequential Systems FSTs: Strings, Runs, Reachability and Products Finite State Transition Structures
6 xi NFAs and e-moves FSTs as Labeled Digraphs Strings, Tapes and Runs of FSTs Product of FSTs FSM Equivalence Checking Strings which Distinguish Two Machines Building the Product Machine Equivalence Identification by Isomorphism Reachability Analysis FSM Traversal Using Binary Decision Diagrams Symbolic FSM State Traversal Transition Relations and Symbolic Image Computation Notes Summary Problems Synthesis and Verification of Finite State Machines Minimization of Incompletely Specified Machines Finding the Compatible Pairs Finding the Maximal Compatibles Finding the Prime Compatibles Setting up the Covering Problem Forming the Reduced Table The Binate Covering Problem Formulation of BCP Reduction Techniques Choice of the Splitting Variable and Bounding Maximal independent set Choice of the branching column Infeasible problems An Example of Reductions State Encoding Practical Encoding Algorithms Decomposition and Encoding Partitions Partitions with Substitution Property Computation of the S.P. Partitions General Decomposition and State Encoding Notes Notes Summary Problems 357
7 xii CONTENTS 9 Finite Automata Finite Automata and Regular Languages String Acceptance Languages of Finite Automata Complements of Languages Examples DFA Synthesis Determinization of FSTs and FAs The Subset Construction The Deterministic Image w-regular Automata Formal Verification with L-Automata w-regular Languages w-regular Language Containment Lifting Acceptance Conditions to a Product //-Automaton Example of Product L-Automaton BDD Representation of Cycle Sets and Recur Edges The Language Containment Algorithm Example of Containment Check Notes Summary Problems 398 IV Multilevel Logic Synthesis Multi-Level Logic Synthesis Introduction Networks and Algebraic Operations Representation Issues and Choices Alternate Node Representations Representing Switching Functions in Factored Form Factored Forms Algebraic and Boolean Expressions Algebraic and Boolean Factored Forms Value of a Factorization Equivalent, Maximal, and Optimum Factorizations Size, Unateness, and Cofactors of a Factored Form Division Kernels and Co-Kernels Computation of Co-Kernels and Kernels Heuristic Factoring Algorithms Generic Factoring Algorithm Quick Factor Good Factor Boolean Factor Summary of Factoring Algorithms 435
8 xiii Rectangle Covering Decomposition and Restructuring Algebraic Resubstitution Selective Node Elimination Extraction Notes Summary 441 lo.loproblems Multi-Level Minimization Introduction Boolean Networks Network Cost Don't Cares in Multi-Level Networks Satisfiability Don't Cares Observability Don't Cares Use of Don't Cares in Minimization Internal and External Don't Cares External Satisfiability Don't Care Conditions External Observability Don't Care Conditions Internal Satisfiability Don't Cares Observability Don't Cares Computing ODCs with the Boolean Difference Prime and Irredundant Networks Two-Level Minimization with Multi-Level Don't Cares Notes Summary 470 ll.loproblems Automatic Test Generation for Combinational Circuits Introduction Faults and Fault Models Automatic Test Generation Excitation and Sensitization A Simple Test Generation Algorithm Implications and Backtracking Choice of the Decision Variables Putting the Pieces Together Redundancy Removal, Notes Summary Problems 492
9 xiv,, CONTENTS 13 Technology Mapping 505 IXI Graph Covering and Technology Mapping Choice of Base Functions Creating the Subject Graph The DAG-Covering Problem Tree Covering by Dynamic Prograniming D i^11 512»o j Delay Optimization and Graph Covering Notes Summary 514 l3.lopk>blen>» 515 A ASCII Codes 523 B Supplementary Problems 525 Uxr 537 Bibliography Index 555
LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS
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