GateLevel Minimization


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1 GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,
2 Outlines The Map Method FourVariable Map FiveVariable Map ProductofSums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel Implementations ExclusiveOR Function HDL Description DCD032
3 The Map Method Boolean function sum of minterms sum of products (or product of sum) in the simplest form a minimum number of terms a minimum number of literals The simplified expression may not be unique Gatelevel minimization refers to the design task of finding an optimal gatelevel implementation of Boolean functions describing a digital circuit. Logic minimization algebraic approach: lack specific rules Karnaugh map approach a simple straight forward procedure a pictorial form of a truth table applicable if the # of variables < 7 A diagram made up of squares each square represents one minterm DCD033
4 TwoVariable Map A twovariable map four minterms x' = row 0; x = row 1 y' = column 0; y = column 1 a truth table in square diagram DCD034
5 Eight minterms Gray code sequence ThreeVariable Map Any two adjacent squares in the map differ by only one variable e.g., m 5 and m 7 can be simplified m 5 + m 7 = xy'z + xyz = xz (y'+y) = xz yz DCD035
6 Example 3.1 F(x,y,z) = S(2,3,4,5) = x'y + xy' DCD036
7 ThreeVariable Map m 0 and m 2 (m 4 and m 6 ) are adjacent m 0 + m 2 = x'y'z' + x'yz' = x'z' (y'+y) = x'z' m 4 + m 6 = xy'z' + xyz' = xz' (y'+y) = xz' yz DCD037
8 Example 3.2 F(x,y,z) = S(3,4,6,7) = yz+ xz' DCD038
9 Four adjacent squares 2, 4, 8 and 16 squares ThreeVariable Map m 0 +m 2 +m 4 +m 6 = x'y'z'+x'yz'+xy'z'+xyz' = x'z'(y'+y) +xz'(y'+y) = x'z' + xz = z' m 1 +m 3 +m 5 +m 7 = x'y'z+x'yz+xy'z+xyz =x'z(y'+y) + xz(y'+y) =x'z + xz = z yz DCD039
10 Example 3.3 F(x,y,z) = S(0,2,4,5,6)= z'+ xy' DCD0310
11 Example 3.4 Given F = A'C + A'B + AB'C + BC Express it in sum of minterms => S(1,2,3,5,7) Find the minimal sum of products expression => F=C+A B DCD0311
12 The map FourVariable Map 16 minterms combinations of 2, 4, 8, and 16 adjacent squares DCD0312
13 Example 3.5 Simplify the Boolean Function: F(w,x,y,z) = S(0,1,2,4,5,6,8,9,12,13,14)=y'+w'z'+xz' DCD0313
14 Example 3.6 Simplify the Boolean Function: Given F = A B C + B CD + A BCD + AB C => F = B D + B C + A CD DCD0314
15 Systematic Simplification Implicant a product term of which if the function has the value 1 for all minterms. A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map into a rectangle with the number of squares a power of 2 remove any literal not a implicant. A prime implicant is called an Essential Prime Implicant if it is the only prime implicant that covers (includes) one or more minterms. Prime Implicants and Essential Prime Implicants can be determined by inspection of a KMap. A set of prime implicants "covers all minterms" if, for each minterm of the function, at least one prime implicant in the set of prime implicants includes the minterm. Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD0315
16 Example of Prime Implicants Find ALL Prime Implicants BD CD C ESSENTIAL Prime Implicants C BD BD A AB 1 1 B D AD BC BD A Minterms covered by single prime implicant 1 1 B D Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD0316
17 Example of Prime Implicants Find all prime implicants for: F(A, B,C, D) = Sm (0,2,3,8,9,10,11,12,13,14,15) BD 1 C 1 BC 1 A 1 1 A D Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. B DCD0317
18 Example of Prime Implicants Find all prime implicants for: G(A, B,C, D) = Sm Hint: There are seven prime implicants! (0,2,3,4,7,12,13,14,15) C A B D Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD0318
19 Prime Implicants Selection Rule Find all prime implicants. Include all essential prime implicants in the solution Select a minimum cost set of nonessential prime implicants to cover all minterms not yet covered: Minimize the overlap among prime implicants as much as possible. Make sure that each prime implicant selected includes at least one minterm not included in any other prime implicant selected avoid redundancy. Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. DCD0319
20 Selection Rule Example Simplify F(A, B, C, D) given on the Kmap. C Selected Essential C A B A B D Minterms covered by essential prime implicants Source: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals. D DCD0320
21 Simplification Using Prime Implicants Consider F( A, B, C, D ) = (0,2,3,5,7,8,9,10,11,13,15) The simplified expression may not be unique F = BD+B'D'+CD+AD = BD+B'D'+CD+AB = BD+B'D'+B'C+AD = BD+B'D'+B'C+AB' Digital Circuit Design DCD0321
22 FiveVariable Map Map for more than four variables becomes complicated. fivevariable map: two fourvariable map (one on the top of the other) DCD0322
23 Example 3.7 F = S(0,2,4,6,9,13,21,23,25,29,31)=A'B'E'+BD'E+ACE DCD0323
24 Another Map for Example 3.7 DCD0324
25 Relationship between # of Adjacent Squares and # of the Literals Digital Circuit Design DCD0325
26 Product of Sums Simplification Approach 1: Complement from minterms Step 1: Simplify F' in the form of sum of products Step 2: Apply DeMorgan's theorem F = (F')' => F': sum of products => F: product of sums Approach 2: Duality from maxterms Combinations of maxterms M 0 M 1 = (A+B+C+D)(A+B+C+D') = (A+B+C)+(DD') = A+B+C CD AB M 0 M 1 M 3 M 2 01 M 4 M 5 M 7 M 6 11 M 12 M 13 M 15 M M 8 M 9 M 11 M 10 DCD0326
27 Given F = S(0,1,2,5,8,9,10) Approach 1: Step 1: F' = AB+CD+BD' Example 3.8 Step 2: Apply DeMorgan's theorem; F=(A'+B')(C'+D')(B'+D) Approach 2: Think in terms of maxterms DCD0327
28 Implementation of Example 3.8 DCD0328
29 Truth Table of Function F Consider the function defined in Table 3.2. In sumofminterm: F( x, y, z ) = (1,3,4,6) In productofmaxterm: F ( x, y, z) = (0,2,5,7) Taking the complement of F F( x, y, z) = ( x z )( x z) DCD0329
30 Truth Table of Function F Consider the function defined in Table 3.2. Combine the 1 s: F( x, y, z) = x' z xz' Combine the 0 s : F' ( x, y, z) = xz x' z' DCD0330
31 Don'tCare Conditions The value of a function is not specified for certain combinations of variables BCD; : don't care The don't care conditions can be utilized in logic minimization can be implemented as 0 or 1 DCD0331
32 Example 3.9 Given F(w,x,y,z) = S(1,3,7,11,15) and d(w,x,y,z) = S(0,2,5) F = yz + w'x'; F = yz + w'z F = S(0,1,2,3,7,11,15) ; F = S(1,3,5,7,11,15) Either expression is acceptable DCD0332
33 NAND Implementation NAND gate is a universal gate can implement any digital system Two graphic symbols for a NAND gate DCD0333
34 Twolevel Implementation NANDNAND = sum of products Example: F = AB+CD F = ((AB)' (CD)' )' =AB+CD DCD0334
35 Example 3.10 F( x, y, z ) = (1,2,3,4,5,7) F( x, y, z) = xy x y z DCD0335
36 General Design Procedure Procedure 1. Convert all AND gates to NAND gates with ANDinverter graphic symbols. 2. Convert all OR gates to NAND gates with inverteror graphic symbols. 3. Check all the bubbles in the diagram. For every bubble that is not compensated by another small circle along the same line, insert an inverter or complement the input literal. DCD0336
37 Multilevel NAND Circuits Implementing F = A(CD + B) + BC using NAND gate only DCD0337
38 Multilevel NAND Circuits Implementing F = (AB +A B)(C+ D ) using NAND gate only DCD0338
39 NOR Implementation NOR function is the dual of NAND function. The NOR gate is also universal. Two graphic symbols for a NOR gate DCD0339
40 Twolevel Implementation Implementing F = (A + B)(C + D)E using NOR gate only. DCD0340
41 Multilevel NOR Circuits Implementing F = (AB +A B)(C + D ) using NOR gate only. DCD0341
42 Other Twolevel Implementations Digital Circuit Design Wired logic A wire connection between the outputs of two gates Opencollector TTL NAND gates: wiredand logic The NOR output of ECL gates: wiredor logic F = ( AB) ( CD) = ( AB CD) = ( A B )( C D ) F = ( A B) ( C D) = [( A B)( C D)] ANDORINVERT function ORANDINVERT function DCD0342
43 Nondegenerate Forms Considering four types of goats: AND, OR, NAND, NOR, 16 possible combinations of twolevel forms are obtained. Eight of them: degenerate forms = a single operation The eight nondegenerate forms ANDOR, ORAND, NANDNAND, NORNOR, NOROR, NAND AND, ORNAND, ANDNOR ANDOR and NANDNAND = sum of products ORAND and NORNOR = product of sums NOROR, NANDAND, ORNAND, ANDNOR =? DCD0343
44 ANDORInvert Implementation ANDORINVERT (AOI) Implementation NANDAND = ANDNOR = AOI F = (AB+CD+E)' F' = AB+CD+E (sum of products) DCD0344
45 ORANDInverter Implementation ORANDINVERT (OAI) Implementation ORNAND = NOROR = OAI F = ((A+B)(C+D)E)' F' = (A+B)(C+D)E (product of sums) simplified F' in products of sum DCD0345
46 Tabular Summary DCD0346
47 Example 311 Example 3.11 F' = x'y+xy'+z (F': sum of products) F = (x'y+xy'+z)' (F: AOI implementation) F = x'y'z' + xyz' (F: sum of products) F' = (x+y+z)(x'+y'+z) (F': product of sums) F = ((x+y+z)(x'+y'+z))' (F: OAI) DCD0347
48 Example 3.11 DCD0348
49 ExclusiveOR Function ExclusiveOR (XOR) x y = xy'+x'y ExclusiveNOR (XNOR) (x y)' = xy + x'y' Some identities x 0 = x x 1 = x' x x = 0 x x' = 1 x y' = (x y)' x' y = (x y)' Commutative and associative A B = B A (A B) C = A (B C) = A B C DCD0349
50 ExclusiveOR Function Implement (x'+y')x + (x'+y')y = xy'+x'y = x y DCD0350
51 Odd and Even Functions A B C = (AB'+A'B)C' +(AB+A'B')C = AB'C'+A'BC'+ABC+A'B'C = S(1,2,4,7) An odd number of 1's DCD0351
52 Logic Diagram of Odd and Even Functions Logic diagram of odd and even functions DCD0352
53 FourVariable ExclusiveOR Function Fourvariable ExclusiveOR function A B C D = (AB +A B) (CD +C D) = (AB +A B)(CD+C D )+(AB+A B )(CD +C D) Digital Circuit Design DCD0353
54 Parity Generation and Checking Parity Generation and Checking a parity bit: P = x y z parity check: C = x y z P C=1: an odd number of data bit error C=0: correct or an even # of data bit error DCD0354
55 Parity Generation and Checking DCD0355
56 Hardware Description Language (HDL) Describe the design of digital systems in a textual form hardware structure function/behavior Timing VHDL and Verilog HDL
57 A TopDown Design Flow Specification RTL design and Simulation Logic Synthesis Gate Level Simulation ASIC Layout FPGA Implementation
58 Module Declaration Examples of keywords: module, endmodule, input, output, wire, and, or, and not.
59 HDL Example 3.1 Digital Circuit Design HDL description for circuit shown in Fig. 3.37
60 Example: timescale directive timescale 1 ns/100ps Gate Displays Digital Circuit Design
61 HDL Example 3.2 Digital Circuit Design Gatelevel description with propagation delays for circuit shown in Fig. 3.37
62 HDL Example 3.3 Test bench for simulating the circuit with delay Digital Circuit Design
63 Simulation Output for HDL Example 3.3
64 Boolean Expression Digital Circuit Design Boolean expression for the circuit of Fig Boolean expression: HDL Example 3.4
65 HDL Example 3.4
66 UserDefined Primitives General rules: Declaration: Implementing the hardware in Fig. 3.39
67 HDL Example 3.5
68 HDL Example 3.5 (Continued)
69
70 Conclusions From this lecture, you have learned the follows: FourVariable Map FiveVariable Map ProductofSums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel Implementations ExclusiveOR Function Verilog Design DCD0370
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