A High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions *

Transcription

1 JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 21, (2005) A High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Mebership Functions * SHIH-HSU HUANG AND JIAN-YUAN LAI + Departent of Electronic Engineering Chung Yuan Christian University Chungli, 320 Taiwan E-ail: shhuang@cycu.edu.tw + E-ail: yuan@vlsi.el.cycu.edu.tw Fuzzy logic has been successfully applied in various fields, but these applications have usually suffered fro the proble of low speed. Typically, calculation of the atching degree requires very high latency, which liits the overall inference speed. In this paper, we prove that the atching degree between two trapezoid-shaped ebership functions can be obtained without traversing all the eleents in the universal disclosure set. Based on this analysis, we present an effective hardware unit that can be used to obtain the atching degree very quickly. Moreover, a pipelined parallel VLSI fuzzy inference processor is proposed to take advantage of our basic idea. The proposed hardware architecture has been ipleented using 0.35µ process technology. To the best of our knowledge, our fuzzy inference processor is the only existing architecture that can tackle 64 rules with fuzzified inputs at a speed of 7 MFLIPS. Keywords: digital design, hardware design, high perforance, fuzzy logic, fuzzy inference 1. INTRODUCTION The goal of fuzzy inferencing [1, 2] is to build a odel of a huan expert, which is capable of controlling a plant without thinking in ters of a atheatical odel. Given a set of input data, the fuzzy inference processor evaluates proposed actions in ters of their confority with the knowledge base. A real-tie fuzzy inference involves processing the knowledge base in a period of constant tie and with iniu speed of one MFLIPS [3]. In this paper, we investigate a digital hardware design for real-tie fuzzy inferencing based on trapezoid-shaped ebership functions. The digital hardware fuzzy inference processor was originally developed by Togai and Watanabe [4]. Many variations [5-9] have been proposed to iprove the inferencing perforance. The speed bottleneck of these fuzzy inference processors [4-9] lies in the calculation of the atching degree. In order to obtain the atching degree between two ebership functions, these fuzzy inference processors need to traverse all the eleents in the universal disclosure set. As a result, calculating the atching degree requires very high latency, which liits the overall circuit perforance. Received Deceber 16, 2003; revised July 19, 2004; accepted Noveber 15, Counicated by Liang-Gee Chen. * A preliinary version, entitled A High-Speed VLSI Fuzzy Logic Controller with Pipeline Architecture, has appeared in the Proceedings of IEEE International Conference on Fuzzy Systes (FUZZ-IEEE),

2 608 SHIH-HSU HUANG AND JIAN-YUAN LAI By iposing soe restrictions on the specification of the fuzzy inference processor, one can accelerate calculation of the atching degree 1. Soe digital hardware fuzzy inference processors [10, 11] restrict their inputs to crisp values; in other words, they do not tackle fuzzified inputs. Since calculating the atching degree only involves a crisp value and a ebership function, these fuzzy inference processors need not traverse all the eleents in the universal disclosure set to obtain the atching degree. The ain drawback of these fuzzy inference processors [10, 11] is that they do not cover the ignorance of the input easure. Asica, Catania and Russo [12] assue that each ebership function is coposed of nine segents. Based on this assuption, they use a binary search echanis to obtain the atching degree between two ebership functions. The ain drawback of their fuzzy inference processor [12] is that they apply a detection process to extract active rules fro the knowledge base. As a result, the inference speed of their fuzzy inference processor depends on the nuber of active rules. Therefore, their fuzzy inference processor is only suitable for applications that have few active rules. In this paper, we assue that each ebership function is trapezoid-shaped 2. We prove that the atching degree between two trapezoid-shaped ebership functions can be obtained without traversing all the eleents in the universal disclosure set. Based on this analysis, we present an effective hardware unit that can be used to obtain the atching degree very quickly. Moreover, a pipelined parallel VLSI hardware is proposed to take advantage of our basic idea. The ain features of our fuzzy inference processor are as follows: (1) Our approach achieves very high perforance. To the best of our knowledge, our fuzzy inference processor is the only existing hardware architecture that can tackle 64 rules with fuzzified inputs at the speed of 7 MFLIPS. (2) Different fro [12], our approach is independent of the nuber of active rules; i.e., the inference speed of our fuzzy inference processor always reains constant. The rest of the paper is organized as follows. Section 2 provides background inforation. Then, in section 3, we present the otivation for fast calculation of the atching degree. The architecture of our proposed fuzzy inference processor is described in section 4. Ipleentation results and coparisons with other hardware architectures are presented in section 5. Finally, soe concluding rearks are presented in section PRELIMINARIES In this section, we will provide background inforation. Section 2.1 will provide an overview of the fuzzy syste. Then, section 2.2 will introduce the concept of fuzzy rules. Finally, section 2.3 will describe the function of fuzzy inferences. 1 The atching degree can be obtained by applying the table-look-up ethod. 2 Note that this assuption is practical for the design of real fuzzy systes. In fact, to reduce the eory storage requireent, [7, 9] and [11] also assue that each ebership function is trapezoid-shaped.

3 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR Fuzzy Syste Fuzzy logic replaces true and false with continuous set ebership values ranging fro ZERO to ONE, which irrors natural language concepts. Therefore, a fuzzy set is, in fact, a ebership function µ S : M [0, 1], which associates each eleent in the universal disclosure set M with a real value between ZERO and ONE. In other words, the ebership function µ S can be defined as a fuzzy set S = {( i, µ S ( i )) i M}, where 0 µ S ( i ) 1. A typical block diagra of a fuzzy syste is depicted in Fig. 1. The fuzzy syste consists of a sensor, fuzzification unit, fuzzy inference processor, and plant. The sensor is used to detect the state of the plant. Since the inputs fro the plant are crisp values, a fuzzification unit is used to translate the into linguistic descriptions in ters of ebership functions 3. Due to the fuzzification operation, the fuzzy inference process can deal with ignorance of the input easures. The fuzzy inference processor is coposed of two iportant parts: the fuzzy rules and the inference engine. The details are presented in the following section. Fig. 1. A typical block diagra of a fuzzy syste. 2.2 Fuzzy Rules A typical fuzzy rule assues the for of a conditional stateent as follows: IF (a set of conditions is satisfied) THEN (a set of consequences can be inferred). 3 Note that the fuzzy inference processors in [10] and [11] restrict their inputs to crisp values. Thus, for these two fuzzy inference processors [10, 11], there is no need to use a fuzzification unit to translate crisp values into linguistic descriptions in ters of ebership functions.

4 610 SHIH-HSU HUANG AND JIAN-YUAN LAI Each rule has an antecedent (or IF) part containing several preconditions and a consequent (or THEN) part that describes the output action. The antecedent and consequent parts are characterized by appropriate ebership functions. For exaple, one fuzzy rule fro a two-input and one-output ceent ixer controller could be as follows: IF (the teperature is approxiately 90 ) and (the viscosity is very thick) THEN (increase the aount of water significantly). The phrases approxiately, very, and significantly represent an intuitive feeling of an expert huan and can be expressed as ebership functions. Since the fuzzy predicates are inherently range based, fewer rules are required than is the case with typical boolean-based expert systes, which deand precise atches. In this paper, without loss of generality, we assue that each fuzzy rule has two inputs (X and Y) and one output (O), and is expressed in the following for: Rule R i : IF (X is A i ) and (Y is B i ) then (O is C i ), where A i and B i are the antecedent ebership functions associated with the linguistic input variables X and Y, respectively, and C i is the consequent ebership function associated with the linguistic output variable O. 2.3 Fuzzy Inferences A fuzzy inference is characterized by a set of fuzzy rules. Assue that the knowledge base has r fuzzy rules, including R 1, R 2,, and R r. With the fuzzified inputs X and Y, the fuzzy inference process can be depicted in the following steps. Firstly, X and Y are siultaneously broadcasted to all fuzzy rules to be copared with the antecedent parts. The atching degrees between (X and A i ) and between (Y and B i ) are obtained with the ax-in calculation ethod as in the following two equations: A i α = ax(in( X( ), A( ))), (1) B i i α = ax(in( Y ( ), B( ))). (2) The weight of rule R i is calculated as follows: A B i i i i ω = in( α, α ). (3) Hence, rule R i recoends a control decision as follows: O ( ) = in( ω, C ( )). (4) i i i Lastly, the linguistic output O, which cobines the control decisions of all the fuzzy rules, is given by

5 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR 611 i 0 r 1 (5) i O ( ) = O( ) = ax( O( ),..., O ( )). Since the inference process should output soe crisp control results in practice, it requires the use of a defuzzifier. If the center of gravity (COG) algorith is eployed, the final crisp output o can be calculated as follows: ( O( )) o =. (6) O( ) 3. THE MOTIVATION We assue that each ebership function is trapezoid-shaped. Our basic idea is derived fro an analysis of all the possible conditions of ax-in calculation between two trapezoid-shaped ebership functions. We will prove that the atching degree can be obtained by using only the corner points of two trapezoid-shaped ebership functions. Based on this basic idea, we will propose an effective hardware unit that can be used to obtain the atching degree very quickly. 3.1 The Forat A trapezoid has two segents in parallel. In order to represent all possible trapezoid-shaped ebership functions, we store the four corner points. As a result, the new forat uses four tuples (L0, L1, R1, R0) to describe a trapezoid-shaped ebership function, in which L0, L1, R1, and R0 are the x-axis values of the leftost point in the lower left side of the trapezoid, the leftost point in the upper left side of the trapezoid, the rightost point in the upper right side of the trapezoid, the rightost point in the lower right side of the trapezoid, respectively. According to the definition, the grade of L0 and the grade of R0 are always equal to 0, and the grade of L1 and the grade of R1 are always equal to 1. Fig. 2 shows an exaple illustrating our new forat. µ() 1 0 L0 L1 R1 R0 ebership function Fig. 2. A trapezoid-shaped ebership function.

6 612 SHIH-HSU HUANG AND JIAN-YUAN LAI A trapezoid-shaped ebership function has the following properties. Firstly, the upper side is not longer than the lower side; otherwise an eleent ay have ultiple ebership values. In other words, for each trapezoid-shaped ebership function, we always have L0 L1 R1 R0. Secondly, the grade of each eleent in the upper side, i.e., in the region [L1, R1], is always equal to 1. Triangular shapes can be considered as special cases of trapezoidal shapes, which have L1 = R Fast Max-Min Calculation As described in section 2.2, the ax-in calculation is perfored to find the atching degree between the fuzzified input and the antecedent ebership function associated with the input. Based on the properties of trapezoid-shaped ebership functions, all the possible conditions of the ax-in calculation are given in Lea 1. Lea 1 Suppose that the antecedent ebership function is (a1, a2, a3, a4), and that the fuzzified input is (x1, x2, x3, x4). All the possible situations of ax-in calculation can be classified according to the following six utually exclusive conditions: (1) a4 x1, (2) a3 < x2 and a4 > x1, (3) x2 a3 < x3, (4) a2 x3 a3, (5) x3 < a2 and x4 > a1, (6) x4 a1. Proof: It is obvious that a1 a2 a3 a4 and x1 x2 x3 x4. Without loss of generality, we first classify the conditions into the following two cases: the case with a3 < x2 and the case with a3 x2. Then, we further analyze each case as follows: (i) For the case with a3 < x2: If a4 x1, it belongs to condition (1). If a4 > x1, it belongs to condition (2). (ii) For the case with a3 x2: If x3 > a3, it belongs to condition (3). If a2 x3 a3, it belongs to condition (4). If a2 > x3: When x4 > a1, it belongs to condition (5). When x4 a1, it belongs to condition (6). The following lea shows that only the corner points need to be used as inputs to perfor the ax-in calculation. Lea 2 Suppose that the antecedent ebership function is (a1, a2, a3, a4), and that the fuzzified input is (x1, x2, x3, x4). The atching degree can be obtained by follows:

7 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR 613 (1) If a4 x1 or x4 a1, then the atching degree is 0. (2) If x2 a3 x3 or a2 x3 a3, then the atching degree is 1. (3) If a3 < x2 and x1 < a4, then the atching degree is the grade value of the cross-over point between the line fro (a3, 1) to (a4, 0) and the line fro (x1, 0) to (x2, 1). (4) If x3 < a2 and a1 < x4, then the atching degree is the grade value of the cross-over point between the line fro (x3, 1) to (x4, 0) and the line fro (a1, 0) to (a2, 1). Proof: For the classification of conditions in Lea 1, we can further analyze the results of the ax-in calculation as follows. (i) a4 x1: This condition looks like Fig. 3 (a). The result of the ax-in calculation is 0. (ii) a3 < x2 and a4 > x1: This condition looks like Fig. 3 (b) or Fig. 3 (c). The result of the ax-in calculation is the grade value of the cross-over point between the line fro (a3, 1) to (a4, 0) and the line fro (x1, 0) to (x2, 1). (iii) x2 a3 < x3: This condition looks like Fig. 3 (d). The result of the ax-in calculation is 1. (iv) a2 x3 a3: This condition looks like Fig. 3 (e). The result of the ax-in calculation is 1. (v) x3 < a2 and x4 > a1: This condition looks like Fig. 3 (f) or Fig. 3 (g). The result of the ax-in calculation is the grade value of the cross-over point between the line fro (x3, 1) to (x4, 0) and the line fro (a1, 0) to (a2, 1). (vi) x4 a1: This condition looks like Fig. 3 (h). The result of the ax-in calculation is 0. We suarize the above discussion in Lea 2. µ () µ() a2 a3 x2 x3 a2 a3 x2 x3 a1 a4 (a) x1 x4 a1 x1 (b) a4 x4 µ() µ() a2 a3 x2 x3 a2 x2 a3 x3 x1 a1 (c) a4 x4 a1 x1 (d) a4 x4 Fig. 3. The conditions of ax-in calculation.

8 614 SHIH-HSU HUANG AND JIAN-YUAN LAI µ () µ() x2 a2 x3 a3 x2 x3 a2 a3 x1 a1 (e) x4 a4 x1 a1 (f) x4 a4 µ() µ() x2 x3 a2 a3 x2 x3 a2 a3 a1 x1 (g) x4 a4 x1 x4 (h) a1 a4 Fig. 3. (Cont d) The conditions of ax-in calculation. Fro Lea 2, we know that the ax-in calculation can be perfored without traversing all the eleents in the universal disclosure set. The ajor coputational cost is spent on calculating of the grade value of the cross-over point between two lines. 3.3 Hardware Design According to Lea 2, Fig. 4 shows a logic diagra of the dedicated ax-in calculation hardware. Without loss of generality, we assue that the grade is discretized into 16 levels, and that the universal disclosure set has 64 eleents. Thus, the representations of grade values 0 and 1 are 0000 and 1111, respectively. The details of the dedicated hardware are given below. Firstly, a coparator circuit is applied to distinguish the four conditions classified in Lea 2. The inputs to the coparator circuit are a1, a2, a3, a4, x1, x2, x3, and x4. The outputs of the coparator circuit need two bits due to four conditions. The cross-over point calculation circuit is applied to find the grade value of the cross-over point between two lines. According to the result obtained by the coparator circuit, the output of the dedicated ax-in calculation hardware is selected. The ethod used to calculate the cross-over point is described below. According to Lea 2, conditions 3 and 4 require the cross-over point calculation unit. In the following, we will derive the inputs to the cross-over point calculation circuit for these two conditions, respectively. We find that: for condition 3, the inputs to the cross-over point calculation circuit are a3, a4, x1, and x2; for condition 4, the inputs to the cross-over point calculation circuit are x3, x4, a1, and a2. Thus, the inputs to the cross-over point calculation circuit are selected by the output of the coparator circuit as shown in Fig. 4.

9 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR 615 a1 a2 a3 a4 x1 x2 x3 x coparator circuit 0 1 a4 x4 a3 x3 x1 a1 2-to-1 ux 2-to-1 ux 2-to-1 ux x2 a2 2-to-1 ux phase 1 phase 1 + <<4 phase 2 phase 2 cross-over point calculator SRT-division to-1 ux 4 weight Fig. 4. A block diagra of the ax-in calculator. Fig. 5 presents an exaple illustrating condition 3 of Lea 2. Suppose that a grade is discretized into 2 l levels. Under the condition that a3 < x2 and x1 < a4, the atching degree can be calculated as follows: l 2( x2 a3) atching degree = 2, a+ x l where a = a 4 a 3 and x = x 2 x 1. Therefore, under this condition, the inputs to the cross-over point calculation circuit are a3, a4, x1, and x2. Fig. 6 illustrates another exaple, which is in condition 4 of Lea 2. In a siilar way, the atching degree can be calculated as: l 2( a2 x3) atching degree = 2 a + x l

10 616 SHIH-HSU HUANG AND JIAN-YUAN LAI µ() a x a2 a3 x2 x3 atching degree a1 x1 a4 x4 Fig. 5. The cross-over point calculation for condition 3 of Lea 2. µ() x' a' x2 x3 a2 a3 atching degree x1 a1 x4 a4 Fig. 6. The cross-over point calculation for condition 4 of Lea 2. where a = a 2 a 1 and x = x 4 x 3. In this condition, the inputs to the cross-over point calculation circuit are x3, x4, a1, and a2. Note that a cobinational circuit can be used to ipleent the division in the cross-over point calculation unit. Here, we use the SRT division algorith proposed in [13]. In addition, we split the division in the cross-over point calculation unit into two phases. Therefore, as shown in Fig. 4, our ax-in calculator is divided into two phases. 3.4 Coparisons Let the notations l and e denote the nuber of bits for the discrete levels and the nuber of bits for the eleents in the universal disclosure set, respectively. In other words, the grade is discretized into 2 l discrete levels, and the universal disclosure set has 2 e eleents. We use a 0.35µ cell library to ipleent the proposed ax-in calculator with respect to the following two specifications: (1) l = 4 bits and e = 6 bits; and (2) l = 6 bits and e = 8 bit. According to our ipleentation results, we find that our ax-in calculator uses 1230 gates, and that the longest path delay is 16 ns if l = 4 bits and e = 6 bits; in addition,

11 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR 617 our ax-in calculator uses 2000 gates, and the longest path delay is 20 ns if l = 6 bits and e = 8 bits. Therefore, for both of the specifications, even if the clock rate is designed to operate at 100 MHz, the longest path delay only takes two clock cycles. In other words, for both specifications, each phase of our ax-in calculator only takes two clock cycles. Since our ax-in calculator has two phases, the nuber of clock cycles needed to coplete a ax-in calculation between two ebership functions is four. Furtherore, because of the pipelining design, the average nuber of clock cycles needed to obtain a atching degree is two. We copared our ax-in calculator with other ax-in calculators. Table 1 tabulates the coparison results, including the nuber of bytes needed to store a trapezoid-shaped ebership function, the nuber of clock cycles needed to coplete a ax-in calculation, and the average nuber of clock cycles needed to obtain a atching degree. Copared with [4-6], and [12], we find that our approach uses uch less storage space. Although [7] uses less storage space, it only can represent five syetrical trapezoidal shapes, while, our approach allows for any trapezoid-shaped ebership function. In addition, Table 1 shows that [4-6], and [7] take 64 clock cycles to coplete a ax-in calculation. Note that [4-7], and [12] are designed to operate at clock rates of less than 66 MHz. However, even if the clock rate is designed to operate at 100 MHz, our approach only takes four clock cycles to coplete a ax-in calculation. Approach Specification Table 1. Coparison of different ax-in calculators. Meory Required to Store a Mebership Function (Bytes) Nuber of Clock Cycles Required to Coplete a Max-Min Calculation Average Nuber of Clock Cycles Required to Obtain a Matching Degree [4-6] l = 4, e = [7] l = 4, e = [12] l = 6, e = Ours l = 4, e = l = 6, e = THE PROPOSED ARCHITECTURE Our fuzzy inference processor has a pipelined parallel architecture, with 64 rules, two input variables, and one output variable. Fig. 7 shows the proposed architecture. Following the sae specifications in [4-7], the grade is discretized into 16 levels (i.e., l = 4 bits), and the universal disclosure set has 64 eleents (i.e., e = 6 bits). Regarding teporal parallelis, the fuzzy inference execution can be split into the following three priary steps: fuzzy decoding, inference decision, and defuzzification. As described in section 3.3, our ax-in calculator is a two-phase pipelined design. Accordingly, our fuzzy inference processor also uses two pipeline stages to ipleent the function of fuzzy decoding function. In addition, our fuzzy inference processor uses the COG algorith to ipleent the defuzzification function. Since the COG algorith is

12 618 SHIH-HSU HUANG AND JIAN-YUAN LAI Address Data Antecedent rule eory Consequent rule eory Address Data X,Y Fuzzy decoding 16-to-1 Mux Max-tree Inference decision O() Acculator Divisor Defuzzification o stage 1 stage 2 stage 3 stage 4 stage 5 Fig. 7. The proposed pipelined architecture. coplex, the defuzzification function is also divided into two pipeline stages: an accuulation stage and a division stage. Therefore, our fuzzy inference processor has five pipeline stages: two pipeline stages for fuzzy decoding, one pipeline stage for aking inference decisions, and two pipeline stages for defuzzification. Note that each pipeline stage takes 16 clock cycles. The details of our fuzzy inference processor are given in the following. For the convenience of presentation, we will introduce each priary step in the fuzzy inference execution procedure. 4.1 Fuzzy Decoding The function of fuzzy decoding is to find the weights of rules, including weight 0, weight 1,, weight 63. Note that, as described in section 3.3, the function of the ax-in calculator is split into two phases. Thus, the fuzzy decoding step is also divided into two pipeline stages. Fig. 8 shows the logic diagra of a fuzzy decoder. Two ax-in calculation units operate in parallel to obtain the atching degrees of the two input variables at the sae tie, as shown in Eqs. (1) and (2). Then, a iniu unit is eployed to obtain the weight, as shown in Eq. (3). Note that, at each pipeline stage, a rule only takes two clock cycles. Thus, in order to fully utilize the fuzzy decoder, eight rules are processed sequentially during a pipeline stage. In the first pipeline stage, two 8-to-1 ultiplexers are used to sequentially pass the rules to ax-in calculators; in the second pipeline stage, a 1-to-8 deultiplexer is used to sequentially store the obtained weights. The fuzzy decoder is expandable. To process 64 rules, we eploy eight fuzzy decoders, operating in parallel. During a pipeline stage, rules R 8i (i = 0, 1, 2, 3, 4, 5, 6, 7) are processed in the first and the second cycles, rules R 8i+1 (i = 0, 1, 2, 3, 4, 5, 6, 7) are processed in the third and the fourth cycles, rules R 8i+2 (i = 0, 1, 2, 3, 4, 5, 6, 7) are processed in the fifth and the sixth cycles, and so on.

13 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR 619 Y & B8 i Y & B 8i+ 1 Y & B 8i+ 7 X & A8 i X & A8 i+ 1 X & A8 i to-1 ux 8-to-1 ux stage 1 stage sel phase 1 phase 2 ax-in calculator phase 1 phase 2 ax-in calculator stage 2 tage in weight 8i 4 8-to-1 deux registers... 4 weight8 i+7 Fig. 8. A block diagra of the fuzzy decoder. 4.2 Inference Decisions The inference decision function finds the grades of the output variable O, including O(0), O(1),, and O(63). Each grade O(), where = 0, 1, 2,, and 63, is deterined by eans of a axiu of 64 control decisions, which are O 0 (), O 1 (),, and O 63 (). We eploy 64 control decision units, operating siultaneously. As Eq. (4) shows, the control decision of a rule O i () is obtained by eans of the iniu between weight i and C i (), where = 0, 1, 2,, and 63, and i = 0, 1, 2,, and 63. Fig. 9 depicts the control decision unit of a fuzzy rule. The weight i, which is the weight of rule R i, is calculated in the fuzzy decoding step. C i is the consequent ebership function associated with rule R i. For coputation of O i (), where = 0, 1, 2,, and 63, we need to have all 64 eleents of C i. To find all the control decisions within a pipeline stage, four 16-to-1 ultiplexers are used. Then, C i (15), C i (31), C i (47), and C i (63) are sapled on the first cycle, C i (14), C i (30), C i (46), and C i (62) are sapled on the second cycle, and so on. Consequently, O i (15), O i (31), O i (47), and O i (63) are obtained on the first cycle, O i (14), O i (30), O i (46), and O i (62) are obtained on the second cycle, and so on. Four axiu units, i.e., MAX1, MAX2, MAX3, and MAX4, are used to ipleent Eq. (5) siultaneously. Each axiu unit has 64 inputs. In the first cycle, the inputs to MAX1 are O 0 (15), O 1 (15),, and O 63 (15); the inputs to MAX2 are O 0 (31), O 1 (31),, and O 63 (31); the inputs to MAX3 are O 0 (47), O 1 (47),, and O 63 (47); and the inputs to MAX4 are O 0 (63), O 1 (63),, and O 63 (63). In the second cycle, the inputs to

14 620 SHIH-HSU HUANG AND JIAN-YUAN LAI C i (63) C i (48) C (47) C i i (32) C i (31) C i (16) C i (15) C i (0) to-1 ux 16-to-1 ux 16-to-1 ux 16-to-1 ux weight i in in in in MAX4 i MAX3 i MAX2 i MAX1 i Fig. 9. A block diagra of the fuzzy control decision unit. MAX1 are O 0 (14), O 1 (14),, and O 63 (14); the inputs to MAX2 are O 0 (30), O 1 (30),, O 63 (30); the inputs to MAX3 are O 0 (46), O 1 (46),, and O 63 (46); the inputs to MAX4 are O 0 (62), O 1 (62),, and O 63 (62); and so on. 4.3 Defuzzification The function of defuzzification is to copute the COG of the final fuzzy output O, as the depicted in Eq. (6). It includes two pipeline stages: accuulation and division. In order to process the outputs of four axiu units in parallel, four accuulation paths are eployed during the accuulation stage. Let P and Q represent the nuerator and denoinator of the defuzzification equation. Then, P is given as = 15 = 31 = 47 = 63 P = O ( ) + O ( ) + O ( ) + O ( ) = P1 + P2 + P3 + P4, Q = O( ) + O( ) + O( ) + O( ) = 1 = 16 = 32 = 48 = Q1 + Q2 + Q3 + Q4. The four accuulation paths are P1, P2, P3, and P4, respectively. The ethod adopted to ipleent accuulation path P1 is described below. We have P1 = 15 O(15) + 14 O(14) O(1). Suppose P1 j = O(15) + O(14) + + O(j). Then, we can have P1 = P P P1 1 and Q1 = P1 0. By sapling and accuulating the

15 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR 621 values in the sequence of O(15), O(14),, and O(0), we can obtain the values of P1 and Q1 within a pipeline stage. At the sae tie, the values of P2, P3, P4, Q2, Q3, and Q4 can be obtained siultaneously based on the siilar architecture. For exaple, P2 can be calculated by adding the following two ters: [15 O(31) + 14 O(14) O(17)] and 16 [O(31) + O(30) + + O(16)]. In our design, a 4-bit shifter ipleents the ultiplication to 16. The divisor is based on the SRT division algorith proposed in [13]. It takes 16 clock cycles to coplete the division operation. Subsequently, the final crisp output o is obtained. 5. PROCESSOR PERFORMANCE The fuzzy inference processor proposed in section 4 has been ipleented and fabricated using 0.35µ process technology. The chip layout is shown in Fig. 10. The chip size is µ * µ. The axiu clock rate is 112 MHz. Because of its pipelining design, our fuzzy inference processor only takes 16 clock cycles to coplete a fuzzy inference. Thus, the inference speed is 7 MFLIPS. Note that the inference speed of our fuzzy inference processor is independent of the nuber of active rules and, thus, is applicable to various real-tie applications. To the best of our knowledge, the proposed fuzzy inference processor is the only approach that can tackle 64 rules with fuzzified inputs at a speed of 7 MFLIPS. Fig. 10. Layout view. Here, we will discuss the reason why our fuzzy inference processor can achieve very high perforance. The following analysis will deonstrate the advantage of our fuzzy decoder. As shown in Fig. 8, our fuzzy decoder copletes eight rules within a

16 622 SHIH-HSU HUANG AND JIAN-YUAN LAI pipeline stage (i.e., 16 clock cycles). Further analysis shows that the nuber of gates, including the gate count of the eory needed to store eight rules, is For the purpose of coparison, we have used the sae cell library to ipleent another fuzzy decoder that uses the typical ax-in calculation ethod (i.e., traversing all the eleents in the universal disclosure set) to coplete the eight rules in parallel. Analysis of the results showed that the nuber of clock cycles was 64, and that the nuber of gates was Clearly, by exploiting the proposed ax-in calculator, our fuzzy decoder not only speeds up the fuzzy coputation but also reduces the chip size. Table 2 copares our approach with other ASIC ipleentations, including those in [5, 7, 10-12]. For the purpose of coparison, we have ipleented a version that has the sae design described in section 4 but has 8 inputs, 4 outputs, l = 6 bits, and e = 8 bits. When we applied post-layout gate-level tiing analysis, we estiated the inference speed to be 4.5 MFLIPS. We also wish to draw the reader s attention to the following three points: (1) Our fuzzy inference processor as well as those presented in [5, 7] and [12] can tackle fuzzified inputs, while those in [10] and [11] restrict their inputs to crisp values. (2) Note that the COG algorith is the ost typical ethod used in the defuzzification process, while the Yager algorith [14] and the Sugeno algorith [15] are less accurate. Our fuzzy inference processor as well as those in [5] and [7] use the COG algorith; those in [10] and [12] use the Yager algorith; and that in [11] uses the Sugeno algorith. (3) The inference speeds reported in [10] and [12] are only fro pre-layout gate-level tiing analysis. Thus, no chip area inforation is provided. Table 2. Coparison of our approach with other ASIC ipleentations. Processor Ours [5] [7] [10] [11] [12] Resolution l = 4 e = 6 l = 6 e = 8 l = 4 e = 6 l = 4 e = 6 l = 6 e = 8 l = 4 e = 7 l = 6 e = 8 l = 6 e = 8 Active Rules / Inputs 2 8 4/ l = 6 e = 8 Input Type Fuzzy Fuzzy Fuzzy Fuzzy Crisp Crisp Fuzzy Fuzzy Fuzzy Outputs 1 4 2/ Defuzzification Method Process Technology COG COG COG COG Yager Sugeno Yager Yager Yager CMOS 0.35µ CMOS 0.35µ CMOS 1.1µ CMOS 0.8µ CMOS 0.5µ CMOS 0.7µ CMOS 0.5µ CMOS 0.5µ Area ( 2 ) CMOS 0.5µ MFLIPS In fact, it is very difficult to copare these ASIC ipleentations directly. They are not only ipleented with different process technology but also designed based on different specifications. However, with careful analysis, we find that our fuzzy inference

17 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR 623 processor achieves very high perforance. Under a siilar specification, our fuzzy inference processor achieves MFLIPS, while that in [5] only achieves MFLIPS. Although we use better process technology, our speedup is significant since our inference speed is 12 ties faster than that reported in [5]. On the other hand, under a siilar specification, our fuzzy inference processor achieves MFLIPS, while that in [12] only achieves MFLIPS. Although we use better process technology, our speedup is significant since our inference speed is 4.5 ties faster than that reported in [12]. Copared with the architecture presented in [12], another advantage of our architecture is that it is uch easier to extend to adaptive fuzzy applications [16, 17]. Due to the binary search echanis, the fuzzy rules in [12] have to be sorted. As a result, in [12], the flexibility in odifying ebership functions is liited. Our architecture, on the other hand, does not have this liitation. Therefore, a learning echanis can be easily integrated into our architecture. Fig. 11 shows how our architecture can be extended to adaptive fuzzy applications. As shown in Fig. 11, the learning echanis can odify any antecedent ebership function and any consequent ebership function without causing any side effect. Learning echanis address data address data Antecedent rule eory Consequent Rule eory X,Y Fuzzy decoding Weight adjuster 16-to-1 Mux Max-tree Inference decision O() Acculator Divisor Defuzzification o stage 1 stage 2 stage 3 stage 4 stage 5 Fig. 11. An illustration showing how our architecture can be extended to adaptive fuzzy systes. Soe high-speed fuzzy inference processors, including those proposed in [3, 8, 9], and [18], are not ipleented using the ASIC approach. Note that the ipleentation in [3] is a software ipleentation running on a high-speed DSP, those in [8] and [9] are FPGA ipleentations, and that in [18] is an extension of the MIPS processor. Table 3 copares our fuzzy inference processor with those. Fro Table 3, we can find that our fuzzy inference processor achieves very high perforance. It is worth entioning that [3] and [18] executed their instructions sequentially. Therefore, the works in [3] and [18] are only suitable for applications that have few rules or whose required inference speeds are not high. Furtherore, regarding the work in [9], the following two issues should be pointed out.

18 624 SHIH-HSU HUANG AND JIAN-YUAN LAI Ipleentation Resolution Table 3. Coparison of our approach with those in [3, 8, 9] and [18]. Ours [3] [8] [9] [18] Dedicated ASIC Design l = 4 e = 6 l = 6 e = 8 Software Running on the DSP TSM320C6201 FPGA Design Using ALTERA Flex10K l = 5 e = 8 FPGA Design Using XILINX XC2V1000 l = 6 e = 8 l = 6 e = 8 Extra Instructions for MIPS Processor Active Rules Inputs Outputs MFLIPS (1) The inference speed reported in [9] depends on the nuber of active rules. (2) The defuzzification ethod used in [9] is the Sugeno algorith [15]. 6. CONCLUSIONS In this paper, we have presented a high-speed VLSI fuzzy inference processor for the real-tie applications using trapezoid-shaped ebership functions. Fro our analysis of all possible conditions, we have proved that the atching degree between two trapezoid-shaped ebership functions can be obtained without traversing all the eleents in the universal disclosure set. A pipelined parallel VLSI architecture has been proposed to take advantage of our basic idea. The fuzzy inference processor has been ipleented and fabricated using 0.35µ process technology. Experiental data show that the processing speed reaches 7 MFLIPS with 64 rules, two inputs, and one output. To the best of our knowledge, our fuzzy inference processor is the only existing architecture that can tackle 64 rules with fuzzified inputs at a speed of 7 MFLIPS. ACKNOWLEDGMENTS This work was supported in part by the National Science Council of Taiwan, R.O.C., under contract nuber NSC E Furtherore, the authors would like to acknowledge fabrication support provided by National Chip Ipleentation Center (CIC). REFERENCES 1. L. A. Zadeh, Fuzzy sets, Inforation Control, Vol. 8, 1965, pp K. Nakaura, N. Sakashita, Y. Nitta, K. Shioura, and T. Tokuda, Fuzzy inference and fuzzy inference processor, IEEE Micro, Vol. 13, 1993, pp E. Frias-Martinez, Real-tie fuzzy processor on a DSP, in Proceedings of IEEE International Conference on Eerging Technologies and Factory Autoation, Vol. 1, 2001, pp

19 HIGH-SPEED VLSI FUZZY INFERENCE PROCESSOR M. Togai and H. Watanabe, Expert syste on a chip: an engine for real-tie approxiate reasoning, IEEE Expert Magazine, Vol. 1, 1986, pp H. Watanabe, W. D. Dettloff, and K. E. Yount, A VLSI fuzzy logic controller with reconfigurable, cascade architecture, IEEE Journal of Solid-State Circuits, Vol. 25, 1990, pp T. C. Chiueh, Optiization of fuzzy logic inference architecture, IEEE Coputer, Vol. 25, 1992, pp J. M. Jou and P. Y. Chen, An adaptive fuzzy logic controller: its VLSI architecture and applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systes, Vol. 8, 2000, pp R. D Aore, O. Saotoe, and K. H. Kienitz, A two-input, one-output bit-scalable architecture for fuzzy processors, IEEE Design and Test of Coputers, 2001, pp F. Hoburg and R. Paloera-Garcia, A high-speed scalable and reconfigurable fuzzy controller, in Proceedings of IEEE International Syposiu on Circuits and Systes, Vol. 5, 2003, pp G. Asica, V. Catania, M. Russo, and L. Vita, Rule driven VLSI fuzzy processor, IEEE Micro, Vol. 16, 1996, pp A. Gabriellu and E. Gandolfi, A fast digital fuzzy processor, IEEE Micro, Vol. 19, 1999, pp G. Asica, V. Catania, and M. Russo, VLSI hardware architecture for coplex fuzzy systes, IEEE Transactions on Fuzzy Systes, Vol. 7, 1999, pp J. L. Hennessy and D. A. Patterson, Coputer Architecture: A Quantitative Approach, 2nd ed., Morgan Kaufann Publishers, M. Figueiredo, F. Goide, A. Rocha, and R. Yager, Coparison of Yager s level set ethod for fuzzy logic control with Mandai s and Larsen s ethods, IEEE Transactions on Fuzzy Systes, Vol. 1, 1993, pp M. Sugeno, Industrial Application of Fuzzy Control, Elsevier Science Publishers, E. Cox, Adaptive fuzzy systes, IEEE Spectru, 1993, pp S. H. Huang, W. H. Peng, and J. Y. Lai, Autoatic synthesis of fuzzy systes based on trapezoid-shaped ebership functions, in Proceedings of IEEE Asia and Pacific Conference on Circuits and Systes, Vol. 2, 2002, pp V. Salapura, A fuzzy RISC processor, IEEE Transactions on Fuzzy Systes, Vol. 8, 2000, pp Shih-Hsu Huang ( 黃世旭 ) received the B.S. degree in Coputer Science and Inforation Engineering fro National Chiao Tung University, Hsinchu, Taiwan, in 1989, the M.S. degree in Coputer Science fro National Tsing Hua University, Hsinchu, Taiwan, in 1991, and the Ph.D. degree in Coputer Science and Inforation Engineering fro National Taiwan University, Taipei, Taiwan, in Fro 1995 to 2000, he was with coputer and counications research laboratories, industrial technology research institute, Hsinchu, Taiwan, rising to the po-

20 626 SHIH-HSU HUANG AND JIAN-YUAN LAI sition of deputy anager of IC design departent, responsible for the design of high perforance IC s. He has been an Assistant Professor with the Departent of Electronic Engineering at Chung Yuan Christian University, Chungli, Taiwan, since His research interests include tiing optiization, digital design, and fuzzy logic. Jian-Yuan Lai ( 賴建元 ) received the B.S. degree in Electronic Engineering fro Chung Yuan Christian University, Chungli, Taiwan, in 2000, and the M.S. degree in Electronic Engineering fro Chung Yuan Christian University, Chungli, Taiwan, in His research interests include fuzzy logic, data copression, and VLSI chip design.