An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits

Transcription

1 An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits Juan A. Prieto, José M. Quintana, A. Rueda and José L. uertas Instituto de Microelectrónica de Sevilla - Centro Nacional de Microelectrónica Avda. Reina Mercedes s/n, (Edif. CICA) E-41012, Sevilla, Spain Published at the IEEE Int. Symp. on Circuits and Systems, (ISCAS 94), pp , IEEE. Personal use of this material is permitted. owever, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author s copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 1

2 An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits Juan A. Prieto, José M. Quintana, A. Rueda and José L. uertas Departamento de Diseño Analógico Centro Nacional de Microelectrónica Edif. CICA Avda. Reina Mercedes s/n Sevilla SPAIN Name and address of author responsible for correspondence: José M. Quintana Departamento de Diseño Analógico Centro Nacional de Microelectrónica Edif. CICA Avda. Reina Mercedes s/n Tel.: (34) FAX: (34) Sevilla SPAIN Abstract: This paper presents an optimization algorithm which simultaneously deals with the problems of placement and global routing in an analog macrocell layout style. The optimization process is based on a simulated annealing algorithm. We evaluate the physical placement of the cells and estimate the global routing for each intermediate solution generated. The basic idea, that together with an appropriate heuristic make the algorithm extremely efficient, consist of maintaining the same basic representative structure (slicing structures) for both problems. This method enables us to impose symmetry conditions and to penalize the existence of sensitive and noisy nets in the same channel. 2

3 Introduction Automation of analog design is considered as indispensable for the progress and competitivity of mixed analog-digital VLSI circuits. One of the main problems is the automatic generation of the layout, since this design phase is very time consuming and prone to errors when performed manually. Circuit layout generally consists of two phases. The relative placement in the plane of a group of cells (circuit elements), and the routing of the nets. Automation of any of these processes is usually treated as an optimization problem with a series of objectives: normally, minimize the total area and estimated routing length for the placement problem, and minimize the number of tracks or channel width for routing problem. There are different approximations which are efficient for digital cases, but this is not so in the case of analog circuits due to the need to consider other specific objectives. The complexity of analog layout derives not only from the diversity of the cells and the disparity between them depending on the concrete application, but also on the layout s influence on the global performance of the circuit. Thus, considerations of symmetry at a cell or wire level, on sensitive and noisy nets, on orientation, etc., are more important that those of area and connection length. The solution of the problem of analog macrocell placement cannot be separated from the problem of their routing. This strong dependence obliges us to consider both problems together in the optimization process. The integration of placement and routing problems in a quasi-exhaustive heuristic optimization algorithm presents serious problems. Among these, the most complex is the calculation of routing related of the solutions generated in the placement phase. An optimum solution to this problem requires solving an NP-complete problem for each optimization algorithm iteration. A feasible solution, applied frequently in digital and adopted in the initial phases of placement in analog [1,2], is to make only one approximate estimation of the routing length using a linear complexity algorithm, and leave refining of the optimum sizing of the routing channels for a later phase. The linear complexity methods traditionally used rely on a measurement of the rectangular environment which encompasses all the pins in one net, the bounding box. This measurement gives only an estimate of the area and routing length, without defining the exact path taken by each net through the different routing channels. Consequently, it is not adequate to contemplate analog constraints, such as the penalization of crosses and/or the co-existence of specific nets in the same channel. This paper presents an algorithm for the simultaneous optimization of placement and global routing capable of contemplating analog restrictions, which has been implemented in the pro- 3

4 gram GELSA. The basic idea, which together with an appropriate heuristic make the algorithm very efficient, is to maintain the same basic representation structure for both problems. In particular, slicing structures [3,4] have been chosen. These structures efficiently represent the placement problem and are used in many solutions for both digital and analog automatic layout [1,2]. We will use the slicing tree as an elemental graph for each intermediate placement solution. This elemental graph contains hierarchical information of the channels and the connections between them. We will perform an estimation of the routing on the same tree by using a heuristic algorithm of linear complexity that we have developed, and have integrated in the optimization process without excessively increasing the total cost. The potential of the algorithm is shown by the results obtained from different examples of analog cells. Simulated annealing [5] is the optimization technique used. This is a general and robust method that minimizes the probability of being trapped in local minima and allows obtaining solutions close to the global optimum. In spite of the fact that it generally requires large CPU time, it is considered a very adequate technique to deal with analog requirements, due to the flexibility that it offers in determining complex cost functions, without affecting the complexity of the optimization algorithm [2]. This summary is distributed as follows. First, we will present the optimization algorithm implemented in GELSA, explaining the mechanism we use to integrate the macrocell placement, the routing, and the evaluation of the symmetry requirements processes. Next, we will consider some examples of application to specific problems and finally, some conclusions will be outlined. Description of the Proposed Algorithm We have used slicing structures to represent the problem, we designate the operators of the horizontal and vertical cuts as and V, respectively. The slicing structures including the N cells (operands) are represented as binary slicing trees, or in Polish notation on the alphabet = {1, 2,, N;, V} [4]. All these structures are made up of N operands (macrocell) and (N-1) operators (channels). Each cell is also related to a group of routing pins bonded to electric nets in the circuit. Each point of the solution space is represented by a binary slicing tree that bonds the N cells of the problem and by a parameter that selects one of the four possible orientations. Figure 1 shows a Pidgin_C description of the optimization algorithm implemented in GELSA. At a given temperature T, the function Gen_mov() explores the search space modifying the slicing tree, or the orientation of one or a group of cells. Once a new configuration is generated on the slic- 4

5 ing tree, the function Place&Route() determines the physical position of each cell, the pins, and routing channels (defined by the and V operators), and makes an estimate of the area and routing length. Finally, the function Eval_cost() evaluates the different terms of the cost function. All configurations which reduce the solution cost are accepted, and those which increase it are accepted with a certain probability. The temperature T is reduced after each iteration until a specific temperature is reached, or specific stop criteria are met. Figure 1: General optimization loop. The proposed approximation is relatively similar to that implemented in [2], both in the general optimization method employed as in the type of representation on which it is based. owever, there are important differences in the manner of dealing with symmetries, in the global routing estimation, and in the cost function considered. A detailed description follows of the main parts of GELSA. Set of moves We enlarged the group of basic moves defined by Wong and Liu [4] in such a way that we can deal with moves of groups of cells, which is of great assistance to verify symmetry restricmain() { i = Read_initial_configuration(); P i = Place&Route(i); C i = Eval_cost(i, P i ); T = Det_T o (i, P i ); while (stop_criterium not satisfied) { while (inner-loop_criterium not satisfied) { j = Gen_mov(i); P j = Place&Route(j); C j = Eval_cost(j, P j ); if ( accept(t, C i, C j ) ) { i = j; C i = C j ; } } /* inner_loop */ T = Update(T); } The function Gen_mov() gives a valid solution directly altering the slicing tree by making a set of moves which affect its reverse Polish notation or the orientation of the cells or groups of cells (through the operator that relates them). The slicing tree is made up of 2N-1 elements which may be cells (user-defined macrocells) or operators (horizontal and vertical cuts). 5

6 tions. The additional movements group acts on cells (rotation) and subtrees (swapping, rotation, and insertion) [7]. The Place&Route function Figure 2 is a Pidgin_C description of the Place&Route function, the central module of the algorithm developed. It uses as input the codification of the problem obtained after applying a move to the slicing tree; as a result it determines the exact placement of the cells and channels, as well as a realistic estimation of the global routing. Place&Route(j) { Det_pos(j); /* determines cells and channels positions */ G = VE(j); /* extend the slicing tree to an VE graph*/ for (net=1; net NETS; net++) { R = Def_branch(G, net); /* defines the initial group of branches to propagate */ while (R not connected) { R = Prop_branch(G, R, net); } L net = Simplify(G, R, net); /* gives the list of routed channels for each net */ S net = Det_routing(L net ); /* gives the location of the net in each occuped channel */ } for (net=1; net NETS; net++) for (channel=1; channel N+3; channel++) D channel = Det_channel_max_density(channel, S net ); for (channel=1; channel N+3; channel++) Det_channel_width(channel, D channel ); Update_place(j); } Figure 2: Integrated algorithm of Place&Route. The Det_pos() function simultaneously determines the physical positions of the N macrocells, of the N-1 internal routing channels (with zero width waiting to process the global routing), of the four external channels (the circuit peripherals), and of the pins. It also designates specific pins that affect each channel. This process is carried out in two steps: a) The size of each subtree and the relative placement of each cell that makes it up are evaluated and routing pins associated with each of the channels are extracted. For this, the expression of reverse Polish notation of the slicing tree is directly explored. 6

7 b) Once the real size of the problem is known, the slicing tree is explored in reverse direction, fixing the cell s position. Next, the VE() function extends the tree incorporating the four external channels, forming the extended graph of partitioning (VE graph) as indicated in Figure 3. In this figure, CORE refers to the slicing tree of the 2N-1 elements, and the external channels are represented by N, E, S, and W (North, East, South, and West faces). V (W) (S) V (E) (CORE)(N) Figure 3: VE graph. On the VE graph and for each net, the Def_branch() function defines the initial group of branches (one for each group of pins in a specific channel) that function Prop_branch() will propagate directly rising in the hierarchy of the VE graph, avoiding parallel channels, until one unique effective branch results. If the considered branches belong to a supply, ground and pad-connected net, their access is guaranteed to one of the four external channels. At this point, those channels susceptible for use in the routing of each net are marked. The solution thus generated may lead to inefficient routing. To avoid this, the Simplify() function applies a series of simplification rules to the VE graph with the marked channels and as a result, supplies the channels used to perform the minimized routing of each electric net. These rules (and their symmetrical ones) allow shortcuts to rise in the hierarchy of the graph, as shown in Figure 4. The rule to use depends on the tree structure; if one arrives to a level already marked, then the minimized way given by the rule is used; on the contrary, this branch is propagated to the next higher level. The next step is to apply the function Det_routing() in order to determine the routing at the level of segments occupied in each channel, the maximum occupation density of each channel (Det_channel_max_density() function), and its width (Det_channel_width() function). This information is used later for the routing length estimation as well as to avoid the coexistence of noisy and sensitive nets in the same channel. Finally, the Update_place() function physically relocates the macrocells. 7

8 V V V V V(//) V(//) (//) (//) V V(//) V(//) (//) RULE 1 RULE 2 RULE 3 // indicates a paralell channel set Figure 4: Simplification rules. The cost function The function Eval_cost() performs a quantitative evaluation of the area occupied by the design, of the routing length, and of symmetry restrictions; and reduces these terms to one unique scalar value which reflects the quality of the generated solution. This cost is expressed as: COST = C_AREA AREA + C_AREL AREL + C_BOUND BOUND+C_NETS SS_NETS + C_SUPPLY SUPPLY + C_RESTS RESTS + C_SIM SIMCOST + C_FF FFCOST where C_AREA, C_AREL, C_BOUND, C_NETS, C_SUPPLY, C_RESTS, C_SIM, and C_FF are the weights relating to each term, that can vary during the cooling process. AREA is the area occupied by the physical solution considered. AREL is the relative area of the minimum occupied area. SS_NETS expresses the routing length. SUPPLY refers to the number of channels occupied by the supply lines. RESTS serves to avoid the existence of sensitive and noisy nets in the same channel. SIMCOST controls the symmetry limitations at a cell level. FFCOST controls the form factor of the solution, and BOUND expresses the semiperimeter of the rectangle that encompasses the solution considered, including the desired form factor, expressed as BOUND = 0.5 (FACFORM X + Y). All the terms in the cost function (except AREA) are normalized with the purpose of making the cost evaluation independent of the specific problem and the set of weights. Considerations regarding symmetry A previously reported approach [8] for the application of the symmetry constraints works on the real space once the cells are positioned. In our proposed approach, the slicing tree itself is 8

9 used to group the cells affected by the symmetry in one unique subtree, and thus treat them as a single cell. The direct method that we propose, allows us to treat centroid, matching, and array (matching of more than two cells) groups of symmetries. The cost associated to a symmetry group (Cost group ) depends on the degree of orientation of the N GS cells of the group (f orientation ), and the separation between the subtree associated to the symmetry group and the subtree defined as reference of this group (f form_subtree). The cost is obtained as a weighted sum of both terms: 2.0 f Cost form_subtree + f orientation group = (1) Let us illustrate how the array symmetry group is processed. In this case one wishes to have N GS cells forming an array with same orientation (for instance, a set of matching transistors with their Drain pins facing the same channel). First, we define the term f orientation as a normalized value in the interval [0.0, 1.0]. The procedure is the following: a) We evaluate the number of cells in each of the four orientations. b) As reference orientation, we assume the orientation of the majority of the cells in the symmetry group. Let this number be n maximum. Consequently, there are n disoriented = N GS - n maximum cells with an orientation other than the reference. c) We define the normalization value n max_disoriented from the minimum number of cells with the reference orientation: n max_disoriented = N GS n minimum (2) where n minimum = N GS 1 int (3) d) The normalized cost associated with the disorientation of the N GS cells is given by: f orientation n disoriented N GS n maximum N GS n = = = maximum n max_disoriented N GS n minimum N GS 1 N GS int (4) Next, we define the term f form_subtree, with a normalized value in the interval [0.0, 1.0]: a) We select 2N GS -1 elements from the first element of the symmetry group appearing in 9

10 the slicing tree, and count the number of operators of each type (N oper, N operv ), the total of operators (N oper ), and the cells belonging to the symmetry group (N cells_gs ). b) We verify that the group of 2N GS -1 elements truly forms part of a subtree. The separation between both situations is reflected in n non-verified_restrictions. The largest value of nonverified restrictions is obtained when the first element is a cell and the rest are cut operators; in other words, 2N GS -2. Finally, we evaluate the following functions, f 1 = Weight 1 N cells_gs N GS + N oper ( N GS 1) (5) f 2 = n non-verified_restrictions (6) f 3 = max( N oper, N operv ) ( N GS 1) (7) and define the normalized value f form_subtree as a weighted sum of f 1, f 2, and f 3 normalized at their maximum values: (Weight 1 +1)(N GS -1), 2N GS -2, and N GS -1, respectively. f 1 1 f form_subtree = ( Weight 1 + 1) ( N GS 1) N GS N GS 1 f 2 f 3 (8) Example of Application We have demonstrated GELSA operation by applying it to the realization of the layouts of different analog cells. The following results were obtained for a 17 cells (transistors) transconductor, with five symmetry restrictions; a centroid placement for transistors 3 to 6; matching symmetry between the transistors 1 and 2, 11 and 13, and 12 and 14; and array symmetry restriction between the transistors 8 to 10. Figure 5 presents the results obtained with the following parameters: C_AREL=4.5, C_NETS=6.0, C_FF=1.5, C_BOUND=1.0, C_SIM=50.0. It shows how the symmetries are met and how the channels are properly sized. Figure 6 shows the layout obtained for the same problem but with a free form factor (C_FF=0.0). For both cases, the CPU time was 15 minutes on a Sparc IPX, 50% of which was spent in the routing estimation phase. owever, this is not significant since our efforts aimed to check the efficiency of the proposed place-and-route approach. We believe that an implementation of the algorithm more efficient in CPU time is feasible. 10

11 V cc V c V B V V ss 3 5 I 1 V 1 I Figure 5: Example of application. 15 I 2 I 1 V 1 V 2 V c V ss V B 11 Figure 6: Example of application. 12 V cc 11

12 Conclusions We have developed a tool for the automatic layout of analog cells, in which we have integrated the problems of placement and global routing under the same optimization algorithm. The routing problem is treated with a heuristic algorithm of linear complexity that enables us to obtain a good estimation of the routing for each net and to penalize the existence of noisy and sensitive nets in the same channel. The obtained results show the feasibility of the proposed algorithm. References [1] C. Sechen y A. Sangiovanni-Vicentelli, "The TimberWolf Placement and Routing Package", IEEE J. Solid-State Circuits, Vol. 20, No.2, April [2] J. Rijmenants, J. Litsios, T. Schwarz, y M. Degrauwe, "ILAC: An Automated Layout Tool for Analog CMOS Circuits", IEEE J. Solid-State Circuits, Vol. 24, No. 2, pp , April [3] D. F. Wong, y C. L. Liu, "A new algorithm for floorplan design", Proc. 23rd. Design Automation Conf., pp , June [4] D. F. Wong,. W. Leong, y C. L. Liu, "Simulated Annealing for VLSI design", Boston: Kluwer Academic, [5] R. A. Rutenbar, "Simulated Annealing Algorithms: An Overview", IEEE Circuits and Devices Magazine [6] J. Cohn, D. Garrod, R. Rutenbar, L. R. Carley, "KOAN/ANAGRAM II: New Tools for Device-Level Analog Placement and Routing", en IEEE J. Solid-State Circuits, Vol. 26, No. 3, March [7] J.A. Prieto, A. Rueda, J.M. Quintana, y J.L. uertas, "Una aproximación al problema de Layout automático de celdas analógicas", VII Congreso de Diseño de Circuitos Integrados, Toledo, [8] E. Malavasi, E. Charbon, G. Jusuf, R. Totaro and A. Sangiovanni-Vicentelli, "Virtual Symmetry Axes for the Layout of Analog IC s", in6 Proc. 2 nd ICVC, Seoul, Korea, pp , Oct