Combinational Logic Circuits


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1 Combinational Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch
2 Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory Outputs determined by previous and current values of inputs inputs functional spec timing spec outputs Digital Logic Design Ch2
3 Outlines. Introduction. 2. Combinational Circuits 3. Design Procedure Binary Adder (Half adder Full adder) Binary Subtractor (Half subtractor Full Subtractor) Binary Multiplier Magnitude Comparator Binary Decoders(2*4 Decoder 3*8 Decoder 4*6 Decoder) Binary Encoder Multiplexers (2* Multiplexer 4* Multiplexer 8* Multiplexer) Digital Logic Design Ch3
4 Introduction Combinational Circuits Output is function of input only i.e. no feedback n inputs Combinational Circuits m outputs When input changes, output may change (after a delay) Digital Logic Design Ch4
5 Analysis Given a circuit, find out its function Function may be expressed as: A B C A B C A B A C B C F F2??» Boolean function» Truth table Design Given a desired function, determine its circuit Function may be expressed as:» Boolean function» Truth table? Digital Logic Design Ch5
6 Analysis Procedure Boolean Expression Approach A B C A B C T 2 =ABC T =A+B+C F A B F 2 =(A +B )(A +C )(B +C ) A C B C F 2 F 2 =AB+AC+BC F =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC Digital Logic Design Ch6
7 Truth Table Approach A = B = C = A = B = C = A = B = A = C = B = C = B A C F F 2 A B C F F 2 B A C F =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC Digital Logic Design Ch7
8 Design Procedure Given a problem statement: Determine the number of inputs and outputs Derive the truth table Simplify the Boolean expression for each output Produce the required circuit Example: Design a circuit to convert a BCD code to Excess 3 code 4bits 9 values? 4bits Value+3 Digital Logic Design Ch8
9 BCDtoExcess 3 Converter A B C D w x y z x x x x x x x x x x x x x x x x x x x x x x x x C A x x x x x x D w = A+BC+BD C A x x x x x x D B B y = C D +CD z = D C A x x x x x x D C A x x x x x x D B x = B C+B D+BC D B Digital Logic Design Ch9
10 Design Procedure BCDtoExcess 3 Converter A B C D w x y z x x x x x x x x x x x x x x x x x x x x x x x x A B C D w = A + B(C+D) x = B (C+D) + B(C+D) y = (C+D) + CD z = D w x y z Digital Logic Design Ch
11 SevenSegment Decoder w x y z a b c d e f g x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x w x y z? BCD code y w x x x x x x z a b c d e f g a = w + y + xz + x z b =... c =... d =... x f e d a g b c Digital Logic Design Ch
12 SevenSegment Decoder A sevensegment display decoder takes a 4bit data input, D 3:, and produces seven outputs to control lightemitting diodes to display a digit from to 9. The seven outputs are often called segments a through g. Digital Logic Design Ch2
13 SevenSegment Decoder Digital Logic Design Ch3
14 SevenSegment Decoder Digital Logic Design Ch4
15 Quiz A sevensegment display decoder takes a 4bit data input, D3:, and produces seven outputs to control lightemitting diodes to display a digit from to 9. The seven outputs are often called segments a through g, or Sa Sg.The digits are shown in Figure. Write a truth table for the outputs, and use Kmaps to find Boolean equations for outputs Sa and Sb. Assume that illegal input values ( 5) produce a blank readout. Digital Logic Design Ch5
16 Ans. Digital Logic Design Ch6
17 Ans. Digital Logic Design Ch7
18 Binary Adder Binary Adder Design Steps  Construct The truth table 2 Obtain the Boolean function from Truth table 3 Minimize the Boolean Function 4 Draw the Logic Circuit to the minimized Boolean function Digital Logic Design Ch8
19 Half Adder Adds bit plus bit Produces Sum and Carry A B HA S C A B S C A + B C S A S B C Digital Logic Design Ch9
20 Full Adder Adds bit plus bit plus bit Produces Sum and Carry x y z C S y x y z FA S C x + y + z C S x z S = xy'z'+x'yz'+x'y'z+xyz = x y z y x z C = xy + xz + yz Digital Logic Design Ch2
21 Binary Adder Implementation x y z Full Adder x y z x y z x y z x y z x y x z S C S = xy'z'+x'yz'+x'y'z+xyz = x y z C = xy + xz + yz x y z x y z x y x z y z S C y z Digital Logic Design Ch2
22 Rev. Design the Binary Full adder Logic Circuit? Step Construct The Truth Table Step 2 Obtain the Boolean Function Inputs outputs A B C in S C o Step 3 Minimize each of output Boolean Functions Digital Logic Design Ch22
23 Step 4 Implement each of output minimized Boolean Function Digital Logic Design Ch23
24 Design the Binary Full adder Logic Circuit to add 4Bits A3 A2 A A B3 B2 B B + Digital Logic Design Ch24
25 Full Adder x y HA HA S z C x y S C z Digital Logic Design Ch25
26 4bits Binary Adder Implementation C y x 3 x 2 x x y 3 y 2 y y Binary Adder C Carry Propagate Addition c 3 c 2 c. + x 3 x 2 x x + y 3 y 2 y y Cy S 3 S 2 S S S 3 S 2 S S x 3 x 2 x x y 3 y 2 y y FA FA FA FA C 4 C S 3 C 3 S 2 C 2 S S Digital Logic Design Ch26
27 Carry Propagate Adder x 7 x 6 x 5 x 4 y7 y 6 y 5 y 4 x 3 x 2 x x y3 y 2 y y A 3 A 2 A A B 3 B 2 B B A 3 A 2 A A B 3 B 2 B B C y CPA C C y CPA C S 3 S 2 S S S 3 S 2 S S S 7 S 6 S 5 S 4 S 3 S 2 S S Digital Logic Design Ch27
28 BCD Adder 4bits plus 4bits Operands and Result: to 9 X +Y x 3 x 2 x x y 3 y 2 y y Sum Cy S 3 S 2 S S + = + = + 2 = 2 + x 3 x 2 x x + y 3 y 2 y y Cy S 3 S 2 S S + 9 = 9 + = + = = = A 2 + = = 2 Invalid Code Wrong BCD Value Digital Logic Design Ch28
29 X +Y x 3 x 2 x x y 3 y 2 y y Sum Cy S 3 S 2 S S Required BCD Output Value 9 + = 9 = = = = = = 2 = = 3 = = 4 = = 5 = = 6 = = 7 = = 8 = Digital Logic Design Ch29
30 BCD Adder Correct Binary Adder s Output (+6) If the result is between A and F If Cy = S 3 S 2 S S Err S S 3 S S 2 Err = S 3 S 2 + S 3 S Digital Logic Design Ch3
31 BCD Adder Implementation x 3 x 2 x x y 3 y 2 y y A 3 A 2 A A B 3 B 2 B B C y Binary Adder C i S 3 S 2 S S Err A 3 A 2 A A B 3 B 2 B B C y Binary Adder C i S 3 S 2 S S C y S 3 S 2 S S Digital Logic Design Ch3
32 Binary Subtractor The subtraction of unsigned binary numbers can be done by means of complements. As discussed Before : Remember that the subtraction A  B can be done by taking the 2 s complement of B and adding it to A. The 2 s complement can be obtained by taking the s complement and adding to the least significant pair of bits. The s complement can be implemented with inverters, and a can be added to the sum through the input carry. The circuit for subtracting A  B consists of an adder with inverters placed between each data input B and the corresponding input of the full adder. The input carry C must be equal to when subtraction is performed. Digital Logic Design Ch32
33 The Half  Subtract Circuit A, B are the Circuit Inputs D, B o are the Circuit outputs where(d is the Difference and B is the Borrow Step () Step (2) INPUTS A B OUTPUTS D B o o Step (3) Digital Logic Design Ch33
34 Digital Logic Design Ch34 The Full Subtract Circuit OUTPUTS INPUTS B o D B in B A A, B, B in are the Circuit Inputs D, B o are the Circuit outputs where(d is the Difference and B o is the Borrow Step () Step (2)
35 Full Subtract Circuit (Cont.) Step (3) B Digital Logic Design Ch35
36 Binary Multiplier Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers. The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit. Each such multiplication forms a partial product. Successive partial products are shifted one position to the left. The final product is obtained from the sum of the partial products. C = A B C = A B + A B C 2 = A B C 3 Digital Logic Design Ch36
37 Magnitude Comparator The comparison of two numbers is an operation that determines whether one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether : A > B, A = B, or A < B. Inputs (A,B) : Outputs [X(A=B), Y(A<B), Z(A>B)] Step () Digital Logic Design Ch37
38 Magnitude Comparator (Cont.) X A B AB A B Y Z AB A B Step (2) Step (3) ( A XNOR B ) Digital Logic Design Ch38
39 Decoders A Decoder has n Inputs and 2 n Output Decoder (2 to 4) Line Decoder (Has 2 inputs and 4 Outputs ) Step () Step (2) Step (3) D = A B D = AB D 2 = AB D 3 = AB Digital Logic Design Ch39
40 Binary Decoder 2to4 Line Decoder I I Y 3 Y 2 Y Y Y I Y I Y I Y I 3 I 2 I I I Y 3 Y 2 I I y 3 y 2 y y Y Y I I Digital Logic Design Ch4
41 3to8 Line Decoder Y 7 I 2 I I Y 6 I 2 I I I 2 I I Binary Decoder Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y 5 Y 4 Y 3 Y 2 Y Y I I I I I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I I 2 I I Digital Logic Design Ch4
42 I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y Y Y 2 Y 3 Y 4 Y 5 Y 6 I I I I I I I I Y 7 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I Digital Logic Design Ch42
43 Binary Decoder Design Enable Control 2 to 4 Decoder E I I Y 3 Y 2 Y Y x x Y 3 Y 2 Y Y I I E Y 3 Y 2 Y Y I I E Digital Logic Design Ch43
44 Implementation Using Decoders Each output is a minterm All minterms are produced Sum the required minterms Example: Full Adder S(x, y, z) = (, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7) S = xy'z'+x'yz'+x'y'z+xyz = x y z C = xy + xz + yz x y z Binary Decoder I 2 I I Y 7 Y I2 I I Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y Y 2 Y 3 Y 4 Y 5 Y 6 I I I I I I I Y 7 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I S C Digital Logic Design Ch44
45 Logic function using decoder Decoders can be combined with OR gates to build logic functions. Figure shows the twoinput XNOR function using a 2:4 decoder and a single OR gate. Because each output of a decoder represents a single minterm, the function is built as the OR of all the minterms in the function. Digital Logic Design Ch45
46 Encoders An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code corresponding to the input value. An example of an encoder is the octaltobinary encoder whose truth table is given in Table. It has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary number. Digital Logic Design Ch46
47 OctaltoBinary Encoder (8to3) The encoder can be implemented with three OR gates. I 7 I 6 I 5 I 4 I 3 I 2 I I Y 2 Y Y Y Y Y I 7 I 6 I 5 I 4 I 3 I 2 I I 2 I I I I I I I I I I I I 4 2 Y 2 Y Y Digital Logic Design Ch47
48 Encoder / Decoder Pairs Binary Encoder Binary Decoder I 7 I 6 I 5 I 4 I 3 I 2 I I Y 2 Y Y I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Digital Logic Design Ch48
49 Multiplexers A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2 n input lines and n selection lines whose bit combinations determine which input is selected. If S = The output (Q)= Y, If S = The output(q) = X Q = S XY + S XY + S X Y + S XY Q = S Y( X+ X) + S X( Y + Y) Q = S Y+ S X After minimization Digital Logic Design Ch49
50 Digital Logic Design Ch5
51 A twotooneline multiplexer the circuit has two data input lines, one output line, and one selection line S. When S =, the upper AND gate is enabled and The output = I the output. When S =, the lower AND gate is enabled The output = I A fourtooneline multiplexer Digital Logic Design Ch5
52 2to MUX I I I MUX S Y I Y S 4to MUX I I I I 2 MUX I 3 S S I Y I 2 I 3 Y S S Digital Logic Design Ch52
53 Q: Construct an multiplexer 8* with 2 Multiplexer 4* and additional gate Ans : Digital Logic Design Ch53
54 Q2: Construct an multiplexer 8* with 2 Multiplexer 4* and multiplexer 2*. Ans : Digital Logic Design Ch54
55 Quad 2to MUX A 3 Y 3 A 3 B 3 I I MUX Y S A 2 A A Y 2 Y Y A 2 A A B 2 B B I I I I I I MUX Y S MUX Y S MUX Y S B 3 B 2 B B S E A 3 A 2 A A B 3 B 2 B B MUX S E Y 3 Y 2 Y Y S Digital Logic Design Ch55
56 Example F(x, y) = (,, 3) Implementation Using Multiplexers x y F I I MUX Y I 2 I 3 S S x y F Digital Logic Design Ch56
57 Example F(x, y, z) = (, 2, 6, 7) x y z F I I I 2 I 3 I MUX Y 4 I 5 I 6 I 7 S 2 S S x y z F Digital Logic Design Ch57
58 Example F(x, y, z) = (, 2, 6, 7) x y z F F = z F = z F = F = z z I I MUX Y I 2 I 3 S S x y F Digital Logic Design Ch58
59 Example F(A, B, C, D) = (, 3, 4,, 2, 3, 4, 5) A B C D F F = D F = D F = D F = F = F = D F = F = D D D D I I I 2 I 3 I MUX Y 4 I 5 I 6 I 7 S 2 S S A B C F Digital Logic Design Ch59
60 HDL MODELS OF COMBINATIONAL CIRCUITS The logic of a module can be described in any one (or a combination) of the following modeling styles called The Verilog HDL:  Gatelevel modeling using instantiations of predefined and userdefined primitive gates.  Dataflow modeling using continuous assignment statements with the keyword assign.  Behavioral modeling using procedural assignment statements with the keyword always. HDL Example (RippleCarry Adder) // Description of half adder // module half_adder (S, C, x, y); // // output S, C; // input x, y; module half_adder ( output S, C, input x, y); // // Instantiate primitive gates xor (S, x, y); and (C, x, y); endmodule // Description of full adder // module full_adder (S, C, x, y, z); // output S, C; // input x, y, z; module full_adder ( output S, C, input x, y, z); wire S, C, C2; // Instantiate half adders half_adder HA (S, C, x, y); half_adder HA2 (S, C2, S, z); or G (C, C2, C); endmodule Digital Logic Design Ch6
61 HDL Example (TwotoFourLine Decoder) // Gatelevel description of twotofourline decoder // Refer to Fig. 4.9 with symbol E replaced by enable, for clarity. module decoder_2x4_gates (D, A, B, enable); output [: 3] D; input A, B; input enable; wire A_not,B_not, enable_not; not G (A_not, A), G2 (B_not, B), G3 (enable_not, enable); nand G4 (D[], A_not, B_not, enable_not), G5 (D[], A_not, B, enable_not), G6 (D[2], A, B_not, enable_not), G7 (D[3], A, B, enable_not); endmodule Digital Logic Design Ch6
62 Quiz  Design a combinational circuit with three inputs and one output. (a)* The output is when the binary value of the inputs is less than 3. The output is otherwise. (b) The output is when the binary value of the inputs is an even number. 2 Obtain the simplified Boolean expressions for output F and G in terms of the input variables in the circuit : 3 Design 3 to 8 Binary line Decoder? 4 Design a combinational circuit that converts a fourbit Gray code (Table.6) to a bit four binary number. Implement the circuit with exclusiveor gates. 5 Design a fourbit combinational circuit 2 s complementer. (The output generates the 2 s complement of the input binary number.) Show that the circuit can be constructed with exclusiveor gates. 6Using four halfadders (a) Design a fullsubtractor circuit incrementer. (A circuit that adds one to a fourbit binary number.) (b) Design a fourbit combinational decrementer (a circuit that subtracts from a four bit binary number). Digital Logic Design Ch62
63 7 For the circuit shown in Fig. Write the Boolean functions for the four outputs in terms of the input variables. Ans. Digital Logic Design Ch63
64 8 Design (a) halfsubtractor circuit with inputs x and y and outputs Diff and B out. The circuit subtracts the bits x y and places the difference in D and the borrow in B out. (b) Design a fullsubtractor circuit with three inputs x, y, B in and two outputs Diff and B out The circuit subtracts x y B in, where B in is the input borrow, B out is the output borrow, and Diff is the difference. 9 Construct a 3to8line decoder? Design Octal to Binary Encoder?  Construct a 6 multiplexer with two 8 and one 2 multiplexers? 2 Implement Octal to Hexadecimal Combinational Logic Circuit? 3 Implement the Binary Comparator Combinational logic Circuit? 4 implement the Full adder Combinational Logic Circuit? 5 Suppose we have the function Y = F(A, B, C) with the Kmap shown in Figure. Minimize the equation using the Kmap. Digital Logic Design Ch64
65 6 Draw the logic diagram of the digital circuit specified by the following Verilog description: module Circuit_A (A, B, C, D, F); input A, B, C, D; output F; wire w, x, y, z, a, d; or (x, B, C, d); and (y, a,c); and (w, z,b); and (z, y, A); or (F, x, w); not (a, A); not (d, D); Endmodule Ans Digital Logic Design Ch65
66 7 Write a Verilog gatelevel (HDL) description of the circuit shown? Digital Logic Design Ch66
67 Rev) Gray Code Gray Code The advantage is that only bit in the code group changes in going from one number to the next.» Error detection.» Representation of analog data.» Low power design.  and onto!! Digital Logic Design Ch67
68 INDEX Lecture 6 Sol: (b) Digital Logic Design Ch68
69 Sol 4 Digital Logic Design Ch69
70 Sol 4 Digital Logic Design Ch7
71 Ans 5 Digital Logic Design Ch7
72 Quiz Sol 6 Digital Logic Design Ch72
73 Ans 8 Digital Logic Design Ch73
74 Ans 9 Digital Logic Design Ch74
75 Ans. 7 (a) module Fig_3_22a_gates (F, A, B, C, C_bar, D); output F; input A, B, C, C_bar, D; wire w, w2, w3, w4; and (w, C, D); or (w2, w, B); and (w3, w2, A); and (w4, B, C_bar); or (F, w3, w4); Endmodule (b) module Fig_3_22b_gates (F, A, B, C, C_bar, D); output F; input A, B, C, C_bar, D; wire w, w2, w3, w4; not (w_bar, w); not (B_bar, B); not (w3_bar, w3); not (w4_bar, w4); nand (w, C, D); or (w2, w_bar, B_bar); nand (w3, w2, A); nand (w4, B, C_bar); or (F, w3_bar, w4_bar); endmodule Digital Logic Design Ch75
76 END Digital Logic Design Ch76
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