# Combinational Logic Circuits

Size: px
Start display at page:

Transcription

1 Combinational Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch-

2 Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory Outputs determined by previous and current values of inputs inputs functional spec timing spec outputs Digital Logic Design Ch-2

3 Outlines. Introduction. 2. Combinational Circuits 3. Design Procedure Binary Adder (Half adder Full adder) Binary Subtractor (Half subtractor Full Subtractor) Binary Multiplier Magnitude Comparator Binary Decoders(2*4 Decoder 3*8 Decoder 4*6 Decoder) Binary Encoder Multiplexers (2* Multiplexer 4* Multiplexer 8* Multiplexer) Digital Logic Design Ch-3

4 Introduction Combinational Circuits Output is function of input only i.e. no feedback n inputs Combinational Circuits m outputs When input changes, output may change (after a delay) Digital Logic Design Ch-4

5 Analysis Given a circuit, find out its function Function may be expressed as: A B C A B C A B A C B C F F2??» Boolean function» Truth table Design Given a desired function, determine its circuit Function may be expressed as:» Boolean function» Truth table? Digital Logic Design Ch-5

6 Analysis Procedure Boolean Expression Approach A B C A B C T 2 =ABC T =A+B+C F A B F 2 =(A +B )(A +C )(B +C ) A C B C F 2 F 2 =AB+AC+BC F =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC Digital Logic Design Ch-6

7 Truth Table Approach A = B = C = A = B = C = A = B = A = C = B = C = B A C F F 2 A B C F F 2 B A C F =AB'C'+A'BC'+A'B'C+ABC F 2 =AB+AC+BC Digital Logic Design Ch-7

8 Design Procedure Given a problem statement: Determine the number of inputs and outputs Derive the truth table Simplify the Boolean expression for each output Produce the required circuit Example: Design a circuit to convert a BCD code to Excess 3 code 4-bits -9 values? 4-bits Value+3 Digital Logic Design Ch-8

9 BCD-to-Excess 3 Converter A B C D w x y z x x x x x x x x x x x x x x x x x x x x x x x x C A x x x x x x D w = A+BC+BD C A x x x x x x D B B y = C D +CD z = D C A x x x x x x D C A x x x x x x D B x = B C+B D+BC D B Digital Logic Design Ch-9

10 Design Procedure BCD-to-Excess 3 Converter A B C D w x y z x x x x x x x x x x x x x x x x x x x x x x x x A B C D w = A + B(C+D) x = B (C+D) + B(C+D) y = (C+D) + CD z = D w x y z Digital Logic Design Ch-

11 Seven-Segment Decoder w x y z a b c d e f g x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x w x y z? BCD code y w x x x x x x z a b c d e f g a = w + y + xz + x z b =... c =... d =... x f e d a g b c Digital Logic Design Ch-

12 Seven-Segment Decoder A seven-segment display decoder takes a 4-bit data input, D 3:, and produces seven outputs to control light-emitting diodes to display a digit from to 9. The seven outputs are often called segments a through g. Digital Logic Design Ch-2

13 Seven-Segment Decoder Digital Logic Design Ch-3

14 Seven-Segment Decoder Digital Logic Design Ch-4

15 Quiz A seven-segment display decoder takes a 4-bit data input, D3:, and produces seven outputs to control light-emitting diodes to display a digit from to 9. The seven outputs are often called segments a through g, or Sa Sg.The digits are shown in Figure. Write a truth table for the outputs, and use K-maps to find Boolean equations for outputs Sa and Sb. Assume that illegal input values ( 5) produce a blank readout. Digital Logic Design Ch-5

16 Ans. Digital Logic Design Ch-6

17 Ans. Digital Logic Design Ch-7

18 Binary Adder Binary Adder Design Steps - Construct The truth table 2- Obtain the Boolean function from Truth table 3- Minimize the Boolean Function 4- Draw the Logic Circuit to the minimized Boolean function Digital Logic Design Ch-8

19 Half Adder Adds -bit plus -bit Produces Sum and Carry A B HA S C A B S C A + B C S A S B C Digital Logic Design Ch-9

20 Full Adder Adds -bit plus -bit plus -bit Produces Sum and Carry x y z C S y x y z FA S C x + y + z C S x z S = xy'z'+x'yz'+x'y'z+xyz = x y z y x z C = xy + xz + yz Digital Logic Design Ch-2

21 Binary Adder Implementation x y z Full Adder x y z x y z x y z x y z x y x z S C S = xy'z'+x'yz'+x'y'z+xyz = x y z C = xy + xz + yz x y z x y z x y x z y z S C y z Digital Logic Design Ch-2

22 Rev. Design the Binary Full adder Logic Circuit? Step Construct The Truth Table Step 2 Obtain the Boolean Function Inputs outputs A B C in S C o Step 3 Minimize each of output Boolean Functions Digital Logic Design Ch-22

23 Step 4 Implement each of output minimized Boolean Function Digital Logic Design Ch-23

24 Design the Binary Full adder Logic Circuit to add 4-Bits A3 A2 A A B3 B2 B B + Digital Logic Design Ch-24

25 Full Adder x y HA HA S z C x y S C z Digital Logic Design Ch-25

26 4-bits Binary Adder Implementation C y x 3 x 2 x x y 3 y 2 y y Binary Adder C Carry Propagate Addition c 3 c 2 c. + x 3 x 2 x x + y 3 y 2 y y Cy S 3 S 2 S S S 3 S 2 S S x 3 x 2 x x y 3 y 2 y y FA FA FA FA C 4 C S 3 C 3 S 2 C 2 S S Digital Logic Design Ch-26

27 Carry Propagate Adder x 7 x 6 x 5 x 4 y7 y 6 y 5 y 4 x 3 x 2 x x y3 y 2 y y A 3 A 2 A A B 3 B 2 B B A 3 A 2 A A B 3 B 2 B B C y CPA C C y CPA C S 3 S 2 S S S 3 S 2 S S S 7 S 6 S 5 S 4 S 3 S 2 S S Digital Logic Design Ch-27

28 BCD Adder 4-bits plus 4-bits Operands and Result: to 9 X +Y x 3 x 2 x x y 3 y 2 y y Sum Cy S 3 S 2 S S + = + = + 2 = 2 + x 3 x 2 x x + y 3 y 2 y y Cy S 3 S 2 S S + 9 = 9 + = + = = = A 2 + = = 2 Invalid Code Wrong BCD Value Digital Logic Design Ch-28

29 X +Y x 3 x 2 x x y 3 y 2 y y Sum Cy S 3 S 2 S S Required BCD Output Value 9 + = 9 = = = = = = 2 = = 3 = = 4 = = 5 = = 6 = = 7 = = 8 = Digital Logic Design Ch-29

30 BCD Adder Correct Binary Adder s Output (+6) If the result is between A and F If Cy = S 3 S 2 S S Err S S 3 S S 2 Err = S 3 S 2 + S 3 S Digital Logic Design Ch-3

31 BCD Adder Implementation x 3 x 2 x x y 3 y 2 y y A 3 A 2 A A B 3 B 2 B B C y Binary Adder C i S 3 S 2 S S Err A 3 A 2 A A B 3 B 2 B B C y Binary Adder C i S 3 S 2 S S C y S 3 S 2 S S Digital Logic Design Ch-3

32 Binary Subtractor The subtraction of unsigned binary numbers can be done by means of complements. As discussed Before : Remember that the subtraction A - B can be done by taking the 2 s complement of B and adding it to A. The 2 s complement can be obtained by taking the s complement and adding to the least significant pair of bits. The s complement can be implemented with inverters, and a can be added to the sum through the input carry. The circuit for subtracting A - B consists of an adder with inverters placed between each data input B and the corresponding input of the full adder. The input carry C must be equal to when subtraction is performed. Digital Logic Design Ch-32

33 The Half - Subtract Circuit A, B are the Circuit Inputs D, B o are the Circuit outputs where(d is the Difference and B is the Borrow Step () Step (2) INPUTS A B OUTPUTS D B o o Step (3) Digital Logic Design Ch-33

34 Digital Logic Design Ch-34 The Full- Subtract Circuit OUTPUTS INPUTS B o D B in B A A, B, B in are the Circuit Inputs D, B o are the Circuit outputs where(d is the Difference and B o is the Borrow Step () Step (2)

35 Full Subtract Circuit (Cont.) Step (3) B Digital Logic Design Ch-35

36 Binary Multiplier Multiplication of binary numbers is performed in the same way as multiplication of decimal numbers. The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit. Each such multiplication forms a partial product. Successive partial products are shifted one position to the left. The final product is obtained from the sum of the partial products. C = A B C = A B + A B C 2 = A B C 3 Digital Logic Design Ch-36

37 Magnitude Comparator The comparison of two numbers is an operation that determines whether one number is greater than, less than, or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether : A > B, A = B, or A < B. Inputs (A,B) : Outputs [X(A=B), Y(A<B), Z(A>B)] Step () Digital Logic Design Ch-37

38 Magnitude Comparator (Cont.) X A B AB A B Y Z AB A B Step (2) Step (3) ( A XNOR B ) Digital Logic Design Ch-38

39 Decoders A Decoder has n Inputs and 2 n Output Decoder (2 to 4) Line Decoder (Has 2 inputs and 4 Outputs ) Step () Step (2) Step (3) D = A B D = AB D 2 = AB D 3 = AB Digital Logic Design Ch-39

40 Binary Decoder 2-to-4 Line Decoder I I Y 3 Y 2 Y Y Y I Y I Y I Y I 3 I 2 I I I Y 3 Y 2 I I y 3 y 2 y y Y Y I I Digital Logic Design Ch-4

41 3-to-8 Line Decoder Y 7 I 2 I I Y 6 I 2 I I I 2 I I Binary Decoder Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y 5 Y 4 Y 3 Y 2 Y Y I I I I I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I I 2 I I Digital Logic Design Ch-4

42 I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y Y Y 2 Y 3 Y 4 Y 5 Y 6 I I I I I I I I Y 7 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I Digital Logic Design Ch-42

43 Binary Decoder Design Enable Control 2 to 4 Decoder E I I Y 3 Y 2 Y Y x x Y 3 Y 2 Y Y I I E Y 3 Y 2 Y Y I I E Digital Logic Design Ch-43

44 Implementation Using Decoders Each output is a minterm All minterms are produced Sum the required minterms Example: Full Adder S(x, y, z) = (, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7) S = xy'z'+x'yz'+x'y'z+xyz = x y z C = xy + xz + yz x y z Binary Decoder I 2 I I Y 7 Y I2 I I Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Y Y 2 Y 3 Y 4 Y 5 Y 6 I I I I I I I Y 7 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I 2 I I S C Digital Logic Design Ch-44

45 Logic function using decoder Decoders can be combined with OR gates to build logic functions. Figure shows the twoinput XNOR function using a 2:4 decoder and a single OR gate. Because each output of a decoder represents a single minterm, the function is built as the OR of all the minterms in the function. Digital Logic Design Ch-45

46 Encoders An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code corresponding to the input value. An example of an encoder is the octal-to-binary encoder whose truth table is given in Table. It has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary number. Digital Logic Design Ch-46

47 Octal-to-Binary Encoder (8-to-3) The encoder can be implemented with three OR gates. I 7 I 6 I 5 I 4 I 3 I 2 I I Y 2 Y Y Y Y Y I 7 I 6 I 5 I 4 I 3 I 2 I I 2 I I I I I I I I I I I I 4 2 Y 2 Y Y Digital Logic Design Ch-47

48 Encoder / Decoder Pairs Binary Encoder Binary Decoder I 7 I 6 I 5 I 4 I 3 I 2 I I Y 2 Y Y I 2 I I Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y Y Digital Logic Design Ch-48

49 Multiplexers A multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally, there are 2 n input lines and n selection lines whose bit combinations determine which input is selected. If S = The output (Q)= Y, If S = The output(q) = X Q = S XY + S XY + S X Y + S XY Q = S Y( X+ X) + S X( Y + Y) Q = S Y+ S X After minimization Digital Logic Design Ch-49

50 Digital Logic Design Ch-5

51 A two-to-one-line multiplexer the circuit has two data input lines, one output line, and one selection line S. When S =, the upper AND gate is enabled and The output = I the output. When S =, the lower AND gate is enabled The output = I A four-to-one-line multiplexer Digital Logic Design Ch-5

52 2-to- MUX I I I MUX S Y I Y S 4-to- MUX I I I I 2 MUX I 3 S S I Y I 2 I 3 Y S S Digital Logic Design Ch-52

53 Q: Construct an multiplexer 8* with 2 Multiplexer 4* and additional gate Ans : Digital Logic Design Ch-53

54 Q2: Construct an multiplexer 8* with 2 Multiplexer 4* and multiplexer 2*. Ans : Digital Logic Design Ch-54

55 Quad 2-to- MUX A 3 Y 3 A 3 B 3 I I MUX Y S A 2 A A Y 2 Y Y A 2 A A B 2 B B I I I I I I MUX Y S MUX Y S MUX Y S B 3 B 2 B B S E A 3 A 2 A A B 3 B 2 B B MUX S E Y 3 Y 2 Y Y S Digital Logic Design Ch-55

56 Example F(x, y) = (,, 3) Implementation Using Multiplexers x y F I I MUX Y I 2 I 3 S S x y F Digital Logic Design Ch-56

57 Example F(x, y, z) = (, 2, 6, 7) x y z F I I I 2 I 3 I MUX Y 4 I 5 I 6 I 7 S 2 S S x y z F Digital Logic Design Ch-57

58 Example F(x, y, z) = (, 2, 6, 7) x y z F F = z F = z F = F = z z I I MUX Y I 2 I 3 S S x y F Digital Logic Design Ch-58

59 Example F(A, B, C, D) = (, 3, 4,, 2, 3, 4, 5) A B C D F F = D F = D F = D F = F = F = D F = F = D D D D I I I 2 I 3 I MUX Y 4 I 5 I 6 I 7 S 2 S S A B C F Digital Logic Design Ch-59

60 HDL MODELS OF COMBINATIONAL CIRCUITS The logic of a module can be described in any one (or a combination) of the following modeling styles called The Verilog HDL: - Gate-level modeling using instantiations of predefined and user-defined primitive gates. - Dataflow modeling using continuous assignment statements with the keyword assign. - Behavioral modeling using procedural assignment statements with the keyword always. HDL Example (Ripple-Carry Adder) // Description of half adder // module half_adder (S, C, x, y); // // output S, C; // input x, y; module half_adder ( output S, C, input x, y); // // Instantiate primitive gates xor (S, x, y); and (C, x, y); endmodule // Description of full adder // module full_adder (S, C, x, y, z); // output S, C; // input x, y, z; module full_adder ( output S, C, input x, y, z); wire S, C, C2; // Instantiate half adders half_adder HA (S, C, x, y); half_adder HA2 (S, C2, S, z); or G (C, C2, C); endmodule Digital Logic Design Ch-6

61 HDL Example (Two-to-Four-Line Decoder) // Gate-level description of two-to-four-line decoder // Refer to Fig. 4.9 with symbol E replaced by enable, for clarity. module decoder_2x4_gates (D, A, B, enable); output [: 3] D; input A, B; input enable; wire A_not,B_not, enable_not; not G (A_not, A), G2 (B_not, B), G3 (enable_not, enable); nand G4 (D[], A_not, B_not, enable_not), G5 (D[], A_not, B, enable_not), G6 (D[2], A, B_not, enable_not), G7 (D[3], A, B, enable_not); endmodule Digital Logic Design Ch-6

62 Quiz - Design a combinational circuit with three inputs and one output. (a)* The output is when the binary value of the inputs is less than 3. The output is otherwise. (b) The output is when the binary value of the inputs is an even number. 2- Obtain the simplified Boolean expressions for output F and G in terms of the input variables in the circuit : 3- Design 3 to 8 Binary line Decoder? 4- Design a combinational circuit that converts a four-bit Gray code (Table.6) to a bit four binary number. Implement the circuit with exclusive-or gates. 5- Design a four-bit combinational circuit 2 s complementer. (The output generates the 2 s complement of the input binary number.) Show that the circuit can be constructed with exclusive-or gates. 6-Using four half-adders (a) Design a full-subtractor circuit incrementer. (A circuit that adds one to a four-bit binary number.) (b) Design a four-bit combinational decrementer (a circuit that subtracts from a four bit binary number). Digital Logic Design Ch-62

63 7- For the circuit shown in Fig. Write the Boolean functions for the four outputs in terms of the input variables. Ans. Digital Logic Design Ch-63

64 8- Design (a) half-subtractor circuit with inputs x and y and outputs Diff and B out. The circuit subtracts the bits x y and places the difference in D and the borrow in B out. (b) Design a full-subtractor circuit with three inputs x, y, B in and two outputs Diff and B out The circuit subtracts x y B in, where B in is the input borrow, B out is the output borrow, and Diff is the difference. 9- Construct a 3-to-8-line decoder? Design Octal to Binary Encoder? - Construct a 6 multiplexer with two 8 and one 2 multiplexers? 2- Implement Octal to Hexadecimal Combinational Logic Circuit? 3- Implement the Binary Comparator Combinational logic Circuit? 4- implement the Full adder Combinational Logic Circuit? 5- Suppose we have the function Y = F(A, B, C) with the K-map shown in Figure. Minimize the equation using the K-map. Digital Logic Design Ch-64

65 6 Draw the logic diagram of the digital circuit specified by the following Verilog description: module Circuit_A (A, B, C, D, F); input A, B, C, D; output F; wire w, x, y, z, a, d; or (x, B, C, d); and (y, a,c); and (w, z,b); and (z, y, A); or (F, x, w); not (a, A); not (d, D); Endmodule Ans Digital Logic Design Ch-65

66 7- Write a Verilog gate-level (HDL) description of the circuit shown? Digital Logic Design Ch-66

67 Rev) Gray Code Gray Code The advantage is that only bit in the code group changes in going from one number to the next.» Error detection.» Representation of analog data.» Low power design. - and onto!! Digital Logic Design Ch-67

68 INDEX Lecture 6 Sol: (b) Digital Logic Design Ch-68

69 Sol- 4 Digital Logic Design Ch-69

70 Sol- 4 Digital Logic Design Ch-7

71 Ans 5 Digital Logic Design Ch-7

72 Quiz Sol 6 Digital Logic Design Ch-72

73 Ans 8 Digital Logic Design Ch-73

74 Ans 9 Digital Logic Design Ch-74

75 Ans. 7 (a) module Fig_3_22a_gates (F, A, B, C, C_bar, D); output F; input A, B, C, C_bar, D; wire w, w2, w3, w4; and (w, C, D); or (w2, w, B); and (w3, w2, A); and (w4, B, C_bar); or (F, w3, w4); Endmodule (b) module Fig_3_22b_gates (F, A, B, C, C_bar, D); output F; input A, B, C, C_bar, D; wire w, w2, w3, w4; not (w_bar, w); not (B_bar, B); not (w3_bar, w3); not (w4_bar, w4); nand (w, C, D); or (w2, w_bar, B_bar); nand (w3, w2, A); nand (w4, B, C_bar); or (F, w3_bar, w4_bar); endmodule Digital Logic Design Ch-75

76 END Digital Logic Design Ch-76

### Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93

Combinational Logic Prof. Wangrok Oh Dept. of Information Communications Eng. Chungnam National University Prof. Wangrok Oh(CNU) / 93 Overview Introduction 2 Combinational Circuits 3 Analysis Procedure

### EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output

### Combinational Circuits

Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables

### Combinational Logic II

Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

### Chap.3 3. Chap reduces the complexity required to represent the schematic diagram of a circuit Library

3.1 Combinational Circuits 2 Chap 3. logic circuits for digital systems: combinational vs sequential Combinational Logic Design Combinational Circuit (Chap 3) outputs are determined by the present applied

UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination

### Chapter 4. Combinational Logic

Chapter 4. Combinational Logic Tong In Oh 1 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential

### DLD VIDYA SAGAR P. potharajuvidyasagar.wordpress.com. Vignana Bharathi Institute of Technology UNIT 3 DLD P VIDYA SAGAR

DLD UNIT III Combinational Circuits (CC), Analysis procedure, Design Procedure, Combinational circuit for different code converters and other problems, Binary Adder- Subtractor, Decimal Adder, Binary Multiplier,

### 1. Mark the correct statement(s)

1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

### COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

### END-TERM EXAMINATION

(Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

### Objectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure

Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification:

### SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech

### R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What

### CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...

### LOGIC CIRCUITS. Kirti P_Didital Design 1

LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists

### Injntu.com Injntu.com Injntu.com R16

1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

### R10. II B. Tech I Semester, Supplementary Examinations, May

SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

### Chapter 3. Gate-Level Minimization. Outlines

Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

### Code No: R Set No. 1

Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

### Chapter 3 Part 2 Combinational Logic Design

University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 3 Part 2 Combinational Logic Design Originals by: Charles R. Kime and Tom

### NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-II COMBINATIONAL CIRCUITS

NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203

### SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented

### QUESTION BANK FOR TEST

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

### KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

### VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

### Combinational Logic with MSI and LSI

1010101010101010101010101010101010101010101010101010101010101010101010101010101010 1010101010101010101010101010101010101010101010101010101010101010101010101010101010 1010101010101010101010101010101010101010101010101010101010101010101010101010101010

### NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 2 COMBINATIONAL LOGIC Combinational circuits Analysis

www.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL

### Gate Level Minimization

Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =

### Gate-Level Minimization

MEC520 디지털공학 Gate-Level Minimization Jee-Hwan Ryu School of Mechanical Engineering Gate-Level Minimization-The Map Method Truth table is unique Many different algebraic expression Boolean expressions may

### Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.

Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:15--8:3PM 1. (15 points) (a) (5 points) NAND, NOR

### Gate-Level Minimization

Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

### Chapter 4: Combinational Logic

Chapter 4: Combinational Logic Combinational Circuit Design Analysis Procedure (Find out nature of O/P) Boolean Expression Approach Truth Table Approach Design Procedure Example : BCD to Excess-3 code

### ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two Solutions 26 February 2014

Problem 1 (4 parts, 21 points) Encoders and Pass Gates Part A (8 points) Suppose the circuit below has the following input priority: I 1 > I 3 > I 0 > I 2. Complete the truth table by filling in the input

28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28

### SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA

### Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register

### Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019

### BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book

BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write

### CS/COE 0447 Example Problems for Exam 2 Spring 2011

CS/COE 0447 Example Problems for Exam 2 Spring 2011 1) Show the steps to multiply the 4-bit numbers 3 and 5 with the fast shift-add multipler. Use the table below. List the multiplicand (M) and product

### that system. weighted value associated with it. numbers. a number. the absence of a signal. MECH 1500 Quiz 2 Review Name: Class: Date:

Name: Class: Date: MECH 1500 Quiz 2 Review True/False Indicate whether the statement is true or false. 1. The decimal system uses the number 9 as its base. 2. All digital computing devices perform operations

### Design Using Verilog

EGC220 Design Using Verilog Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Basic Verilog Lexical Convention Lexical convention are close to C++. Comment // to the of the line. /* to

### Arithmetic Circuits. Nurul Hazlina Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit

Nurul Hazlina 1 1. Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit Nurul Hazlina 2 Introduction 1. Digital circuits are frequently used for arithmetic operations 2. Fundamental

### UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT

UNIT-III 1 KNREDDY UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT Register Transfer: Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Micro operations Logic

### Chapter 4. Combinational Logic. Dr. Abu-Arqoub

Chapter 4 Combinational Logic Introduction N Input Variables Combinational Logic Circuit M Output Variables 2 Design Procedure The problem is stated 2 The number of available input variables & required

### Experiment 4 Boolean Functions Implementation

Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.

### 60-265: Winter ANSWERS Exercise 4 Combinational Circuit Design

60-265: Winter 2010 Computer Architecture I: Digital Design ANSWERS Exercise 4 Combinational Circuit Design Question 1. One-bit Comparator [ 1 mark ] Consider two 1-bit inputs, A and B. If we assume that

### UNIT- V COMBINATIONAL LOGIC DESIGN

UNIT- V COMBINATIONAL LOGIC DESIGN NOTE: This is UNIT-V in JNTUK and UNIT-III and HALF PART OF UNIT-IV in JNTUA SYLLABUS (JNTUK)UNIT-V: Combinational Logic Design: Adders & Subtractors, Ripple Adder, Look

### Code No: 07A3EC03 Set No. 1

Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,

### Computer Architecture and Organization: L04: Micro-operations

Computer Architecture and Organization: L4: Micro-operations By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com, hafez@research.iiit.ac.in 1 Outlines 1. Arithmetic microoperation 2.

### Chapter Three. Digital Components

Chapter Three 3.1. Combinational Circuit A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. The binary values of the outputs are a function of the binary

### CS8803: Advanced Digital Design for Embedded Hardware

CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

### Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying

### ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two 26 February 2014

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### Verilog for Combinational Circuits

Verilog for Combinational Circuits Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2014 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/

### Combinational Circuit Design

Modeling Combinational Circuits with Verilog Prof. Chien-Nan Liu TEL: 3-42275 ext:34534 Email: jimmy@ee.ncu.edu.tw 3- Combinational Circuit Design Outputs are functions of inputs inputs Combinational Circuit

### R07

www..com www..com SET - 1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions

### Gate Level Minimization Map Method

Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically

### CENG 241 Digital Design 1

CENG 241 Digital Design 1 Lecture 5 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Lab Review of last lecture: Gate-Level Minimization Continue Chapter 3:XOR functions, Hardware Description Language

### EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS

EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,

### ECEN 468 Advanced Logic Design

ECEN 468 Advanced Logic Design Lecture 26: Verilog Operators ECEN 468 Lecture 26 Operators Operator Number of Operands Result Arithmetic 2 Binary word Bitwise 2 Binary word Reduction 1 Bit Logical 2 Boolean

### HDL for Combinational Circuits. ENEL211 Digital Technology

HDL for Combinational Circuits ENEL211 Digital Technology Lecture Outline Vectors Modular design Tri-state gates Dataflow modelling Behavioural Modelling Vectors Often we want multi-bit quantities in digital

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019

### ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

### DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many

### INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester

### SWITCHING THEORY AND LOGIC CIRCUITS

SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra

### Microcomputers. Outline. Number Systems and Digital Logic Review

Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded

### *Instruction Matters: Purdue Academic Course Transformation. Introduction to Digital System Design. Module 4 Arithmetic and Computer Logic Circuits

Purdue IM:PACT* Fall 2018 Edition *Instruction Matters: Purdue Academic Course Transformation Introduction to Digital System Design Module 4 Arithmetic and Computer Logic Circuits Glossary of Common Terms

### HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)

### DIGITAL ELECTRONICS. Vayu Education of India

DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education

### Register Transfer Language and Microoperations (Part 2)

Register Transfer Language and Microoperations (Part 2) Adapted by Dr. Adel Ammar Computer Organization 1 MICROOPERATIONS Computer system microoperations are of four types: Register transfer microoperations

### Scheme G. Sample Test Paper-I

Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable

### DIGITAL ELECTRONICS. P41l 3 HOURS

UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

### VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN

### COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

### Department of Computer Science & Engineering. Lab Manual DIGITAL LAB. Class: 2nd yr, 3rd sem SYLLABUS

Department of Computer Science & Engineering Lab Manual 435 DIGITAL LAB Class: 2nd yr, 3rd sem SYLLABUS. Verification of Boolean theorems using digital logic gates. 2. Design and implementation of code

### IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

### Gate-Level Minimization

Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

### UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable

### Contents. Appendix D Verilog Summary Page 1 of 16

Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3

### NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary

### Experiment 7 Arithmetic Circuits Design and Implementation

Experiment 7 Arithmetic Circuits Design and Implementation Introduction: Addition is just what you would expect in computers. Digits are added bit by bit from right to left, with carries passed to the

### Introduction to Verilog. Garrison W. Greenwood, Ph.D, P.E.

Introduction to Verilog Garrison W. Greenwood, Ph.D, P.E. November 11, 2002 1 Digital Design Flow Specification Functional Design Register Transfer Level Design Circuit Design Physical Layout Production

### Area Efficient, Low Power Array Multiplier for Signed and Unsigned Number. Chapter 3

Area Efficient, Low Power Array Multiplier for Signed and Unsigned Number Chapter 3 Area Efficient, Low Power Array Multiplier for Signed and Unsigned Number Chapter 3 3.1 Introduction The various sections

### ECE 2030D Computer Engineering Spring problems, 5 pages Exam Two 8 March 2012

Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate

### Lecture 6: Signed Numbers & Arithmetic Circuits. BCD (Binary Coded Decimal) Points Addressed in this Lecture

Points ddressed in this Lecture Lecture 6: Signed Numbers rithmetic Circuits Professor Peter Cheung Department of EEE, Imperial College London (Floyd 2.5-2.7, 6.1-6.7) (Tocci 6.1-6.11, 9.1-9.2, 9.4) Representing

### Digital Design. Verilo. and. Fundamentals. fit HDL. Joseph Cavanagh. CRC Press Taylor & Francis Group Boca Raton London New York

Digital Design and Verilo fit HDL Fundamentals Joseph Cavanagh Santa Clara University California, USA CRC Press Taylor & Francis Group Boca Raton London New York CRC Press is an imprint of the Taylor &

### 3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0

1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog

### BINARY SYSTEM. Binary system is used in digital systems because it is:

CHAPTER 2 CHAPTER CONTENTS 2.1 Binary System 2.2 Binary Arithmetic Operation 2.3 Signed & Unsigned Numbers 2.4 Arithmetic Operations of Signed Numbers 2.5 Hexadecimal Number System 2.6 Octal Number System

Get Free notes at Module-I One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)

### Tutorial on Verilog HDL

Tutorial on Verilog HDL HDL Hardware Description Languages Widely used in logic design Verilog and VHDL Describe hardware using code Document logic functions Simulate logic before building Synthesize code