# Synthesis 1. 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1

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1 Synthesis 1 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1

2 Introduction Logic synthesis is automatic generation of circuitry starting from bit-level descriptions. Behaviour of circuit is usually specified in Verilog or VHDL. Logic synthesis has two parts 1. Converting a behavioural (or algorithmic) description to a structural description. This is called High-level synthesis 2. The sub-optimal logic obtained from high-level synthesis is optimized High-level synthesis is beyond this course. We shall focus on minimizing circuit logic. Typeset by FoilTEX 2

3 Problem description Consider a boolean function f : B m B n m is the number of inputs n is the number of outputs B = { 0, 1 } This does not have don t cares. Including them we have f : B m Y n Y = { 0, 1, d } B m can be subdivided into on-set, off-set, dc-set on-set all elements in B m for which f is 1 off-set all elements in B m for which f is 0 dc-set all elements in B m for which f is d Example of elements in B 3 are (0, 1, 0), (0, 0, 0), (1, 1, 0),... etc. Typeset by FoilTEX 3

4 Problem description Consider the term. This can be shown on a cube. x 2 (a) (b) (c) The term is an example of a minterm. Each variable or its complement is called a literal. If a term has m distinct literals, it is called a minterm., are not minterms. These are called cubes. Any function f can be specified by a sum of minterms (also called sum of products) eg. f = Typeset by FoilTEX 4

5 Problem description f = This function can be represented on a cube as shown (a) (b) (c) The sum of minterms is a canonical form and is unique. This is used as a base reference for comparison later. Storing the canonical representation is an issue as it has 2 m minterms for m inputs. To minimize logic, think in terms of cubes. If a cube has at least one point in the on-set or dc-set it is called an implicant. An implicant not in any other implicant is called a prime implicants. Logic optimization is reduction of the function f to its prime implicants. This is what Karnaugh maps do. Typeset by FoilTEX 5

6 Logic Minimization- Quine McCluskey algorithm y = ā b c d + āb cd + ābcd + a b c d + a b cd + a bc d + a bcd + abc d + abcd Decimal Binary abcd Minterm ā b c d āb cd ābcd a b c d a b cd a bc d a bcd abc d abcd 0, 8 X000 A 5, 7 01X1 B 7, 15 X111 C 8, 9 100X 9, 11 10X1 10, X 10, 14 1X10 14, X 8,9 10,11 10XX D 10,11 14,15 1X1X E Typeset by FoilTEX 6

7 Quine McCluskey - Prime Implicants Minterm A B C D E X000 01X1 X111 10XX 1X1X C is redundant. y = b c d + ābd + a b + ac Typeset by FoilTEX 7

8 Concept of Restriction Binary decision diagrams f xi substitute 1 for x i in f(,,..., x n ). i.e. f xi = f(,,..., 1,..., x n ) Similarly, f xi = f(,,..., 0,..., x n ) These are positive and negative cofactors. Here we are restricting x i to certain values. Now f = x i f xi + x i f xi Note that this can be applied recursively throughout until logic 1 or 0 is left as a cofactor. Typeset by FoilTEX 8

9 Example f = f = f x1 + f x1 f x1 = + + f x1 = + + f = ( + + ) + ( + + ) = ( ( + ) + ( )) + ( ( ) + ( + )) = ( ( 1 + 1) + ( 1 + 0))+ ( ( 0 + 1) + ( 1 + 1)) Typeset by FoilTEX 9

10 Example f = This is an OBDD (Ordered Binary Decision Diagram). Dotted path represents positive cofactors; solid line path represents negative cofactors. Root vertex has no edges incident on it and leaf vertices have no edges diverging from them. A set of terminations will change an OBDD to an ROBDD (Reduced Ordered Binary Decision Diagram) Typeset by FoilTEX 10

11 ROBDD Transformations 1. Replace all identical leaf vertices with one vertex and redirect all edges to the new vertex 2. Process vertices from top to bottom. If two vertices are identical and their subtrees are identical. Remove one of them and redirect the connection of one to the other. 3. If a vertex has the same positive and negative cofactors, the vertex is redundant. Remove the vertex and connect directly to the child vertex. Implementation of these steps on an OBDD gives an ROBDD. Typeset by FoilTEX 11

12 Example 0 1 (a) 0 1 (b) 0 1 (c) Typeset by FoilTEX 12

13 ROBDDs Size of an ROBDD is based on the ordering we choose. chosen, and. As an exercise try, and. In this case we have eg. f = ( )( x 4 ) x 4 x 4 x 4 x (a) (b) To minimize the size of an ROBDD, we have to try all combinations of ordering. This is an NP-complete problem. For a given ordering an ROBDD is unique for a given function. It can thus be used as a canonical form to compare. Typeset by FoilTEX 13

14 ROBDDs can be ordered in two ways ROBDDs 1. Static 2. Dynamic A suite of methods are available to decide before generating an ROBDD to estimate what might be the best ordering. These are usually not helpful since often the expressions are changed; variables are removed and added. Dynamic methods are also present to determine the best order for the ROBDD dynamically. They are based on the fact that Swapping two adjacent vertices in the ROBDD introduces only local changes Typeset by FoilTEX 14

15 Example v a v a v a v a x k x l x k x l x l x l x k x k x l x l x k v b v c v d v e v b v d v c v e v b v c v d v b v d v c (a) (b) Typeset by FoilTEX 15

16 Heuristics for minimizing ROBDDs Brute force method 1. Select a variable and move through all points that can be taken. 2. Find the position where it can give minimum size. 3. Fix its position; pick another variable and repeat from step Iterate till all variables are assigned positions This will not give you the best ordering but something to work with. Note: Smallest ROBDD does not mean minimum logic. Complex methods exist that try to minimize logic. For example: f = x i f 1 + x i f 0 + f d Typeset by FoilTEX 16

17 f 0 f xi ; f 1 f xi ; f d f xi f xi This algorithm tries to find a solution such that f d is largest. Details of these methods will not be covered. Typeset by FoilTEX 17

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