GateLevel Minimization


 Eleanor Anna Poole
 3 years ago
 Views:
Transcription
1 GateLevel Minimization Mano & Ciletti Chapter 3 By Suleyman TOSUN Ankara University
2 Outline Intro to GateLevel Minimization The Map Method variable map methods ProductofSums Method Don t care Conditions NAND and NOR Implementations
3 GateLevel Minimization Finding an optimal gatelevel implementation of Boolean functions. Difficult to perform manually. Can use computerbased logic synthesis tool Exp: espresso logic minimization software Karnough Map (Kmap) can be used for manual design of digital circuits.
4 The Map Method The truth table representation of a function is unique. But, not the algebraic expression Several versions of an algebraic expression exist. Difficult to minimize algebraic functions manually. The map method is a simple proceure to minimize Boolean functions. Pictorial form of a truth table. Called Karnough Map or KMap.
5 TwoVariable Map Four Minterms Two variables Four squares for four minterms Figure b shows the relationship between the squares and the variables x and y.
6 TwoVariable Map (Cont.) May only be useful to represent 16 Boolean functions. Exp: If m1=m2=m3=1 then m1+m2+m3=x y+xy +xy=x+y (OR function)
7 ThreeVariable Map There are 8 minterms for 3 variables. So, there are 8 squares. Minterms are arranged not in a binary sequence, but in sequence similar to the Gray code.
8 ThreeVariable Map (Cont.) The square for square m5 corresponds to row 1 and column 01 (101). Another look to m5 is m5=xy z. When variables are 0, they are primed (ex: x ). Otherwise not primed (x).
9 ThreeVariable Map (Cont.) Two adjacent squares differs one variable (one primed other is not). So, they can be minimized Ex: m5+m7=xy z+xyz=xz(y +y)=xz So, try to cover as many adjacent squares as possible by the orders of two. 1,2,4,8 squares that has the logical value1.
10 Example 1 Simplfy the Boolean function F(x,y,z)=Σ(2,3,4,5) F(x,y,z)=x y+xy
11 Adjacent squares Some adjacent squares don t touch each other. m0 is adjacent to m2 and m4 is adjacent to m6. m0+m2=x y z +x yz =x z (y +y)=x z m4+m6=xy z +xyz =xz (y +y)=xz
12 Example 2 Simplfy the Boolean function F(x,y,z)=Σ(3,4,6,7) F(x,y,z)=yz+xz
13 Example 3 Simplfy the Boolean function F(x,y,z)=Σ(0,2,4,5,6) F(x,y,z)=z +xy
14 Example 4 F=A C+A B+AB C+BC Express F as a sum of minterms. F(A,B,C)=Σ(1,2,3,5,7) Find the minimal sumofproducts expression F=C+A B
15 FourVariable Map 16 minterms (and squares) for 4 variables.
16 Example 5 Simplify F(w,x,y,z)=Σ(0,1,2,4,5,6,8,9,12,13,14) F(w,x,y,z)=y +w z +xz
17 Example 6 Simplfy F=A B C +B CD +A BCD +AB C F=B D +B C +A CD
18 Prime Implicant A product term obtained by combining the max. possible number of adjacent squares. If a minterm is covered by only one prime implicant, that prime implicant is said to be essential.
19 Example F(A,B,C,D)=Σ(0,2,3,5,7,8,9,10,11,13,15)
20 Example F=BD+B D +CD+AD=BD+B D +CD+AB =BD+B D +B C+AD=BD+B D +B C+AB
21 FiveVariable Map Not simple, is not usually used. 5 variables, 32 squares.
22 Example 7 Simplfy F(A,B,C,D,E)=Σ(0,2,4,6,9,13,21,23,25,29,31) F=A B E +BD E +ACE
23 ProductofSums Simplification Mark the empty squares by 0 s. Combine them (as we did for sumofproducts) We obtain F (complement of the function) Take the complement of F ((F ) ) to obtain F.
24 Example 8 Simplfy F(A,B,C,D)=Σ(0,1,2,5,8,9,10) F=B D +B C +A C D F =AB+CD+BD => F=(A +B )(C +D )(B +D)
25 Example 8 gate impl. Two different implementations of the same function.
26 Don t Care Conditions In practice some combinations are not specified as 1 s or 0 s. Four bit binary codes has six unused combinations. Functions having unspecified outputs are called incompletely specified functions. We don t care the unspecified minterms These minterms are called don tcare conditions. They can be used for minimization. They are indicated as X s in the map. They can be assumed as 1 s or 0 s to have best simplification.
27 Example 9 Simplify F(w,x,y,z)=Σ(1,3,7,11,15) having don t care conditions d(w,x,y,z)= Σ(0,2,5)
28 NAND and NOR Implementation Generally used for circuit design Easier to fabricate. Basic gates Other functions can be generated from them. Rules have been developed to convert functions to NAND and NOR only implementations.
29 NAND Circuits NAND gate is universal Any digital system can be implemented with it. AND, OR and NOT can be implemented with NANDs.
30 Two graphic symbols of NAND
31 TwoLevel Implementation Have the function in sumofproduct form. Put bubbles (inverters) to have two different representations of NAND gate Either ANDinvert or InvertOR
32 Example: F=AB+CD
33 Example 10 Implement F(x,y,z)=Σ(1,2,3,4,5,7) with only NAND gates.
34 Multilevel NAND Circuits F=A(CD+B)+BC
35 NOR Implementation Dual of NAND operation
36 Example: F=(A+B)(C+D)E
37 Example: F=(AB +A B)(C+D )
38 ExclusiveOr (XOR) Function XOR x y xy xy 1 if only x is one or if only y is 1 XNOR ( x y) xy xy 1 if both inputs are 1 or both inputs are 0 Some identities of XOR x 0 x x 1 x' x x 0 x x'1 x y' x' y ( x y)'
39 XOR Implementations
40 Odd Funct on N variable XOR function is odd function defined as The logical sum of the 2 n /2 minterms whose binary numerical values have an odd number of 1 s. If n=3, 4 minterms have odd number of 1 s.
41 Logic Diagram of odd and even functions
42 Parity Generation A parity bit is an extra bit included with a binary message If number of 1 s is odd, parity bit is 1; else 0. The circuit that generates the parity bit in the transmitter is called parity generator. Parity bit can be generated using XOR function.
43 3Bit Parity Generator
44 Parity Checker Bits are transmitted to the destination with parity. The circuit that checks the parity in the receiver is called a parity checker. Parity checker can be implmeneted with XOR gates.
45 3Bit Parity Checker
GateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationGateLevel Minimization. BME208 Logic Circuits Yalçın İŞLER
GateLevel Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More information數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
More informationGateLevel Minimization. section instructor: Ufuk Çelikcan
GateLevel Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
More informationDigital Logic Design. Outline
Digital Logic Design GateLevel Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationChapter 3 Simplification of Boolean functions
3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean
More informationDigital Logic Lecture 7 Gate Level Minimization
Digital Logic Lecture 7 Gate Level Minimization By Ghada AlMashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. Kmap principles. Simplification using Kmaps. Don tcare
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationCSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map
CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationUNIT4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More informationDigital Design. Chapter 4. Principles Of. Simplification of Boolean Functions
Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming Boolean Cubes for n =,
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationUNIT II. Circuit minimization
UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 20062007) NOTES 5  page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Terminology For a given term, each
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 21 Binary Logic and Gates 22 Boolean Algebra 23 Standard Forms 24 TwoLevel Circuit Optimization
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum ProductofSums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8 Terminology For
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationChapter 2: Combinational Systems
Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationCombinational Logic & Circuits
WeekI Combinational Logic & Circuits Spring' 232  Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationIncompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples Incompletely specified functions
More informationCENG 241 Digital Design 1
CENG 241 Digital Design 1 Lecture 5 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Lab Review of last lecture: GateLevel Minimization Continue Chapter 3:XOR functions, Hardware Description Language
More informationIntroduction to Boolean logic and Logical Gates
Introduction to Boolean logic and Logical Gates Institute of Statistics Fall 2014 We saw the importance of the binary number system for data representation in a computer system. We ll see that the construction
More informationChapter 4. Combinational Logic. Dr. AbuArqoub
Chapter 4 Combinational Logic Introduction N Input Variables Combinational Logic Circuit M Output Variables 2 Design Procedure The problem is stated 2 The number of available input variables & required
More informationBOOLEAN ALGEBRA. 1. State & Verify Laws by using :
BOOLEAN ALGEBRA. State & Verify Laws by using :. State and algebraically verify Absorption Laws. (2) Absorption law states that (i) X + XY = X and (ii) X(X + Y) = X (i) X + XY = X LHS = X + XY = X( + Y)
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationBinary logic. Dr.AbuArqoub
Binary logic Binary logic deals with variables like (a, b, c,, x, y) that take on two discrete values (, ) and with operations that assume logic meaning ( AND, OR, NOT) Truth table is a table of all possible
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationCHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey
CHAPTER2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, KMap and QuineMcCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationX Y Z F=X+Y+Z
This circuit is used to obtain the compliment of a value. If X = 0, then X = 1. The truth table for NOT gate is : X X 0 1 1 0 2. OR gate : The OR gate has two or more input signals but only one output
More informationDIGITAL CIRCUIT LOGIC UNIT 7: MULTILEVEL GATE CIRCUITS NAND AND NOR GATES
DIGITAL CIRCUIT LOGIC UNIT 7: MULTILEVEL GATE CIRCUITS NAND AND NOR GATES 1 iclicker Question 13 Considering the KMap, f can be simplified as (2 minutes): A) f = b c + a b c B) f = ab d + a b d AB CD
More informationObjectives: 1 Bolean Algebra. Eng. Ayman Metwali
Objectives: Chapter 3 : 1 Boolean Algebra Boolean Expressions Boolean Identities Simplification of Boolean Expressions Complements Representing Boolean Functions 2 Logic gates 3 Digital Components 4
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012DIGITAL
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 20152016 (ODD
More informationModule 7. Karnaugh Maps
1 Module 7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or SumofMinterms (SOM) 2.4 Canonical product of sum or ProductofMaxterms(POM)
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationPresented By : Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak
Presented By : Alok Kumar Lecturer in ECE C.R.Polytechnic, Rohtak Content  Introduction 2 Feature 3 Feature of BJT 4 TTL 5 MOS 6 CMOS 7 K Map  Introduction Logic IC ASIC: Application Specific
More informationIntroduction to Computer Architecture
Boolean Operators The Boolean operators AND and OR are binary infix operators (that is, they take two arguments, and the operator appears between them.) A AND B D OR E We will form Boolean Functions of
More informationGC03 Boolean Algebra
Why study? GC3 Boolean Algebra Computers transfer and process binary representations of data. Binary operations are easily represented and manipulated in Boolean algebra! Digital electronics is binary/boolean
More informationDigital Systems and Binary Numbers
Digital Systems and Binary Numbers Mano & Ciletti Chapter 1 By Suleyman TOSUN Ankara University Outline Digital Systems Binary Numbers NumberBase Conversions Octal and Hexadecimal Numbers Complements
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationDKT 122/3 DIGITAL SYSTEM 1
Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits
More informationSwitching Theory And Logic Design UNITII GATE LEVEL MINIMIZATION
Switching Theory And Logic Design UNITII GATE LEVEL MINIMIZATION Twovariable kmap: A twovariable kmap can have 2 2 =4 possible combinations of the input variables A and B. Each of these combinations,
More informationUNIT V COMBINATIONAL LOGIC DESIGN
UNIT V COMBINATIONAL LOGIC DESIGN NOTE: This is UNITV in JNTUK and UNITIII and HALF PART OF UNITIV in JNTUA SYLLABUS (JNTUK)UNITV: Combinational Logic Design: Adders & Subtractors, Ripple Adder, Look
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationKarnaugh Map (KMap) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using Kmap
Karnaugh Map (KMap) Ch. 2.4 Ch. 2.5 Simplification using Kmap A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or
More informationENDTERM EXAMINATION
(Please Write your Exam Roll No. immediately) ENDTERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA103 Subject: Digital Electronics Time: 3 Hours Maximum
More information01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2006
Introduction to Digital Logic ENGR 34 Computer Architecture Mark L. Chang Fall 26 Acknowledgements Patterson & Hennessy: Book & Lecture Notes Patterson s 997 course notes (U.C. Berkeley CS 52, 997) Tom
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show
More informationContent beyond Syllabus. Parity checker and generator
Class : SE Div: B Subject : Logic Design Content beyond Syllabus Parity checker and generator What is parity bit? The parity generating technique is one of the most widely used error detection techniques
More informationDHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY
DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many
More informationDIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (KMAPS)
DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (KMAPS) 1 Learning Objectives 1. Given a function (completely or incompletely specified) of three to five variables, plot it on a Karnaugh map. The function
More informationCombinational Circuits
Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables
More informationLOGIC CIRCUITS. Kirti P_Didital Design 1
LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists
More informationDr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010
Dr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010 Instructions: This examination paper includes 9 pages and 20 multiplechoice questions starting on page 3. You are responsible for ensuring that your
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More informationCOMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic
More informationCombinational Logic Circuits Part III Theoretical Foundations
Combinational Logic Circuits Part III Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More informationReview: Standard forms of expressions
Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows
More information01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2008
Introduction to Digital Logic ENGR 34 Computer Architecture Mark L. Chang Fall 28 Acknowledgements Patterson & Hennessy: Book & Lecture Notes Patterson s 997 course notes (U.C. Berkeley CS 52, 997) Tom
More informationCS470: Computer Architecture. AMD Quad Core
CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flipflops Functional bocks: Combinational, Sequential Instruction
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationS1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017
S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and
More informationCombinational Logic with MSI and LSI
1010101010101010101010101010101010101010101010101010101010101010101010101010101010 1010101010101010101010101010101010101010101010101010101010101010101010101010101010 1010101010101010101010101010101010101010101010101010101010101010101010101010101010
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
More informationContents. Chapter 3 Combinational Circuits Page 1 of 34
Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4
More informationDSAS Laboratory no 4. Laboratory 4. Logic forms
Laboratory 4 Logic forms 4.1 Laboratory work goals Going from Boolean functions to Boolean forms. Logic forms equivalence. Boolean forms simplification. Shannon s theorems. Representation in NAND and NOR
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary
More informationMenu. Algebraic Simplification  Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification
Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification  Boolean Algebra Minterms (written as m i ):
More informationLogic Gates and Boolean Algebra ENT263
Logic Gates and Boolean Algebra ENT263 Logic Gates and Boolean Algebra Now that we understand the concept of binary numbers, we will study ways of describing how systems using binary logic levels make
More informationDigital Techniques. Lecture 1. 1 st Class
Digital Techniques Lecture 1 1 st Class Digital Techniques Digital Computer and Digital System: Digital computer is a part of digital system, it based on binary system. A block diagram of digital computer
More informationLogic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 3 Additional Gates and Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View
More information