6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

Size: px
Start display at page:

Download "6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )"

Transcription

1 6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2)

2 Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate logical values from place to place. Signals "flow" from left to right. Signals and Wires A drawing convention, sometimes violated Actually: flow from producer to consumer(s) of signal Input Output 2

3 Logic Gates Logical gates. Fundamental building blocks. x x' x y xy x y x + y NOT AND OR 3

4 Multiway AND Gates AND(x, x, x 2, x 3, x 4, x 5, x 6, x 7 ). if all inputs are. otherwise. 4

5 Multiway OR Gates OR(x, x, x 2, x 3, x 4, x 5, x 6, x 7 ). if at least one input is. otherwise. 5

6 Boolean Algebra History. Developed by Boole to solve mathematical logic problems (847). Shannon master's thesis applied it to digital circuits (937). Basics. Boolean variable: value is or. Boolean function: function whose inputs and outputs are,. Relationship to circuits. Boolean variables: signals. Boolean functions: circuits. "possibly the most important, and also the most famous, master's thesis of the [2th] century" --Howard Gardner 6

7 Truth Table Truth table. Systematic method to describe Boolean function. One row for each possible input combination. N inputs 2 N rows. AND Truth Table x y AND(x, y) AND 8

8 Truth Table for Functions of 2 Variables Truth table. 6 Boolean functions of 2 variables. every 4-bit value represents one Truth Table for All Boolean Functions of 2 Variables x y ZERO AND x y XOR OR Truth Table for All Boolean Functions of 2 Variables x y NOR EQ y' x' NAND ONE 9

9 Truth Table for Functions of 3 Variables Truth table. 6 Boolean functions of 2 variables. every 4-bit value represents one 256 Boolean functions of 3 variables. every 8-bit value represents one 2^(2^N) Boolean functions of N variables Some Functions of 3 Variables x y z AND OR MAJ ODD

10 Universality of AND, OR, NOT Any Boolean function can be expressed using AND, OR, NOT. "Universal." XOR(x,y) = xy' + x'y x Expressing XOR Using AND, OR, NOT y x' y' x'y xy' x'y + xy' XOR Exercise. Show {AND, NOT}, {OR, NOT}, {NAND}, {AND, XOR} are universal. Hint. Use DeMorgan s Law: (xy) = (x + y ) and (x + y) = (x y ) Notation x' x y x + y Meaning NOT x x AND y x OR y

11 Sum-of-Products Any Boolean function can be expressed using AND, OR, NOT. Sum-of-products is systematic procedure. form AND term for each in truth table of Boolean function OR terms together x'yz Expressing MAJ Using Sum-of-Products z xyz' xyz xy'z MAJ y x x'yz + xy'z + xyz' + xyz 2

12 Translate Boolean Formula to Boolean Circuit Use sum-of-products form. XOR(x, y) = xy' + x'y. 3

13 Translate Boolean Formula to Boolean Circuit Use sum-of-products form. MAJ(x, y, z) = x'yz + xy'z + xyz' + xyz. 4

14 Simplification Using Boolean Algebra Many possible circuits for each Boolean function. Sum-of-products not necessarily optimal in: number of gates (space) depth of circuit (time) MAJ(x, y, z) = x'yz + xy'z + xyz' + xyz = xy + yz + xz. size = 8, depth = 3 size = 4, depth = 2 5

15 Expressing a Boolean Function Using AND, OR, NOT Ingredients. AND gates. OR gates. NOT gates. Wire. Instructions. Step : represent input and output signals with Boolean variables. Step 2: construct truth table to carry out computation. Step 3: derive (simplified) Boolean expression using sum-of products. Step 4: transform Boolean expression into circuit. 6

16 ODD Parity Circuit ODD(x, y, z). if odd number of inputs are. otherwise. x'y'z Expressing ODD Using Sum-of-Products z xy'z' xyz x'yz' ODD y x x'y'z + x'yz' + xy'z' + xyz 8

17 ODD Parity Circuit ODD(x, y, z). if odd number of inputs are. otherwise. 9

18 Let's Make an Adder Circuit Goal: x + y = z for 4-bit integers. We build 4-bit adder: 9 inputs, 4 outputs. Same idea scales to 28-bit adder. Key computer component. Step. Represent input and output in binary x 3 x 2 x x + z 3 z 2 z z + c 3 c 2 c c x 3 x 2 x x y 3 y 2 y y c + y 3 y 2 y y z 3 z 2 z z 2

19 Let's Make an Adder Circuit Goal: x + y = z for 4-bit integers. Step 2. (first attempt) Build truth table. Why is this a bad idea? + c x 3 x 2 x x y 3 y 2 y y z 3 z 2 z z 28-bit adder: rows > # electrons in universe 4-Bit Adder Truth Table c x 2 x y 2 y z 2 z x 3 x y 3 y z 3 z 2 8+ = 52 rows

20 Let's Make an Adder Circuit Goal: x + y = z for 4-bit integers. Step 2. (do one bit at a time) Build truth table for carry bit. Build truth table for summand bit. + c 3 c = c 2 c x 3 x 2 x x y 3 y 2 y y z 3 z 2 z z Carry Bit x i y i c i c i+ Summand Bit y i c i z i x i 22

21 Let's Make an Adder Circuit Goal: x + y = z for 4-bit integers. Step 3. Derive (simplified) Boolean expression. + c 3 c = c 2 c x 3 x 2 x x y 3 y 2 y y z 3 z 2 z z Carry Bit Summand Bit y i c i c i+ MAJ y i c i z i ODD x i x i 23

22 Let's Make an Adder Circuit Goal: x + y = z for 4-bit integers. Step 4. Transform Boolean expression into circuit. Chain together -bit adders. 24

23 Let's Make an Adder Circuit Goal: x + y = z for 4-bit integers. Step 4. Transform Boolean expression into circuit. Chain together -bit adders. 25

24 Subtractor Subtractor circuit: z = x - y. One approach: new design, like adder circuit. Better idea: reuse adder circuit. 2's complement: to negate an integer, flip bits, then add x 3 x 2 x x z 3 x + z 2 z y - x - y y 3 y 2 y y carry z 4-Bit Subtractor Interface 4-Bit Subtractor Implementation 26

25 TOY Arithmetic Logic Unit: Interface ALU Interface. Add, subtract, bitwise and, bitwise xor, shift left, shift right, copy. Associate 3-bit integer with 5 primary ALU operations. ALU performs operations in parallel control wires select which result ALU outputs op 2 Input 6 +, - & ALU 6 ^ <<, >> input 2 Input ALU select shift direction subtract 27

26 n = 8 for main memory 2 n -to- Multiplexer 2 n -to- multiplexer. n select inputs, 2 n data inputs, output. Copies "selected" data input bit to output. x x x 2 x 3 y x x 4 x x 2 x 3 x 4 x 5 x 6 8 to MUX select y x 5 x 6 x 7 x 7 s s s 2 s 2 s s 8-to- Mux Interface 8-to- Mux Implementation 28

27 TOY Arithmetic Logic Unit: Implementation Input 6 Input 2 6 ~ + carry in & MUX 6 ^^ << >> op 2 +, - & 3 ^ <<, >> input 2 subtract shift direction ALU select 29

28 6.2: Sequential Circuits S Q R COS 26: General Computer Science

29 Combinational circuits. Sequential vs. Combinational Circuits Output determined solely by inputs. Can draw solely with left-to-right signal paths. Sequential circuits. Output determined by inputs AND previous outputs. Feedback loop. S R Q 3

30 Flip-Flop Flip-flop. A small and useful sequential circuit. Abstraction that "remembers" one bit. Basis of important computer components: memory counter We will consider several flavors. 32

31 SR Flip-Flop What is the value of Q if: S = and R =? Q is surely S Q R 33

32 SR Flip-Flop What is the value of Q if: S = and R =? Q is surely S = and R =? Q is surely S Q R 34

33 SR Flip-Flop What is the value of Q if: S = and R =? Q is surely S = and R =? Q is surely S = and R =? Q is possibly S Q R 35

34 SR Flip-Flop What is the value of Q if: S = and R =? Q is surely S = and R =? Q is surely S = and R =? Q is possibly... or possibly S Q R 36

35 SR Flip-Flop What is the value of Q if: S = and R =? Q is surely S = and R =? Q is surely S = and R =? Q is possibly... or possibly S old Q Q R While S = R =, Q remembers what it was the last time S or R was. 37

36 SR Flip-Flop SR Flip-Flop. S =, R = (Set) Flips bit on. S =, R = (Reset) Flops bit off. S = R = Status quo. S = R = Not allowed. S Q SR flip flop R S R Q Implementation Interface 38

37 Clock Clock. Fundamental abstraction. regular on-off pulse From some oscillating device, possibly external. Synchronizes operations of different circuit elements. GHz clock means billion pulses per second. cycle time Clock 39

38 How much does it Hert? Frequency is inverse of cycle time. Expressed in hertz. Frequency of Hz means that there is cycle per second. Hence: kilohertz (khz) means cycles/sec. megahertz (MHz) means million cycles/sec. gigahertz (GHz) means billion cycles/sec. terahertz (THz) means trillion cycles/sec. By the way, no such thing as hert Heinrich Rudolf Hertz ( ) 4

39 Clocked SR Flip-Flop Clocked SR Flip-Flop. Same as SR flip-flop except S and R only active when clock is. S clk R Implementation SR flip flop S Q R Clocked SR flip flop S clk R Q Interface Q clk R S 4

40 Clocked D Flip-Flop Clocked D Flip-Flop. Output follows D input while clock is. Output is remembered while clock is. D Cl Clocked SR flip flop S clk R Implementation Q Clocked D flip flop D clk Q Interface Q clk D 42

41 Summary Combinational circuits implement Boolean functions Gates and wires Fundamental building blocks. Truth tables. Describe Boolean functions. Sum-of-products. Systematic method to implement functions. Sequential circuits add "state" to digital hardware. Flip-flop. Represents bit. TOY register. 6 D flip-flops. TOY main memory. 256 registers. Next time: we build a complete TOY computer (oh yes). 43

42 George Boole (85 864) Claude Shannon (96 2) 44

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( )

6.1 Combinational Circuits. George Boole ( ) Claude Shannon ( ) 6. Combinational Circuits George Boole (85 864) Claude Shannon (96 2) Signals and Wires Digital signals Binary (or logical ) values: or, on or off, high or low voltage Wires. Propagate digital signals

More information

6. Combinational Circuits. Building Blocks. Digital Circuits. Wires. Q. What is a digital system? A. Digital: signals are 0 or 1.

6. Combinational Circuits. Building Blocks. Digital Circuits. Wires. Q. What is a digital system? A. Digital: signals are 0 or 1. Digital Circuits 6 Combinational Circuits Q What is a digital system? A Digital: signals are or analog: signals vary continuously Q Why digital systems? A Accurate, reliable, fast, cheap Basic abstractions

More information

Combinational Circuits

Combinational Circuits Combinational Circuits Q. What is a combinational circuit? A. Digital: signals are or. A. No feedback: no loops. analog circuits: signals vary continuously sequential circuits: loops allowed (stay tuned)

More information

Lecture 10: Combinational Circuits

Lecture 10: Combinational Circuits Computer Architecture Lecture : Combinational Circuits Previous two lectures.! TOY machine. Net two lectures.! Digital circuits. George Boole (85 864) Claude Shannon (96 2) Culminating lecture.! Putting

More information

6: Combinational Circuits

6: Combinational Circuits Computer Architecture 6: Combinational Circuits Previous two lectures. von Neumann machine. This lectures. Boolean circuits. Later in the course. Putting it all together and building a TOY machine. George

More information

Arithmetic Logic Unit (ALU)

Arithmetic Logic Unit (ALU) Arithmetic Logic Unit (ALU) Introduction to Computer Yung-Yu Chuang with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken (www.nand2tetris.org) and Harris & Harris (DDCA) Let's

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A

More information

QUESTION BANK FOR TEST

QUESTION BANK FOR TEST CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

More information

Mark Redekopp, All rights reserved. EE 352 Unit 8. HW Constructs

Mark Redekopp, All rights reserved. EE 352 Unit 8. HW Constructs EE 352 Unit 8 HW Constructs Logic Circuits Combinational logic Perform a specific function (mapping of 2 n input combinations to desired output combinations) No internal state or feedback Given a set of

More information

Combinational Circuits Digital Logic (Materials taken primarily from:

Combinational Circuits Digital Logic (Materials taken primarily from: Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a

More information

Parallel logic circuits

Parallel logic circuits Computer Mathematics Week 9 Parallel logic circuits College of Information cience and Engineering Ritsumeikan University last week the mathematics of logic circuits the foundation of all digital design

More information

Microcomputers. Outline. Number Systems and Digital Logic Review

Microcomputers. Outline. Number Systems and Digital Logic Review Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded

More information

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book

BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write

More information

Henry Lin, Department of Electrical and Computer Engineering, California State University, Bakersfield Lecture 7 (Digital Logic) July 24 th, 2012

Henry Lin, Department of Electrical and Computer Engineering, California State University, Bakersfield Lecture 7 (Digital Logic) July 24 th, 2012 Henry Lin, Department of Electrical and Computer Engineering, California State University, Bakersfield Lecture 7 (Digital Logic) July 24 th, 2012 1 Digital vs Analog Digital signals are binary; analog

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

More information

Boolean logic. Boolean Algebra. Introduction to Computer Yung-Yu Chuang NOT AND NOT

Boolean logic. Boolean Algebra. Introduction to Computer Yung-Yu Chuang NOT AND NOT oolean lgebra oolean logic ased on symbolic logic, designed by George oole oolean variables take values as or. oolean expressions created from: NOT, ND, OR Introduction to Computer ung-u Chuang with slides

More information

R10. II B. Tech I Semester, Supplementary Examinations, May

R10. II B. Tech I Semester, Supplementary Examinations, May SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

Software and Hardware

Software and Hardware Software and Hardware Numbers At the most fundamental level, a computer manipulates electricity according to specific rules To make those rules produce something useful, we need to associate the electrical

More information

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)

More information

Electronic Engineering Part 1 Laboratory Experiment. Digital Circuit Design 1 Combinational Logic. (3 hours)

Electronic Engineering Part 1 Laboratory Experiment. Digital Circuit Design 1 Combinational Logic. (3 hours) Electronic Engineering Part 1 Laboratory Experiment Digital Circuit Design 1 Combinational Logic (3 hours) 1. Introduction These days most signal processing is done digitally. Electronic signals (representing

More information

Digital Logic Design Exercises. Assignment 1

Digital Logic Design Exercises. Assignment 1 Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system

More information

REGISTER TRANSFER LANGUAGE

REGISTER TRANSFER LANGUAGE REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro

More information

ECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks

ECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class next-next Mon MLK Day ECE230 Review

More information

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3 UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented

More information

Introduction to Boole algebra. Binary algebra

Introduction to Boole algebra. Binary algebra Introduction to Boole algebra Binary algebra Boole algebra George Boole s book released in 1847 We have only two digits: true and false We have NOT, AND, OR, XOR etc operations We have axioms and theorems

More information

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit. Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic

More information

www.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL

More information

END-TERM EXAMINATION

END-TERM EXAMINATION (Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

More information

Injntu.com Injntu.com Injntu.com R16

Injntu.com Injntu.com Injntu.com R16 1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

More information

CS 261 Fall Mike Lam, Professor. Combinational Circuits

CS 261 Fall Mike Lam, Professor. Combinational Circuits CS 261 Fall 2017 Mike Lam, Professor Combinational Circuits The final frontier Java programs running on Java VM C programs compiled on Linux Assembly / machine code on CPU + memory??? Switches and electric

More information

Lecture (04) Boolean Algebra and Logic Gates

Lecture (04) Boolean Algebra and Logic Gates Lecture (4) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Dr. Ahmed ElShafee, ACU : Spring 26, Logic Design Boolean algebra properties basic assumptions and properties: Closure law A set S is

More information

Lecture (04) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee

Lecture (04) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee Lecture (4) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee Boolean algebra properties basic assumptions and properties: Closure law A set S is closed with respect to a binary operator, for every

More information

REGISTER TRANSFER AND MICROOPERATIONS

REGISTER TRANSFER AND MICROOPERATIONS REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: January 2, 2018 at 11:23 CS429 Slideset 5: 1 Topics of this Slideset

More information

01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2008

01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2008 Introduction to Digital Logic ENGR 34 Computer Architecture Mark L. Chang Fall 28 Acknowledgements Patterson & Hennessy: Book & Lecture Notes Patterson s 997 course notes (U.C. Berkeley CS 52, 997) Tom

More information

11/22/1999 7pm - 9pm. Name: Login Name: Preceptor Name: Precept Number:

11/22/1999 7pm - 9pm. Name: Login Name: Preceptor Name: Precept Number: Login Preceptor Precept Number: Computer Science 126 Second Midterm Exam 11/22/1999 7pm - 9pm This exam has 10 questions. The weight of each question is printed in the table below and next to each question.

More information

REGISTER TRANSFER AND MICROOPERATIONS

REGISTER TRANSFER AND MICROOPERATIONS 1 REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

More information

(ii) Simplify and implement the following SOP function using NOR gates:

(ii) Simplify and implement the following SOP function using NOR gates: DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be

More information

UNIT 2 BOOLEAN ALGEBRA

UNIT 2 BOOLEAN ALGEBRA UNIT 2 BOOLEN LGEBR Spring 2 2 Contents Introduction Basic operations Boolean expressions and truth tables Theorems and laws Basic theorems Commutative, associative, and distributive laws Simplification

More information

Reference Sheet for C112 Hardware

Reference Sheet for C112 Hardware Reference Sheet for C112 Hardware 1 Boolean Algebra, Gates and Circuits Autumn 2016 Basic Operators Precedence : (strongest),, + (weakest). AND A B R 0 0 0 0 1 0 1 0 0 1 1 1 OR + A B R 0 0 0 0 1 1 1 0

More information

IA Digital Electronics - Supervision I

IA Digital Electronics - Supervision I IA Digital Electronics - Supervision I Nandor Licker Due noon two days before the supervision 1 Overview The goal of this exercise is to design an 8-digit calculator capable of adding

More information

Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019

More information

Computer Organization and Levels of Abstraction

Computer Organization and Levels of Abstraction Computer Organization and Levels of Abstraction Announcements Today: PS 7 Lab 8: Sound Lab tonight bring machines and headphones! PA 7 Tomorrow: Lab 9 Friday: PS8 Today (Short) Floating point review Boolean

More information

UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination

More information

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

More information

CS 261 Fall Mike Lam, Professor. Logic Gates

CS 261 Fall Mike Lam, Professor. Logic Gates CS 261 Fall 2016 Mike Lam, Professor Logic Gates The final frontier Java programs running on Java VM C programs compiled on Linux Assembly / machine code on CPU + memory??? Switches and electric signals

More information

Boolean algebra. June 17, Howard Huang 1

Boolean algebra. June 17, Howard Huang 1 Boolean algebra Yesterday we talked about how analog voltages can represent the logical values true and false. We introduced the basic Boolean operations AND, OR and NOT, which can be implemented in hardware

More information

Combinational and sequential circuits (learned in Chapters 1 and 2) can be used to create simple digital systems.

Combinational and sequential circuits (learned in Chapters 1 and 2) can be used to create simple digital systems. REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift

More information

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

More information

Chapter 3. Boolean Algebra and Digital Logic

Chapter 3. Boolean Algebra and Digital Logic Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how

More information

ELCT 501: Digital System Design

ELCT 501: Digital System Design ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)

More information

DIGITAL ELECTRONICS. P41l 3 HOURS

DIGITAL ELECTRONICS. P41l 3 HOURS UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

More information

CHAPTER 4: Register Transfer Language and Microoperations

CHAPTER 4: Register Transfer Language and Microoperations CS 224: Computer Organization S.KHABET CHAPTER 4: Register Transfer Language and Microoperations Outline Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations

More information

Code No: 07A3EC03 Set No. 1

Code No: 07A3EC03 Set No. 1 Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,

More information

COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital

COMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in

More information

60-265: Winter ANSWERS Exercise 4 Combinational Circuit Design

60-265: Winter ANSWERS Exercise 4 Combinational Circuit Design 60-265: Winter 2010 Computer Architecture I: Digital Design ANSWERS Exercise 4 Combinational Circuit Design Question 1. One-bit Comparator [ 1 mark ] Consider two 1-bit inputs, A and B. If we assume that

More information

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]

1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] HW 3 Answer Key 1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tri-state buffers and inverters and thus you

More information

01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2006

01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2006 Introduction to Digital Logic ENGR 34 Computer Architecture Mark L. Chang Fall 26 Acknowledgements Patterson & Hennessy: Book & Lecture Notes Patterson s 997 course notes (U.C. Berkeley CS 52, 997) Tom

More information

EECS Components and Design Techniques for Digital Systems. Lec 07 PLAs and FSMs 9/ Big Idea: boolean functions <> gates.

EECS Components and Design Techniques for Digital Systems. Lec 07 PLAs and FSMs 9/ Big Idea: boolean functions <> gates. Review: minimum sum-of-products expression from a Karnaugh map EECS 5 - Components and Design Techniques for Digital Systems Lec 7 PLAs and FSMs 9/2- David Culler Electrical Engineering and Computer Sciences

More information

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE) SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech

More information

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register

More information

Arithmetic-logic units

Arithmetic-logic units Arithmetic-logic units An arithmetic-logic unit, or ALU, performs many different arithmetic and logic operations. The ALU is the heart of a processor you could say that everything else in the CPU is there

More information

Chapter 4. The Processor

Chapter 4. The Processor Chapter 4 The Processor Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified

More information

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

More information

Computer Organization and Levels of Abstraction

Computer Organization and Levels of Abstraction Computer Organization and Levels of Abstraction Announcements PS8 Due today PS9 Due July 22 Sound Lab tonight bring machines and headphones! Binary Search Today Review of binary floating point notation

More information

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess

More information

Propositional Calculus. Math Foundations of Computer Science

Propositional Calculus. Math Foundations of Computer Science Propositional Calculus Math Foundations of Computer Science Propositional Calculus Objective: To provide students with the concepts and techniques from propositional calculus so that they can use it to

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 2, 2016 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 2, 2016 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 90 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (10 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a)

More information

FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]

FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1] FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: [] FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed

More information

Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline.

Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline. Review EECS 150 - Components and Design Techniques for Digital Systems Lec 05 Boolean Logic 94-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley Design flow

More information

Question Total Possible Test Score Total 100

Question Total Possible Test Score Total 100 Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,

More information

EECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15

EECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15 1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus,

More information

1 /10 2 /12 3 /16 4 /30 5 /12 6 /20

1 /10 2 /12 3 /16 4 /30 5 /12 6 /20 M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.004 Computation Structures Fall 2018 Practice Quiz #1 1 /10 2 /12 3 /16 4

More information

Introduction to Boolean logic and Logical Gates

Introduction to Boolean logic and Logical Gates Introduction to Boolean logic and Logical Gates Institute of Statistics Fall 2014 We saw the importance of the binary number system for data representation in a computer system. We ll see that the construction

More information

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system. Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)

More information

Objectives: 1- Bolean Algebra. Eng. Ayman Metwali

Objectives: 1- Bolean Algebra. Eng. Ayman Metwali Objectives: Chapter 3 : 1- Boolean Algebra Boolean Expressions Boolean Identities Simplification of Boolean Expressions Complements Representing Boolean Functions 2- Logic gates 3- Digital Components 4-

More information

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT UNIT - V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, Random-Access memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable

More information

R07

R07 www..com www..com SET - 1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions

More information

CSC 220: Computer Organization Unit 10 Arithmetic-logic units

CSC 220: Computer Organization Unit 10 Arithmetic-logic units College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 10 Arithmetic-logic units 1 Remember: 2 Arithmetic-logic units An arithmetic-logic unit,

More information

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015

CS 31: Intro to Systems Digital Logic. Kevin Webb Swarthmore College February 3, 2015 CS 31: Intro to Systems Digital Logic Kevin Webb Swarthmore College February 3, 2015 Reading Quiz Today Hardware basics Machine memory models Digital signals Logic gates Circuits: Borrow some paper if

More information

LECTURE 4. Logic Design

LECTURE 4. Logic Design LECTURE 4 Logic Design LOGIC DESIGN The language of the machine is binary that is, sequences of 1 s and 0 s. But why? At the hardware level, computers are streams of signals. These signals only have two

More information

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify

More information

Sample Exam I PAC II ANSWERS

Sample Exam I PAC II ANSWERS Sample Exam I PAC II ANSWERS Please answer questions 1 and 2 on this paper and put all other answers in the blue book. 1. True/False. Please circle the correct response. a. T In the C and assembly calling

More information

Binary Adders: Half Adders and Full Adders

Binary Adders: Half Adders and Full Adders Binary Adders: Half Adders and Full Adders In this set of slides, we present the two basic types of adders: 1. Half adders, and 2. Full adders. Each type of adder functions to add two binary bits. In order

More information

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

More information

Scheme G. Sample Test Paper-I

Scheme G. Sample Test Paper-I Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable

More information

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown,

More information

Combinational Logic & Circuits

Combinational Logic & Circuits Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other

More information

Real Digital Problem Set #6

Real Digital Problem Set #6 Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch

More information

2008 The McGraw-Hill Companies, Inc. All rights reserved.

2008 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. 28 The McGraw-Hill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28

More information

Chapter 4. Combinational Logic

Chapter 4. Combinational Logic Chapter 4. Combinational Logic Tong In Oh 1 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential

More information

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to

More information

Chapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations

Chapter 4. The Processor. Instruction count Determined by ISA and compiler. We will examine two MIPS implementations Chapter 4 The Processor Part I Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations

More information

Logic design Ibn Al Haitham collage /Computer science Eng. Sameer

Logic design Ibn Al Haitham collage /Computer science Eng. Sameer DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as

More information

Final Exam Solution Sunday, December 15, 10:05-12:05 PM

Final Exam Solution Sunday, December 15, 10:05-12:05 PM Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals

More information