Manikandababu et al., International Journal of Advanced Engineering Technology E-ISSN

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1 Research Paper MODIFIED DISTRIBUTIVE ARITHMETIC ALGORITHM BASED 3D DWT PROCESSOR WITH PARALLELISM OPERATION OF 1D-DWT C.S.Manikandababu 1 Dr. N.J.R. Muniraj 2 Address for Correspondence 1 Assistant Professor (Selection Grade)/ECE, Sri Ramakrishna Engineering College, Coimbatore 2 Principal, Tejaa Shakthi Institute of Technology for Women, Coimbatore India. ABSTRACT The DWT based image compression technique leads into a new era of video and image processing with its better peak signal to noise ratio and high scalability in compression. The 3D DWT on video brings up the new possibilities in advanced fields like medical imaging, hyper spectral imaging, satellite based 3D surveillance system and video on network. The 3D DWT is still far from the real time applications because of its huge requirement of memory and computational complexity. The realization of 3D DWT in hardware is the best option to overcome the hurdles of computational speed. In this paper, we propose a novel Distributive Arithmetic (DA) algorithm based DWT processor which is used to design the three levels of DWT computation. At each level parallel processing is achieved and hence the optimum speed of 3D DWT computation is enhanced to 310MHz. The power consumption is restricted to less than 1W with memory utilization less than 8% on Virtex5 Platform. The 3D DWT processor is designed using modified DA algorithm and has a throughput of 9 clock cycles. The proposed architecture is suitable for high speed 3D DWT computation. EY WORDS: DWT Processor, parallel architecture, distributive arithmetic, FPGA implementation, Virtex5. 1 INTRODUCTION 2D-Discrete Wavelet Transforms (2D-DWT) have been predominantly used for image compression as per the recommendation in JPEG200 standards. Recently for encoding video frames, 3D-DWT have been adopted and have found to exhibit superior results for video coding applications [1][2]. For real time applications of video compression as in medical image processing, hyper spectral image processing, remote surveillance it is required to develop single chip solutions on System on Chip (SoC) platforms. 3D-DWT which is computationally intensive need to be implemented on SoC platforms to achieve higher performance, low power dissipation at reduced cost. One of the most flexible platforms is FPGA, as they provide flexibility and support parallelism. 3D wavelet transform implementation on FPGA is very challenging as it consumes large area and complex memory read/write operations. 3D image transformation and processing are also required in 4D medical imaging systems even need to perform 3D wavelet transforms for multiple 3D volume images, this further increases complexity for hardware implementation. While several 1D and 2D DWT architectures have been introduced and evaluated [3] [7], very few 3D architectures have been reported that have been optimized for hardware implementation. The complexities of 3D DWT architectures are addressed by block based architecture [8] [9], scan based architecture [10]-[12]. Some of them have attempted using convolution algorithm [13]-[17], lifting based algorithm has also been attempted in [18] [19]. Lifting computation is regularized and algorithm has been reported to reduce memory storage [19]. However, very few have attempted on realizing 3D DWT on group of frames, and two-level decomposition of GOPs. In this work, we propose a novel algorithm that can compute 3D DWT on GOPs and also perform two level 3D DWT. The proposed architecture is designed for high speed and low power applications. Section II discusses 3D transformation of video frames using DWT and Distributive Algorithm (DA) for DWT. Section III discusses design of proposed algorithm for 3D DWT, section IV discusses the implementation details and section V discusses results and discussion, section VI is conclusion. 2. 3D TRANSFORMATION OF VIDEO FRAMES The video image compression using 2D DWT is suitable for image compression but when it is for video image compression which will be having many image frames to be decomposed. Today s multimedia systems have to handles huge amount of digital images and the image compression ratio expected to be very high. The surveillance systems, Geographic Information System, hyper spectral imaging systems etc are moving to 3D image capturing and processing, so the Discrete Wavelet Transform for three dimensions 3D images is necessity to achieve good compression ratio. Even better compression ratio can be achieved for 2D video images using temporal correlation of video images using 3D DWT over 2D DWT. The 3D DWT decomposes the images in horizontal(x), vertical(y) and spectral (z) direction the image cubes will be decomposed to cubes of approximation and details. Classical 3D transform on 3D image is presented in Figure 1. The LL and LH represents the two levels transformed data and H is high pass output coefficients. The three dimensional transform is represented as vertical, Horizontal and Spectrum. Figure 1 Classical 3D Transform on 3D image [20] The processing of 3D DWT transform is very expensive due to the huge size buffer memories which are essential to temporarily store spectral

2 images for decomposition. The traditional 3D DWT need buffer memories at each stage and the size of buffer memory goes very high if the high level decomposition required. The memory management for 3D DWT transform processor is really critical as speed of the processor is directly affected and hardware resource costs very high. In traditional 3D DWT the use of buffer memories to calculate the one level 3D DWT for multi-spectral images of size 100x100x100 of pixel depth 8 bit (Size 972 bytes) will be 100x100x100 Bytes at first stage, 100x100 bytes at second stage so the total memory usage will be minimum 982 Bytes. The higher level of 3D DWT decomposition needs still additional memories to process and the speed of the processor will get reduced dramatically. The current situation demands development of novel memory efficient 3D DWT transform. 2.1 DA Scheme for DWT Distributed Arithmetic is one of the signals processing technique used to design and implement FIR filters. It is a bit level rearrangement of multiply accumulate to hide multiplications. DA helps in reducing the total hardware required for multiplyaccumulate operations which made it suitable for FPGA designs [21]. DA is used for computing sum of products using shift and add operations thus avoiding multipliers. Equation 1 describes an FIR filter of length n. N-1 Y= A k X k Eq. (1) k=0 Where, Y = response of the network, A k is filter coefficient and X k is input variable. DA performs multiplication using lookup table based schemes. The sum of product equation 1 can be realized using DA algorithm. The term x k is a 2 s-complement binary number scaled such that x k <1 and A k is fixed coefficients. x k is represented as {b k0, b k1, b k2, b k(n-1) }with word length=n, where b k0 is the sign bit. Expressing each x k as in Equation (2) N 1 n k 0 bkn2 n1 x b Eq. (2) k Substituting (2) in (1), the FIR filter equation can be expressed as in (3) y k1 Ak b Reordering (3) N 1 n k 0 bkn 2 Eq. (3) n1 N 1 n y Ak bkn 2 Ak ( bk 0) Eq. (4) n1 k1 k 1 Where, =No. of taps (inputs), N: Word length of Data. Consider the equation (4), the term A k b kn k 1 k1 A k b k has 2 possible values and the term ( has 2 possible values these terms can 0 ) be pre-computed based on the filter coefficients and stored in a lookup-table(rom) of size=2*2. A basic DA consists of serial in serial out shift register, an address generator, a look up table which stores all the partial products and a scaling accumulator. DA based computations are bit-serial in nature Serial Distributed Arithmetic (SDA) FIR filter (Figure 2). The x [n] to x [n-3] are the input data loaded to the serial shift registers, which are responsible to generate LUT addresses. Bits b0, b1, b2 and b3 fetch the partial result stored in the LUT for further operation. LUT stores the all possible partial product results as shown in the Figure 2. The accumulator and shift register units computes the convolution with all partial products. This is the basic working principle of DA FIR filters. This method is very suitable for implementation of DWT filter on FPGA. If the number of taps to LUT n increases the ROM size will be too large and thus the access time increases. This becomes a bottleneck for speed of whole system. The Parallel Distributed Arithmetic (PDA) implementation is one of the possible solutions which effectively reduces the memory Figure 2 LUT Based DA FIR Filter Design [22] usage and increases the speed of computation by splitting the LUTs [23]. This technique not only reduces the memory usage but also improves the RAM access time thus improving the speed of the whole system. 3. DESIGN OF 3D DWT ARCHITECTURE Design and VLSI implementation of high speed, low power 3D wavelet architecture is focused on video coding application. Flexible hardware architecture is designed for performing 3D Discrete Wavelet Transform. The proposed architecture uses distributive arithmetic algorithm, which has the ability of performing progressive computations by minimizing the buffering between the decomposition levels.

3 Figure 3 Block diagram of 3D 1 level DWT decomposition In this work, a Group of Frames (GOP) of size 8 x 8 x 8 is processed using the proposed algorithm to compute 3D DWT. The first level 3D DWT operates on 8 x 8 x 8 frame and in the second level 4 x 4 x 4 (LLL) component is further decomposed into eight sub bands of size 2 x 2 x 2. The 3D wavelet decomposition is computed by applying three separate 1D transforms along the coordinate axes of the video data as shown in Fig. 3. The 3D data is usually organized frame by frame. The single frames have again rows and columns as in the 2D case, x and y direction often denoted as spatial co-ordinates where as for video data a third dimension z for time is added. In the case of 2D decompositions, it does not matter in which order the filtering is performed. A 2-D filtering frame by frame with subsequent temporal filtering, three 1-D filtering along y, t, and x axes, one decomposition step results in 8 frequency sub bands out of which only the approximation data is processed further in the next decomposition step. The preliminary work in the DWT processor design is to build 1D DWT modules, which are composed of high-pass and low-pass filters that perform a convolution of filter coefficients and input pixels. After a one-level of 3D discrete wavelet transform, the volume of frame data is decomposed into HHH, HHL, HLH, HLL, LHH, LHL, LLH and LLL signals as shown in the Figure. 4. Figure 4 One-level 3D DWT structure Figure 4 shows the two-level decomposition of GOPs using 3D DWT. The first set of frames of size 8 x 8 x 8 are decomposed to eight sub bands of 4 x 4 x 4 size in the first level, and the LLL component is decomposed to eight sub bands of 2 x 2 x 2 in the Figure 6 Single Stage DWT second level. Figure 5 Two level 3D decomposition 3.1 Design of 1D DWT using Modified DA 3D DWT consists of three levels of DWT as shown in Figure 1 and Figure 4. In the first level each frame consisting of 8 x 8 rows and columns are decomposed into L and H sub bands each of size 8 x 4 and 8 x 4 respectively. The 1D-DWT consists of two FIR filters that are based on 9/7 filter coefficients as shown in Figure 6. The Low Pass (LP) filter has 9 coefficients and High Pass (HP) consists of 7 filter coefficients. Figure 7 8-Bit 9-Tap Modified Distributed Arithmetic Architecture for LPF

4 Figure 7 shows the modified DA architecture for LPF. There are 9 coefficients in LPF; hence there are 9 registers in the input shift register. There are 17 LUTs that store the pre computed partial products based on DA logic. For DA logic the output of first 8 registers are used as address for the LUT and the partial products are accumulated in the accumulator unit sequentially. The input data in the 9 th register is used in accessing the data from LUT, and the accumulator at the 5 th stage accumulates the data to compute the final output of LPF. Loading the input register requires 9 clock cycles, computing the output requires 8 clock cycles (depends on input bit width). Due to pipelining approach, the latency is 9 clock cycles, throughput is one clock cycle. For design of HP filter for DWT, the filter coefficients are 7, hence it required to have 7 input registers, with 13 LUTs, 13 summers to produce the final HP output. The HP filter architecture is similar to the one shown in Figure 7, with latency of 9 clock cycles, and throughput of 1 clock cycle due to pipelined architecture. 3.2 Design of 2D DWT architecture The 2D-DWT architecture using 1-D DWT is shown in Figure 8. The input data is stored in the Input memory register, the input data is simultaneously read into the 1D-DWT processor that consists of two modified DA filter architecture (that is shown in Figure 7). The 1-D DWT processor is fed with 8 input samples that generate 8 LP filter coefficients and 8 HP filter coefficients that are downscaled by 2 to obtain 4 LP and HP coefficients. In order to increase the processing speed, in this work, 8 1D- DWT processors are designed that parallel processes 8 rows of first frame and generates 8 output rows each of size 4 LP and 4 HP coefficients. the first frame that is accessed from the 8 intermediate memories. The output control unit reorders the 1D-DWT processor outputs from all the eight row processors into output memory of size 64 x 8. The control unit reads the first four outputs (L R1) from LP filter into first four locations of output memory, and the HP output samples (H R1) from first 1D-DWT row processor into next four locations as shown in Figure 9. Similarly the row outputs from all other processors are stored in the reordered way into the output memory. For processing of one frame of size 8 x 8, 8 row processors are used that process 8 rows simultaneously. The 8 x 8 input data consists of 64 rows that are processed in 8 clock cycles by the 8 row processors shown in Figure 9. The column processor processes the row output data using 8 1D- DWT processors in parallel to generate 8 outputs that are arranged as shown in Figure 10. The column processor processes 8 column inputs of every frame in parallel and hence requires 8 clock cycles for processing 8 frames. For each row processing and column processing it requires 9 clock cycles and 7 clock cycles respectively, thus the row processing clock and clock processing clock are 9 times faster than the master that is used to read row and column elements. The column processor processes the 8 frames in parallel and generates the 8 output frames with each frame consisting of four sub bands. In this example as the input data is of size 8 x 8 x 8, after 2D-DWT the output consists of 32 sub bands as shown in Figure 11. Figure 10 1D-DWT Column Processor Figure 8 2D-DWT architecture using proposed 1D- DWT Figure 9 Parallel processing architecture for 1D-DWT processor Figure 9 shows the parallel processing architecture designed that can process all eight rows of the first frame using the modified DA approach. The input memory is of size 512 x 8 (not shown in Figure 9), stores 8 frames of input each of size 64 x 8. The control unit reads the first frame of size 64 x 8 input from the main memory and stores the data into 8 intermediate memory of size 8 locations. Each of the intermediate memory drives the 1D-DWT processor that computes LP and HP coefficients for 8 rows of Figure 11 Reordering of 2D-DWT The 2D-DWT consists of 32 sub bands, each of size 4 x 4. The 4 x 4 sub bands are reordered into a row matrix of size 128 elements. The first LL sample from each frame is grouped first than the next LL samples and so on to obtain 128 elements. Similarly, all the other sub bands are reordered into 128 elements as shown in Figure 11. The input data to the third level DWT processor is reordered to 128 samples and there are four such sub bands that are processed using four independent DWT processors. The DWT coefficients generated from the DWT processor is rearranged to eight sub bands of LLL, LLH, LHL, LHH, HLL, HLH, HHL and HHH. Each of the sub bands consists of 4 x 4 samples of 4 frames as shown in Figure 13. The input image consisting of 8 x 8 x 8 samples after 2D DWT is decomposed into four sub bands of 4 x 4 x 4 of eight frames, which are further decomposed into 4 x 4 x 4 subbands of four frames each, thus

5 after 3D DWT 8 sub bands are generated. In the first phase there are eight row processor DWTs, in the second phase there are eight column processor DWTs, each operate on 8 samples of data. In the third phase there are 4 temporal DWT processors that operate on 128 samples. It is also possible to have 128 temporal DWT processors to increase the speed of computation in the third level. Figure 15 shows the simulation results of 3D DWT processor, the simulation results shows 8 levels so sub band data at the output from the inputs of 8 x 8 x 8 input. Figure 12 3D-DWT Processor The 3D-DWT architecture using DA algorithm has 20 1D-DWT processors that are operated in parallel. The multiplier logic is eliminated using DA algorithm. Memory units have been used to store the partial products of DA algorithm to compute DWT coefficients. The proposed model is Verilog coded and is simulated to verify its functionality; the HDL model is synthesized using Xilinx ISE. The results are discussed in the next section. Figure 15 Simulation results of 3D DWT of frame1 The design is synthesized in the Xilinx tool, post place, map and route simulation also have been carried out. The synthesized netlist of 1D DWT is shown in the Figure 16. The design is optimized for power, area and timing. Figure 13 Input image with intermediate and output results using 3D DWT 4 RESULTS AND DISCUSSION In order to verify the DWT algorithm, a know test vector is chosen to verify the results. For a known set of test inputs theoritical values of the acutal output is calculated and is compared with the simulation results output. The 1D-DWT processor results for known set of inputs in the range of 0 to 255 have been used as test inputs, and the corresponding outputs are obtained uisng Modelsim. The test results are shown in Figure 14. From the simulation results it is found that the 1D-DWT processor results are matching the theoretical requirements. Figure 14 First stage simulation results of 1D DWT processor using Modelsim Figure 16 Snapshot of 1D-DWT Synthesized netlist RTL synthesized block diagram of 3D-DWT is shown in Figure 17, implementation results of 1D- DWT and 3D-DWT are shown in Table 1. Table 1 Implementation results of 1D-DWT Slice Logic Used Available Utilization utilization Number of Slice ,200 1% Registers Number of Slice LUTs ,200 1% Table 2 Implementation results of 3D-DWT Slice Logic Used Available Utilization utilization Number of Slice ,200 5% Registers Number of Slice LUTs ,200 7%

6 In 1D-DWT 19,200 registers are available and 877 registers are utilized with utilization of 1%. LUT utilization is 1% with 765 LUTs used out of 19,200. In case of 3D-DWT 19,200 registers are available and 3,122 registers are utilized with utilization of 5%. LUT utilization is 7% with 3,734 LUTs out of 19,200. Table 3 shows the power report of 1D and 3D DWT processor. Table 3 Power report of 1D-DWT and 3D-DWT Name 1D-DWT 3D-DWT Total quiescent (W) (W) power Total dynamic (W) (W) power Total power (W) (W) Parallel processing operations of 1D-DWT and 2D- DWT computation can improve the operating speed at the cost of area, further the computation of 2D DWT during 1D DWT operation, as well as computation of 3D DWT during 2D DWT computation can improve the operating speed of the system. 5 CONCLUSION In the paper, a high speed memory efficient 3D DWT architecture has been modelled with parallel processing techniques. A memory efficient DA based 9/7 Daubechies filter bank has been developed that uses parallel processing architecture for 3D DWT computation on FPGA and it improves the speed of the 3D DWT. The custom architecture is modelled for nine frames of 8 x 8 x 8 pixels and validated using robust test bench. The proposed 3D DWT is implemented on Xilinx XC5VLX110 FPGA and achieved a highest operating frequency of 310 MHz. REFERENCES 1. G. Menegaz and J.-P. Thiran, Lossy to lossless objectbased coding of 3-D MRI data, IEEE Trans. Image Process., vol. 11, no. 9, pp , Sep J. E. Fowler and J. T. Rucker, 3-D wavelet-based compression of hyperspectral imagery, in Hyperspectral Data Exploitation: Theory and Applications, C.-I. Chang, Ed. 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Xiong, S. Li, and Y.-Q. Zhang, Memoryconstrained 3-D wavelet transform for video coding without boundary effects, IEEE Trans. Circuits Syst. Video Technol., vol. 12, no. 9, pp , Sep B. Das and S. Banerjee, Low power architecture of running 3-D wavelet transform for medical imaging application, in Proc. Eng. Med. Biol. Soc./Biomed. Eng. Soc. Conf., vol , pp B. Das and S. Banerjee, Data-folded architecture for running 3-D DWT using 4-tap Daubechies filters, IEE Proc. Circuits Devices Syst., vol. 152, no. 1, pp , Feb W. Sweldens, The lifting scheme: A custom-design construction of biorthogonal wavelets, Appl. Comput. Harmon. Anal., vol. 3, no. 15, pp , I. Daubechies and W. Sweldens, Factoring wavelet transforms into lifting steps, J. Fourier Anal. Appl., vol. 4, no. 3, pp , Z. Taghavi and S. asaei, A memory efficient algorithm for multidimensional wavelet transform based on lifting, in Proc. IEEE Int. Conf. Acoust. Speech Signal Process. (ICASSP), vol , pp Anirban Das Stephane. G. Mallat., Multifrequency Channel Decomposition of Images and Wavelet Models, IEEE Transactions on acoustics speech and processing decompositions of image.vol.37, No.12, Tinku Acharya and Ping-Sing Tsai, JPEG2000 Standared for Image Compression concepts, algorithms and VLSI architectures, John Wiley and Sons, Abdullah. AlMuhit, Md.Shabiul. Islam and Masuri. Othman, VLSI Implementation of Discrete Wavelet Transform (DWT) for Image Compression, 2nd International Conference on Autonomous Robots and Agents December 13-15, Yun Q. Shi and Huifang Sun, Image and Video Compression for Multimedia Engineering, Fundamentals, Algorithms and Standards, second edition, CRC Press LLC, USA 2000

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