IE1204/5 Digital Design example exam

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1 IE24/5 Digital Design example exam Part A (p in total) eight short Analysis tasks, p or 2p each - They are corrected only as Right/Wrong! - You need to get at least 6p on A, otherwise parts A2 and B will not be marked at all! Part A2 (p in total) two Methodology tasks. Marked only if there is at least 6p in part A. Part B (p in total) two Design problems. Marked Only if there is at least p in parts A+A2. Pass-limit for the entire exam is at least p, A+A2+(B). You can pass with no points from part B.

2 Grading scale A p A2 p B p Less than p på A+A2 F Part B will not be marked! Max 3 Less than 6p at A F Part A will not be marked! You can theoretical get grade C without solving part B.

3 Part A Analysis Right or wrong, p / p / 2p Minimum 6p out of p, otherwise parts A2 and B will not be marked at all!

4 ?: Part A ( 2// ) task. f ( x, y, z) = z( x + x y) + xyz + xyz = { SoP} =? min

5 !: Part A ( 2// ) task. f ( x, y, z) = z( x + x y) + xyz + xyz = { SoP} =? f( x, y, z) = x yz+ xyz+ x y z+ xyz+ xyz min

6 !: Part A ( 2// ) task. f ( x, y, z) = z( x + x y) + xyz + xyz = { SoP} =? f( x, y, z) = x y z+ xyz+ xyz+ xyz+ xyz min

7 !: Part A ( 2// ) task. f ( x, y, z) = z( x + x y) + xyz + xyz = { SoP} =? f( x, y, z) = x y z+ xyz+ xyz+ xyz+ xyz min

8 !: Part A ( 2// ) task. f ( x, y, z) = z( x + x y) + xyz + xyz = { SoP} =? f( x, y, z) = x y z+ xyz+ xyz+ xyz+ xyz min f ( x, y, z) { SoP} = z + = min xy

9 ?: Part A (/) task 2. 2 s complement-representation of an 8-bit number. ( B7) ±? 6 ( A6) ±? 6 = = ±?? 6

10 !: Part A (/) task 2. 2 s complement-representation of an 8-bit number. ( B7) ±? 6 ( A6) ±? 6 = = ±?? 6 ( B7) ( A6) ( B7) ( 73) Signbit! = = () () ( A6) 6 ( 9) = 2 2 = ( B7) 6 (7) = ( ) = ( ) + (5A) 6 = 2 2 () = ( 49) 6 6 = ( 5A) 6 = ( 73) = ( 9)

11 !: Part A ( 2// ) task 3. f ( x x2xx ) = { PoS} min 3 =?

12 !: Part A ( 2// ) task 3. f ( x3 x2xx min = ) = { PoS}? Groupings of :es

13 ?: Part A (/) task 4. q = x y A, B, C, D =?

14 !: Part A (/) task 4. y x q = A C B D XOR y x = = = = Lookup-table! A = B = C = D =

15 ?: Part A (/) task 5. Q( A, B) =?

16 !: Part A (/) task 5. A B Q Q( A, B) =? PullDown-circuit Q = A B Q = A B = { dm} = A + B

17 ?: Part A (/) task 6. ( q q )?????? =??...

18 !: Part A (/) task 6. Next state

19 ?: Part A (/) task 7. Complete this flow chart (for an asynchronous sequential circuit) with circles around stable states and by crossing out the conditions that can not be reached.

20 !: Part A (/) task 7. Identify the states that have the row letter Golden rule: Only one bit can change at a time. Inexpensive point for all those who did not "skip" section on asynchronous sequential circuits... Conclusion: Do not skip any sections of the course!

21 ?: Part A (/) task comment: example of buzzer circuit entity BUZZER is port (DOOR, IGNITION, SBELT: in std_logic; WARNING: out std_logic); end BUZZER; architecture behavioral of BUZZER is begin WARNING <= (not DOOR and IGNITION) or (not SBELT and IGNITION); end behavioral; Draw entity-box with signal names and circuit diagram

22 !: Part A (/) task 8. entity BUZZER is port (DOOR, IGNITION, SBELT: in std_logic; WARNING: out std_logic); end BUZZER;

23 !: Part A (/) task 8. architecture behavioral of BUZZER is begin WARNING <= (not DOOR and IGNITION) or (not SBELT and IGNITION); end behavioral;

24 Part A2 Methodology Will be marked if you get at least 6p in part A You need to get at least p in A + A2 for the part B to be marked

25 ?: Part A2 (5p) task 9. First, complete the full adder truth table. Then construct a full adder from two 4: MUXes. We assume the Carry signal cin also available in the complemented form (as shown on Figure). a b c in C out S

26 !: Part A2 (5p) task 9.

27 ?: Part A2 (5p) task. Coin slot Cup feeder Full indicator Coffee valve A coffee machine has two input signals: coin from the coin slot to indicate that a coin passed a photocell there and full from a user who observes the plastic cup to be filled. Coin = when the coin passed the photocell. full = when the cup is full. The coffee machine has two output signals: drop_cup to a unit containing plastic cups and coffee to a magnetic valve for filling the coffee. The cap unit drops a cup was once drop_cup becomes and coffee is filled as long as coffee =.

28 ?: Part A2 (5p) task. Coin slot Cup feeder Full indicator Coffee valve Construct a synchronous Moore machine that follows the given state diagram. State assignments must control the outputs directly. No output decoder is used. Use positive edge-triggered D flip-flops and gates of your choice. Draw a complete circuit diagram.

29 !: Part A2 (5p) task. coffee drop_ cup coffee drop _ cup coffee drop _ cup coffee drop_ cup q = qqi + q qi q = qqii qqi

30 !: Part A2 (5p) task. Coin slot Cup feeder Full indicator Coffee valve q = qqi + q qi q = qqii qqi

31 Part B Design We mark part B (p) if you get at least p at A + A2 Tasks can always be solved in different ways. We mark as far as possible taking into account possible errors from previous steps Digital design is a creative process

32 ?: Part B (5p) task 3.

33 !: Part B (5p) task 3. Was minimal from the beginning!

34 !: Part B (5p) task 3. Gray code

35 ?: Part B (5p) task 2. In order to study the I 2 C data transfer we want to construct a Moore-equivalent asynchronous sequential circuit which gives output signal busy = during the time from the start signal to the stop signal. When no data communication occurs busy =

36 !: Part B (5p) task 2. In a state a we "wait" for the start (b), therefore the input signal is impossible (marked with *). The protocol prohibits the alteration of data SDA when SCL is high. Therefore, the input signal is impossible in state e (marked with *). This gives two additional don t care positions in the table. One see immediately which states can be merged.

37 !: Del B (5p) uppg 2. We can use Gray code for state assignment: a =, bc =, de =. The unused state can have any next state except.

38 !: Del B (5p) uppg 2. Note that the resulting implementation is hazard-free becuase all adjacent s are covered by the same implicant.

39 Good Luck!

Written exam for IE1204/5 Digital Design Thursday 29/

Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.00-13.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 08-7904487 Exam text does not have to be returned when