SKEE2263 Sistem Digit

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1 Term Project Guide SKEE2263 Sistem Digit Table of Contents Objectives... 2 Project Scheduling... 2 Option 1: Serial Multiplier... 3 Option 2 : Serial Divider... 7 Option 3 : GCD Calculator Option 4 : Binary to BCD Converter This is a LIVE document and continuously updated. Download it from periodically for the latest version.

2 2 Term Project Guide Objectives To build a complete digital design containing a datapath unit and control unit using Schematic Capture To perform top-down design and bottom-up with emphasis on hierarchy, modularity and regularity To implement and test the design on the EPM240 board with all relevant input/output devices To manage a project with the aid of a Gantt Chart Project Scheduling The term project contributes 30% of your overall marks. At the end of term, you must implement a complete digital system an Altera CPLD board. The titles avalable for the project are listed in this document. To ensure you successfully complete the project, the term project has 6 different tasks, so that you build the complete system incrementally. The following Gantt Chart outlines the tasks. # Task 1 Quartus familiarization 2 Altera built-in module familiarization 3 Construction of combinational modules 4 Construction of sequential modules 5 Datapath unit integration 6 Control unit implementation Week The end of each task is a milestone, and you are to deliver the following: Milestone Date Deliverable 1 Early week 3 Multi-bit adder 2 Early week 5 4-bit to 7-segment decoder 3 Before break Combinational modules of your chosen circuit 4 Early week 11 Sequential modules of your chosen circuit 5 Early week 13 Datapath unit combining all previously designed modules 6 During week 15 Completed system combining datapath unit and control unit Completion of each milestone is worth 5% of the overall grade. You have done Milestones 1 and 2. This document describes Milestones 3 and 4 only since the descriptions for Milestones 5 and 6 are the same. If you are interested in pursuing other interesting titles, discuss with your lecturer concerning the specific deliverables for Milestones 3 and 4. Option # Title 1 Serial Multiplier 2 Serial Divider 3 Greatest Common Denominator (GCD) Calculator 4 Binary to BCD Converter TIP: You can simplify your work by creating a module in Verilog and inserting it in your schematic. You will need to save the circuit as a module by selecting (on the design window) File Create/Update Create Symbol File for Current File. This generates a.bdf file. In Verilog, you cannot insert a Pre-design Symbol Module (.bdf). You can only insert a verilog file (.v) to use a pre-designed module.

3 Option 1: Serial Multiplier 3 Option 1: Serial Multiplier Algorithm Serial multiplication is performed using the shift-and-add algorithm as shown in Figure 1-1. Datapath Figure 1-1: Multiplication using Shift-and-Add algorithm Deliverables Figure 1-2: Serial Multiplier datapath. Milestone Deliverable 3 4 bit Carry Look ahead Full Adder 4 4 bit Parallel Load Shift Register and 9 bit Parallel Load Shift Register 5 Datapath unit combining all previously designed Full Adder & Shift Register 6 Completed system combining datapath unit and control unit

4 Term Project Guide Milestone 3: 4-bit Carry Lookahead Adder Figure 1-3: CLA. Milestone 3a: Create 1- Bit Partial Full Adder Figure 1-4: PFA. Implement a 1-bit binary half adder based on Figure 2.

4 4 Term Project Guide Milestone 3: 4-bit Carry Lookahead Adder Figure 1-3: CLA. Milestone 3a: Create 1- Bit Partial Full Adder Figure 1-4: PFA. Implement a 1-bit binary half adder based on Figure 2. Simulate your circuit using functional simulation show proof that the waveform conform to the Boolean expression of the PFA. Milestone 3b: 4 bit Carry Look Ahead Generator (CLG) Implement a 4 bit Carry Look Ahead Generator based on the expression given Figure 2.

5 Option 1: Serial Multiplier 5 Simulate your circuit using functional simulation show proof that the waveform conform to the Boolean expression of the CLG by giving 4 test cases.. Milestone 3c: 4 bit Carry Look Ahead Adder (CLA4) Step 4: Using the four Half Full Adders and a 4 bit Carry look Ahead modules, implement the 4 bit Carry Look Ahead Adder based on Figure 1. Simulate your circuit using functional simulation. Show proof that the waveform conform to the Function of a 4-bit Full Adder giving 4 test cases Simulate your circuit using functional and timing simulation. Give a snapshot of functional and timing simulation for the following inputs: Cin A[3..0] B[3..0] S[3..0] Gate Delay C4 S3 S2 S1 S0 Note: You will need to determine the period of 1 gate delay. Milestone 4: 9-bit Shift Register Refer to Figure 1-1. There a two registers located below the adder: one 1 bit register and two 4-bit registers. Each bit must be able to perform 3 functions: hold, load from adder and shift right. We can use the universal shift register as the foundation. It can perform 4 functions. We are not going to use the shift left function. Figure 1-5: USR.

6 6 Term Project Guide Milestone 4a: 1 bit of Universal Shift Register (USR) Implement one bit of the USR. Figure 1-6: 1 bit of USR. Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing. Milestone 4b: 4 bit Universal Shift Register (USR) Implement the complete 4 bit USR. Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing i.e. it can do a parallel load (D à Q+) right shift (Q>>1 à Q+), and hold (Q à Q+). Milestone 4c: Linked FF and USRs Combine 1 FF, and 2 USRs according to Figure 1-2. Simulate your circuit using functional and timing simulation show proof that the whole 9-bit register does what it is supposed to be doing. Milestone 5: The Datapath Combine the circuits in Milestones 3 through 4 to build the datapath as shown in Fig Simulate using sensible data combinations. Milestone 6: The Complete System Draw the Algorithmic State Machine (ASM) Chart to control the whole datapath. Build the control unit to implement the ASM chart. Test the system using sensible data combinations. The data set you choose will reveal your knowledge. Choose wisely.

7 Option 2 : Serial Divider 7 Option 2 : Serial Divider Algorithm Division in hardware can be done using several methods. One of them is the non-restoring algorithm in Figure 2-1. Datapath Figure 2-1: Non-restoring division. Figure 2-2 Serial Divider

8 8 Term Project Guide Deliverables Milestone Deliverable 3 5 bit Adder/Subtractor 4 5 bit and 4 bit Parallel Load Shift Registers 5 Datapath unit combining all previously designed Full Adder Shift Register 6 Completed system combining datapath unit and control unit Milestone 3: 5-bit Ripple Carry Adder/Subtractor Figure 2-3: 5-bit Ripple Carry Adder/Subtractor. Milestone 3a: Create 1- Bit Full Adder Figure 2-4: PFA. Implement a 1-bit Full adder based on Figure 2.4. Simulate your circuit using functional simulation show proof that the waveform conform to the Boolean expression of the 1-bit Full adder.

9 Option 2 : Serial Divider 9 Milestone 3b: Ex-Or implementation using 2-1 Multiplexer Figure 2-5: Ex-Or implementation using 2-1 Multiplexer Implement a Ex-OR expression based Figure 2. Simulate your circuit using functional simulation show proof that the waveform conform to the Boolean expression of the X = f (A,B) =. Milestone 3c: 5 bit Adder/Subtractor Step 4: Using the Full Adders and Ex-Or modules, implement the 5 bit Adder/Subtractor based on Figure 1. Simulate your circuit using functional simulation. Show proof that the waveform conform to the Function of a 4-bit Full Adder giving 4 test cases Simulate your circuit using functional and timing simulation. Give a snapshot of functional and timing simulation for the following inputs: Add/Sub A[4..0] B[4..0] S[4..0] Gate Delay C5 S4 S3 S2 S1 S0 Note: You will need to determine the period of 1 gate delay.

10 10 Term Project Guide Milestone 4: 9-bit Shift Register Refer to Figure 2-1. There a two registers located below the 5-bit adder/subtractor: one 5 bit register and one 4- bit registers. Each bit must be able to perform 3 functions: hold, load from adder and shift left. We can use the universal shift register as the foundation. It can perform 4 functions. We are not going to use the shift right function. Figure 2-5: USR. Milestone 4a: 5 bit of Universal Shift Register (USR) Implement the 5 bit USR. Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing i.e. it can do a parallel load (D à Q+), left shift (Q<<1 à Q+) and hold (Q à Q+). Milestone 4b: 4 bit Universal Shift Register (USR) Implement the complete 4 bit USR. Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing i.e. it can do a parallel load (D à Q+), left shift (D<<1 à Q+) and hold (Q à Q+). Milestone 5: The Datapath Combine the circuits in Milestones 3 through 4 to build the datapath as shown in Fig 2-2. Simulate using sensible data combinations. Milestone 6: The Complete System Draw the Algorithmic State Machine (ASM) Chart to control the whole datapath. Build the control unit to implement the ASM chart. Test the system using sensible data combinations. The data set you choose will reveal your knowledge. Choose wisely.

11 Option 3 : GCD Calculator 11 Option 3 : GCD Calculator Algorithm The greatest common divisor (GCD) of two numbers is the largest number that divides both of them without leaving a remainder. The GCD of 54 and 24 is 6 as shown below: The number 54 can be expressed as a product of two integers in several different ways: 54 x 1 = 27 x 2 = 18 x 3 = 9 x 6 Thus the divisors of 54 are: 1,2,3,6,9,18,27,54 Similarly, the divisors of 24 are: 1,2,3,4,6,8,12,24 The numbers that these two lists share in common are the common divisors of 54 and 24: 1,2,3,6 The greatest of these is 6. That is, the greatest common divisor of 54 and 24. One writes: gcd(54,24) = 6. GCD is popularly solved using Euclid s algorithm. The pseudocode: function gcd(x, y) while x y if x > y x := x y; else y := y x; return x; Datapath To make the circuit useful but still simple enough, data size of 6 bits is chosen. Deliverables Figure 3-1 GCD Engine ( Milestone Deliverable 3 6-bit 2:1 mux, 6-bit subtractor (lpm_addsub), bit registers, 6-bit comparator (iterative) 5 Datapath unit combining all modules shown in Fig Completed system combining datapath unit and control unit

12 12 Term Project Guide Milestone 3: 6-bit Ripple Subtractor & Mux Milestone 3a: 6 bit Mux Based on the mux you used in Milestone 2, expand it to 6 bits. Simulate your circuit using functional simulation. Show proof that the waveform conform to the function of a 6-bit mux using 4 test cases. Milestone 3b: 6 bit Subtractor Figure 3-3 lpm_add_sub Pick the lpm_add_sub symbol from the Altera MegaWizard. Configure it as a 6-bit subtractor. Disable the adder function. Simulate your circuit using functional and timing simulation. Show proof that the waveform conform to the function of a 6-bit mux using 4 test cases. X[5..0] Y[4..0] D[4..0]

13 Option 3 : GCD Calculator 13 Milestone 4: Registers and Comparator Milestone 4a: DFFE Figure 3-3 DFFE Build the DFF with enable as shown in Figure 3-3. Refer to your textbook for explanation on how it works. Simulate your circuit using functional and timing simulation. Show proof that you understand how to use the DFFE. Save the circuit as an Altera module called DFFE. Milestone 4a: 6 bit Register with Enable Combine 6 units of the DFFE to build a 6-bit register with 6-bit data input, 6-bit data output, one clock input and one enable input. Simulate your circuit using functional simulation. Show proof that you understand how a register with enable works. Milestone 4c: One Bit Comparator Build one slice of the iterative comparator. Refer to the textbook for more details.

14 14 Term Project Guide Simulate your circuit using functional simulation. Show proof that you understand how the comparator worksl. Save the circuit as an Altera module called comp1bit. Milestone 4d: Six Bit Comparator Combine 6 comp1bit modules to build a 6-bit comparator. Add the necessary gates to produce the x_lt_y and x_ne_y signals as shown in Figure 3-1. Simulate your circuit using functional and timing simulation. Use the following test data. X[5..0] Y[4..0] x_lt_y x_ne_y Save the circuit as an Altera module called DFFE. Milestone 5: The Datapath Combine the circuits in Milestones 3 through 4 to build the datapath in Figure 3-1. Simulate using sensible data combinations. Milestone 6: The Complete System Draw the Algorithmic State Machine (ASM) Chart to control the whole datapath. Build the control unit to implement the ASM chart. Test the system using sensible data combinations. The data set you choose will reveal your knowledge. Choose wisely.

Option 4 : Binary to BCD Converter 15 Option 4 : Binary to BCD Converter Algorithm // Double-dabble algorithm Hundreds = 0; Tens = 0; Ones = 0; for (i=0; i<8; i++ { // check all columns >= 5 if

15 Option 4 : Binary to BCD Converter 15 Option 4 : Binary to BCD Converter Algorithm // Double-dabble algorithm Hundreds = 0; Tens = 0; Ones = 0; for (i=0; i<8; i++ { // check all columns >= 5 if (Hundreds >= 5) Hundreds += 3; if (Tens >= 5) Tens += 3; if (Ones >= 5) Ones += 3; // shift all bits left Hundreds <<- 1; Hundreds[0] = Tens[3]; Tens <<= 1; Tens[0] = Ones[3]; Ones <<= 1; Ones[0] = Binary[7] Binary <<= 1; } Converting 255 from binary to BCD: Hundreds Tens Ones Binary Oper Load << # << # << # << # << # << # << # << #8 Datapath Figure 4-1 Binary to BCD Engine Deliverables Milestone Deliverables 3 Custom add-by-3-if-greater-than-4 circuit & 8-bit PISO bit Universal Shift Register 5 Datapath unit combining all modules shown in Fig Completed system combining datapath unit and control unit

16 16 Term Project Guide Milestone 3: Custom adder and register cell Milestone 3a: Add-3-if-greater-than-4 circuit Figure 4-2: Custom adder circuit. Based on the truth table in Figure 4-2, build the simplest and fastest circuit. Justify your design. Simulate your circuit using functional and functional simulation. Test using all 16 input combinations. Find the worst case delay. Milestone 3b: PISO register Figure 4-3: Simplified PISO. Details have been left out. Based on 4-bit shift right PISO in Figure 4-3, modify it to shift left and expand it to 8 bits. The 8-bit PISO must have 2 control signals: LD (parallel load) and SH (left shift). LD has higher priority than SH. Simulate your circuit using functional and timing simulation. Prove that you understand how a PISO works. Prove that you understand how to use the LD and SH signals.

17 Option 4 : Binary to BCD Converter 17 Milestone 4: bit Shift Register Refer to the universal shift register in Figure 4-4. Use this register as the foundation for the Shift Register. First build a module to implement a single bit. Then use it to build the 2-bit Hundreds register and the 4-bit Tens and Ones registers. Note: The Hundreds register is not required to parallel load. You may find a simpler circuit for it later if you like. Figure 4-4: USR. Milestone 4a: 1 bit of Universal Shift Register (USR) Implement one bit of the USR. Figure 4-5: 1 bit of USR. Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing. Milestone 4b: 4 bit Universal Shift Register (USR) Implement the complete 4 bit USR. Simulate your circuit using functional simulation show proof that the bit cell does what it is supposed to be doing i.e. it can do a parallel load (D à Q+) right shift (Q>>1 à Q+), and hold (Q à Q+).

18 18 Term Project Guide Milestone 4c: 2 bit SIPO Simplify the 1-bit USR cell in Figure 4-5 so that it can shift left or hold only. Simulate your circuit using functional and timing simulation show proof that the whole 9-bit register does what it is supposed to be doing. Milestone 5: The Datapath Combine the circuits in Milestones 3 through 4 to build the datapath as shown in Fig Simulate using sensible data combinations. Milestone 6: The Complete System Draw the Algorithmic State Machine (ASM) Chart to control the whole datapath. Build the control unit to implement the ASM chart. Test the system using sensible data combinations. The data set you choose will reveal your knowledge. Choose wisely.

19 Option 4 : Binary to BCD Converter 19

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition

Digital Design Using Digilent FPGA Boards -- Verilog / Active-HDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9