Verilog for Combinational Circuits

Size: px
Start display at page:

Download "Verilog for Combinational Circuits"

Transcription

1 Verilog for Combinational Circuits Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,

2 HDL Models of Combinational Circuits Modeling Styles Gate-level modeling using instantiations of predefined and user-defined primitive gates. Dataflow modeling using continuous assignments with keyword assign. Behavioral modeling using procedural assignments with keyword always. (Instantiations ~ the HDL counterpart of placing and connecting parts on a circuit board) 2

3 Gate-level Modeling The four-valued logic truth tables for the and, or, xor, and not primitives Unknown High impedance 3

4 Gate-level Modeling Example (identifiers having multiple bit widths, call vectors): output [0: 3] D; wire [7: 0] SUM; 1. The first statement declares an output vector D with four bits, 0 through The second declares a wire vector SUM with eight bits numbered 7 through 0. 4

5 Gate-level Modeling 1st once 5

6 1-Bit Half Adder Half adder = 0 ; = 1 ; = 1 ; = (10) 2 two input variables: x, y two output variables: C (carry), S (sum) truth table S = x'y+xy'=x y= (x+y)(x'+y') C = xy= (x'+y')' S' = xy+x'y' S = (C+x'y')' Lan-Da Van DCD-04-6

7 Logic Diagram of 1-Bit Half Adder Lan-Da Van DCD-04-7

8 Full-Adder The arithmetic sum of three input bits three input bits x, y: two significant bits z: the carry bit from the previous lower significant bit Two output bits: C, S 1-Bit Full Adder Su m Carry Lan-Da Van DCD-04-8

9 Logic Diagram of 1-Bit Full Adder Lan-Da Van DCD-04-9

10 Logic Diagram of 1-Bit Full Adder S = x'y'z+x'yz'+ xy'z'+xyz = x (y z) +x(y z) = x y z C = xy + xz + yz = xy + xyz + xy z + xyz + x yz = xy + z (x y + xy) = xy + z (x y) Lan-Da Van DCD-04-10

11 Gate-level Modeling Bottom-up hierarchical description 11

12 Gate-level Modeling HDL Example 4.2 (cont.) S1 C1 C2 12

13 Gate-level Modeling Statement of Three-state gates: gate name (output, input, control); 13

14 Gate-level Modeling Example (gate instantiation with three-state gates) 14

15 Gate-level Modeling Nets (not a keyword): a set of data types representing connections between hardware elements wire, wor, wand, tri, supply1, supply0. 15

16 Dataflow Modeling What s the function? Example: assign Y = (A & S) (B & ~S) B m_out A select 16

17 Dataflow Modeling 17

18 Dataflow Modeling 18

19 Dataflow Modeling A Verilog HDL synthesis compiler can accept the module description as input, execute synthesis algorithms, and provide an output netlist and a schematic of a circuit equivalent to the one in Fig (see next page), all without manual intervention! 19

20 Magnitude Comparator Fig Four-bit magnitude comparator. 20

21 Magnitude Comparator The comparison of two numbers outputs: A>B, A=B, A<B Design Approaches the truth table 2 2n entries - too cumbersome for large n use inherent regularity of the problem reduce design efforts reduce human errors Algorithm -> logic A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 A=B if A 3 =B 3, A 2 =B 2, A 1 =B 1 and A 0 =B 0 equality: x i = A i B i +A i 'B i ' (A=B) = x 3 x 2 x 1 x 0 (A>B) = A 3 B 3 '+x 3 A 2 B 2 '+x 3 x 2 A 1 B 1 '+x 3 x 2 x 1 A 0 B 0 ' (A<B) = A 3 'B 3 +x 3 A 2 'B 2 +x 3 x 2 A 1 'B 1 +x 3 x 2 x 1 A 0 'B 0 Implementation x i = (A i B i '+A i 'B i )' Lan-Da Van DCD-04-21

22 Dataflow Modeling Conditional operator (?:) condition? true-expression : false-expression B m_out A select 22

23 Behavioral Modeling If statement: if (select) OUT = A; B m_out A select 23

24 Behavioral Modeling 24

25 initial block Writing a Simple Test Bench Inputs specified by a three-bit truth table // #10: delayed by 10ns 25

26 Writing a Simple Test Bench Stimulus module 26

27 Writing a Simple Test Bench Interaction between stimulus and design modules 27

28 Writing a Simple Test Bench System tasks for display Syntax for $display, $write, and $monitor: Task-name (format specification, argument list); Example: Example: 28

29 Writing a Simple Test Bench B m_out A select 29

30 Writing a Simple Test Bench B m_out A select 30

31 Writing a Simple Test Bench a full adder 31

32 Writing a Simple Test Bench 32

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

More information

Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93

Combinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93 Combinational Logic Prof. Wangrok Oh Dept. of Information Communications Eng. Chungnam National University Prof. Wangrok Oh(CNU) / 93 Overview Introduction 2 Combinational Circuits 3 Analysis Procedure

More information

Register Transfer Level in Verilog: Part I

Register Transfer Level in Verilog: Part I Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part I Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

Verilog Dataflow Modeling

Verilog Dataflow Modeling Verilog Dataflow Modeling Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:

More information

Hardware Description Languages (HDLs) Verilog

Hardware Description Languages (HDLs) Verilog Hardware Description Languages (HDLs) Verilog Material from Mano & Ciletti book By Kurtulus KULLU Ankara University What are HDLs? A Hardware Description Language resembles a programming language specifically

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

More information

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE

EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output

More information

Verilog Behavioral Modeling

Verilog Behavioral Modeling Verilog Behavioral Modeling Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:

More information

Combinational Logic Design with Verilog. ECE 152A Winter 2012

Combinational Logic Design with Verilog. ECE 152A Winter 2012 Combinational Logic Design with Verilog ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.10 Introduction to Verilog 2.10.1 Structural Specification of Logic

More information

Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language

Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language 1 / 15 2014/11/20 0 EDA (Electronic Design Assistance) 0 Computer based language 0 HDL (Hardware Description Language) 0 Verilog HDL 0 Created by Gateway Design Automation Corp. in 1983 First modern hardware

More information

ECE Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers

ECE Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers ECE 601 - Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers Fall 2001 Final Version (Important changes from original posted Exercise 1 shown in color) Variables

More information

Introduction to Verilog

Introduction to Verilog Introduction to Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Hardware Description Language Logic Simulation versus Synthesis

More information

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages 14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #22: Introduction to Verilog Hardware Description Languages Basic idea: Language constructs

More information

Combinational Logic Circuits

Combinational Logic Circuits Combinational Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has

More information

Hardware description language (HDL)

Hardware description language (HDL) Hardware description language (HDL) A hardware description language (HDL) is a computer-based language that describes the hardware of digital systems in a textual form. It resembles an ordinary computer

More information

EECS 3201: Digital Logic Design Lecture 4. Ihab Amer, PhD, SMIEEE, P.Eng.

EECS 3201: Digital Logic Design Lecture 4. Ihab Amer, PhD, SMIEEE, P.Eng. EECS 32: Digital Logic Design Lecture 4 Ihab Amer, PhD, SMIEEE, P.Eng. What is a HDL? A high-level computer language that can describe digital systems in tetual form Two applications of HDL processing:

More information

Hardware Description Language (HDL)

Hardware Description Language (HDL) Hardware Description Language (HDL) What is the need for Hardware Description Language? Model, Represent, And Simulate Digital Hardware Hardware Concurrency Parallel Activity Flow Semantics for Signal

More information

CENG 241 Digital Design 1

CENG 241 Digital Design 1 CENG 241 Digital Design 1 Lecture 5 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Lab Review of last lecture: Gate-Level Minimization Continue Chapter 3:XOR functions, Hardware Description Language

More information

Hardware description languages

Hardware description languages Specifying digital circuits Schematics (what we ve done so far) Structural description Describe circuit as interconnected elements Build complex circuits using hierarchy Large circuits are unreadable Hardware

More information

Introduction to Verilog HDL

Introduction to Verilog HDL Introduction to Verilog HDL Ben Abdallah Abderazek National University of Electro-communications, Tokyo, Graduate School of information Systems May 2004 04/09/08 1 What you will understand after having

More information

Iteration Bound. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C.

Iteration Bound. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Iteration Bound ( 范倫達 ) Ph. D. Department of Computer Science National Chiao Tung University Taiwan R.O.C. Fall 2 ldvan@cs.nctu.edu.tw http://www.cs.nctu.tw/~ldvan/ Outline Introduction Data Flow Graph

More information

Verilog Tutorial (Structure, Test)

Verilog Tutorial (Structure, Test) Digital Circuit Design and Language Verilog Tutorial (Structure, Test) Chang, Ik Joon Kyunghee University Hierarchical Design Top-down Design Methodology Bottom-up Design Methodology Module START Example)

More information

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad-500 014 Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of

More information

HDL for Combinational Circuits. ENEL211 Digital Technology

HDL for Combinational Circuits. ENEL211 Digital Technology HDL for Combinational Circuits ENEL211 Digital Technology Lecture Outline Vectors Modular design Tri-state gates Dataflow modelling Behavioural Modelling Vectors Often we want multi-bit quantities in digital

More information

Tutorial on Verilog HDL

Tutorial on Verilog HDL Tutorial on Verilog HDL HDL Hardware Description Languages Widely used in logic design Verilog and VHDL Describe hardware using code Document logic functions Simulate logic before building Synthesize code

More information

Course Topics - Outline

Course Topics - Outline Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7

More information

structure syntax different levels of abstraction

structure syntax different levels of abstraction This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

Introduction to Verilog HDL. Verilog 1

Introduction to Verilog HDL. Verilog 1 Introduction to HDL Hardware Description Language (HDL) High-Level Programming Language Special constructs to model microelectronic circuits Describe the operation of a circuit at various levels of abstraction

More information

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 2 COMBINATIONAL LOGIC Combinational circuits Analysis

More information

INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING

INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 00 0 ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK Course Name : DIGITAL DESIGN USING VERILOG HDL Course Code : A00 Class : II - B.

More information

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is

More information

2/14/2016. Hardware Synthesis. Midia Reshadi. CE Department. Entities, Architectures, and Coding.

2/14/2016. Hardware Synthesis. Midia Reshadi. CE Department.   Entities, Architectures, and Coding. Hardware Synthesis MidiaReshadi CE Department Science and research branch of Islamic Azad University Email: ce.srbiau@gmail.com Midia Reshadi 1 Chapter 2 Entities, Architectures, and Coding Styles Midia

More information

Verilog HDL. A Guide to Digital Design and Synthesis. Samir Palnitkar. SunSoft Press A Prentice Hall Title

Verilog HDL. A Guide to Digital Design and Synthesis. Samir Palnitkar. SunSoft Press A Prentice Hall Title Verilog HDL A Guide to Digital Design and Synthesis Samir Palnitkar SunSoft Press A Prentice Hall Title Table of Contents About the Author Foreword Preface Acknowledgments v xxxi xxxiii xxxvii Part 1:

More information

MLR Institute of Technology

MLR Institute of Technology MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Course Name Course Code Class Branch ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK : DIGITAL DESIGN

More information

Spiral 1 / Unit 4 Verilog HDL. Digital Circuit Design Steps. Digital Circuit Design OVERVIEW. Mark Redekopp. Description. Verification.

Spiral 1 / Unit 4 Verilog HDL. Digital Circuit Design Steps. Digital Circuit Design OVERVIEW. Mark Redekopp. Description. Verification. 1-4.1 1-4.2 Spiral 1 / Unit 4 Verilog HDL Mark Redekopp OVERVIEW 1-4.3 1-4.4 Digital Circuit Design Steps Digital Circuit Design Description Design and computer-entry of circuit Verification Input Stimulus

More information

Chapter 3 Part 2 Combinational Logic Design

Chapter 3 Part 2 Combinational Logic Design University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 3 Part 2 Combinational Logic Design Originals by: Charles R. Kime and Tom

More information

Overview of Verilog Part 1

Overview of Verilog Part 1 University of Wisconsin - Madison ECE/Comp ci 352 Digital ystems Fundamentals Charles R. Kime ection 2 Fall 2001 Chapters 3 and 4 Verilog Part 1 Minor Updates on 11/9/01 are shown in red. Charles Kime

More information

register:a group of binary cells suitable for holding binary information flip-flops + gates

register:a group of binary cells suitable for holding binary information flip-flops + gates 9 차시 1 Ch. 6 Registers and Counters 6.1 Registers register:a group of binary cells suitable for holding binary information flip-flops + gates control when and how new information is transferred into the

More information

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,

More information

N-input EX-NOR gate. N-output inverter. N-input NOR gate

N-input EX-NOR gate. N-output inverter. N-input NOR gate Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It

More information

Contents. Appendix D Verilog Summary Page 1 of 16

Contents. Appendix D Verilog Summary Page 1 of 16 Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3

More information

Chapter 2a: Structural Modeling

Chapter 2a: Structural Modeling Chapter 2a: Structural Modeling Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and FPGAs

More information

FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1]

FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language. Reference: [1] FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: [] FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed

More information

Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28

Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28 99-1 Under-Graduate Project Verilog Simulation & Debugging Tools Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28 ACCESS IC LAB Outline Basic Concept of Verilog HDL Gate Level Modeling

More information

Introduction to Verilog. Garrison W. Greenwood, Ph.D, P.E.

Introduction to Verilog. Garrison W. Greenwood, Ph.D, P.E. Introduction to Verilog Garrison W. Greenwood, Ph.D, P.E. November 11, 2002 1 Digital Design Flow Specification Functional Design Register Transfer Level Design Circuit Design Physical Layout Production

More information

Workshop on Digital Circuit Design in FPGA

Workshop on Digital Circuit Design in FPGA Workshop on Digital Circuit Design in FPGA Session-1 Presented By Mohammed Abdul Kader Assistant Professor, Dept. of EEE, IIUC Email:kader05cuet@gmail.com Website: kader05cuet.wordpress.com The field-programmable

More information

Chapter 2 Using Hardware Description Language Verilog. Overview

Chapter 2 Using Hardware Description Language Verilog. Overview Chapter 2 Using Hardware Description Language Verilog CSE4210 Winter 2012 Mokhtar Aboelaze based on slides by Dr. Shoab A. Khan Overview Algorithm development isa usually done in MATLAB, C, or C++ Code

More information

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1

DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1 DIGITAL LOGIC WITH VHDL (Fall 23) Unit DESIGN FLOW DATA TYPES LOGIC GATES WITH VHDL TESTBENCH GENERATION DESIGN FLOW Design Entry: We specify the logic circuit using a Hardware Description Language (e.g.,

More information

Chap 6 Introduction to HDL (d)

Chap 6 Introduction to HDL (d) Design with Verilog Chap 6 Introduction to HDL (d) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 VERILOG HDL Basic Unit A module Module

More information

EECS150 - Digital Design Lecture 10 Logic Synthesis

EECS150 - Digital Design Lecture 10 Logic Synthesis EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly

More information

Structural Modeling with Verilog

Structural Modeling with Verilog Structural Modeling with Verilog Recall that the ultimate purpose of verilog is that of a modeling language for cirucits. Moreover, verilog supports both structural and behaviorial modeling. structural

More information

LOGIC CIRCUITS. Kirti P_Didital Design 1

LOGIC CIRCUITS. Kirti P_Didital Design 1 LOGIC CIRCUITS Kirti P_Didital Design 1 Introduction The digital system consists of two types of circuits, namely (i) Combinational circuits and (ii) Sequential circuit A combinational circuit consists

More information

Vertex Shader Design II

Vertex Shader Design II The following content is extracted from the paper shown in next page. If any wrong citation or reference missing, please contact ldvan@cs.nctu.edu.tw. I will correct the error asap. This course used only

More information

P-1/26. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU.

P-1/26. Samir Palnitkar. Prentice-Hall, Inc. INSTRUCTOR : CHING-LUNG SU. : P-1/26 Textbook: Verilog HDL 2 nd. Edition Samir Palnitkar Prentice-Hall, Inc. : INSTRUCTOR : CHING-LUNG SU E-mail: kevinsu@yuntech.edu.tw Chapter 4 P-2/26 Chapter 4 Modules and Outline of Chapter 4

More information

MODELING LANGUAGES AND ABSTRACT MODELS. Giovanni De Micheli Stanford University. Chapter 3 in book, please read it.

MODELING LANGUAGES AND ABSTRACT MODELS. Giovanni De Micheli Stanford University. Chapter 3 in book, please read it. MODELING LANGUAGES AND ABSTRACT MODELS Giovanni De Micheli Stanford University Chapter 3 in book, please read it. Outline Hardware modeling issues: Representations and models. Issues in hardware languages.

More information

CSE241 VLSI Digital Circuits Winter Recitation 1: RTL Coding in Verilog

CSE241 VLSI Digital Circuits Winter Recitation 1: RTL Coding in Verilog CSE241 VLSI Digital Circuits Winter 2003 Recitation 1: RTL Coding in Verilog CSE241 R1 Verilog.1 Kahng & Cichy, UCSD 2003 Topic Outline Introduction Verilog Background Connections Modules Procedures Structural

More information

VLSI Design 13. Introduction to Verilog

VLSI Design 13. Introduction to Verilog Last module: Sequential circuit design Design styles This module Synthesis Brief introduction to Verilog Synthesis in the Design Flow Designer Tasks Tools Architect Logic Designer Circuit Designer Define

More information

UNIT V: SPECIFICATION USING VERILOG HDL

UNIT V: SPECIFICATION USING VERILOG HDL UNIT V: SPECIFICATION USING VERILOG HDL PART -A (2 Marks) 1. What are identifiers? Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists

More information

Software Engineering 2DA4. Slides 2: Introduction to Logic Circuits

Software Engineering 2DA4. Slides 2: Introduction to Logic Circuits Software Engineering 2DA4 Slides 2: Introduction to Logic Circuits Dr. Ryan Leduc Department of Computing and Software McMaster University Material based on S. Brown and Z. Vranesic, Fundamentals of Digital

More information

EEL 4783: Hardware/Software Co-design with FPGAs

EEL 4783: Hardware/Software Co-design with FPGAs EEL 4783: Hardware/Software Co-design with FPGAs Lecture 9: Short Introduction to VHDL* Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 What does HDL stand for? HDL is short for Hardware Description

More information

CET ECET CET 486. C. Sisterna Spring 2003

CET ECET CET 486. C. Sisterna Spring 2003 CET 486 586 Hardware Description Language: VHDL Introduction to hardware description languages using VHDL. Techniques for modeling and simulating small digital systems using a VHDL simulator Textbooks

More information

Advanced Digital Design with the Verilog HDL

Advanced Digital Design with the Verilog HDL Copyright 2001, 2003 MD Ciletti 1 Advanced Digital Design with the Verilog HDL M. D. Ciletti Department of Electrical and Computer Engineering University of Colorado Colorado Springs, Colorado ciletti@vlsic.uccs.edu

More information

Design Using Verilog

Design Using Verilog EGC220 Design Using Verilog Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Basic Verilog Lexical Convention Lexical convention are close to C++. Comment // to the of the line. /* to

More information

EECS150 - Digital Design Lecture 10 Logic Synthesis

EECS150 - Digital Design Lecture 10 Logic Synthesis EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but

More information

Digital Systems and Binary Numbers

Digital Systems and Binary Numbers Digital Systems and Binary Numbers ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2018 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outline

More information

Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification

Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA Session One Outline Introducing VHDL

More information

Module 4. Design of Embedded Processors. Version 2 EE IIT, Kharagpur 1

Module 4. Design of Embedded Processors. Version 2 EE IIT, Kharagpur 1 Module 4 Design of Embedded Processors Version 2 EE IIT, Kharagpur 1 Lesson 23 Introduction to Hardware Description Languages-III Version 2 EE IIT, Kharagpur 2 Instructional Objectives At the end of the

More information

TOPIC : Verilog Synthesis examples. Module 4.3 : Verilog synthesis

TOPIC : Verilog Synthesis examples. Module 4.3 : Verilog synthesis TOPIC : Verilog Synthesis examples Module 4.3 : Verilog synthesis Example : 4-bit magnitude comptarator Discuss synthesis of a 4-bit magnitude comparator to understand each step in the synthesis flow.

More information

UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination

More information

ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING. EEM Digital Systems II

ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING. EEM Digital Systems II ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EEM 334 - Digital Systems II LAB 1 - INTRODUCTION TO XILINX ISE SOFTWARE AND FPGA 1. PURPOSE In this lab, after you learn to use

More information

Verilog Design Principles

Verilog Design Principles 16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes

More information

Folding. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall,

Folding. Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, Folding ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2010 ldvan@cs.nctu.edu.tw http://www.cs.nctu.tw/~ldvan/ Outline Introduction Folding Transformation

More information

Online Verilog Resources

Online Verilog Resources EECS 427 Discussion 6: Verilog HDL Reading: Many references EECS 427 F08 Discussion 6 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf it/ pratolo/verilog/verilogtutorial

More information

Chap.3 3. Chap reduces the complexity required to represent the schematic diagram of a circuit Library

Chap.3 3. Chap reduces the complexity required to represent the schematic diagram of a circuit Library 3.1 Combinational Circuits 2 Chap 3. logic circuits for digital systems: combinational vs sequential Combinational Logic Design Combinational Circuit (Chap 3) outputs are determined by the present applied

More information

VHDL. Chapter 1 Introduction to VHDL. Course Objectives Affected. Outline

VHDL. Chapter 1 Introduction to VHDL. Course Objectives Affected. Outline Chapter 1 Introduction to VHDL VHDL VHDL - Flaxer Eli Ch 1-1 Course Objectives Affected Write functionally correct and well-documented VHDL code, intended for either simulation or synthesis, of any combinational

More information

A Brief Introduction to Verilog Hardware Definition Language (HDL)

A Brief Introduction to Verilog Hardware Definition Language (HDL) www.realdigital.org A Brief Introduction to Verilog Hardware Definition Language (HDL) Forward Verilog is a Hardware Description language (HDL) that is used to define the structure and/or behavior of digital

More information

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS

Date Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 09 MULTIPLEXERS OBJECTIVES: To experimentally verify the proper operation of a multiplexer.

More information

Chap 3. Modeling structure & basic concept of Verilog HDL

Chap 3. Modeling structure & basic concept of Verilog HDL Chap 3. Modeling structure & basic concept of Verilog HDL Fall semester, 2016 Prof. Jaeseok Kim School of Electrical & Electronics Eng. Yonsei university jaekim@yonsei.ac.kr Digital System Design 3-1 Chapter

More information

60-265: Winter ANSWERS Exercise 4 Combinational Circuit Design

60-265: Winter ANSWERS Exercise 4 Combinational Circuit Design 60-265: Winter 2010 Computer Architecture I: Digital Design ANSWERS Exercise 4 Combinational Circuit Design Question 1. One-bit Comparator [ 1 mark ] Consider two 1-bit inputs, A and B. If we assume that

More information

Gate level or structural modeling

Gate level or structural modeling Gate level or structural modeling Prerequisites Functioning of basic logic gates and basic understanding of Verilog coding is required. You are suggested to complete the previous unit before starting this

More information

01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2008

01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2008 Introduction to Digital Logic ENGR 34 Computer Architecture Mark L. Chang Fall 28 Acknowledgements Patterson & Hennessy: Book & Lecture Notes Patterson s 997 course notes (U.C. Berkeley CS 52, 997) Tom

More information

Department of Computer Science and Electrical Engineering. Intro to Verilog II

Department of Computer Science and Electrical Engineering. Intro to Verilog II Department of Computer Science and Electrical Engineering Intro to Verilog II http://6004.csail.mit.edu/6.371/handouts/l0{2,3,4}.pdf http://www.asic-world.com/verilog/ http://www.verilogtutorial.info/

More information

Lab 1 Modular Design and Testbench Simulation ENGIN 341 Advanced Digital Design University of Massachusetts Boston

Lab 1 Modular Design and Testbench Simulation ENGIN 341 Advanced Digital Design University of Massachusetts Boston Lab 1 Modular Design and Testbench Simulation ENGIN 341 Advanced Digital Design University of Massachusetts Boston Introduction This lab introduces the concept of modular design by guiding you through

More information

RTL Coding General Concepts

RTL Coding General Concepts RTL Coding General Concepts Typical Digital System 2 Components of a Digital System Printed circuit board (PCB) Embedded d software microprocessor microcontroller digital signal processor (DSP) ASIC Programmable

More information

HW1 Modeling Concepts

HW1 Modeling Concepts HW1 Modeling Concepts Verilog HDL modeling language supports three kinds of modeling styles: gate-level, dataflow, and behavioral. The gate-level and datafow modeling are used to model combinatorial circuits

More information

Vertex Shader Design I

Vertex Shader Design I The following content is extracted from the paper shown in next page. If any wrong citation or reference missing, please contact ldvan@cs.nctu.edu.tw. I will correct the error asap. This course used only

More information

14:332:231 DIGITAL LOGIC DESIGN. Verilog Functions and Tasks

14:332:231 DIGITAL LOGIC DESIGN. Verilog Functions and Tasks 4:332:23 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 203 Lecture #24: Verilog Time Dimension and Test Benches Verilog Functions and Tasks Verilog function

More information

Verilog HDL Introduction

Verilog HDL Introduction EEE3050 Theory on Computer Architectures (Spring 2017) Prof. Jinkyu Jeong Verilog HDL Introduction 2017.05.14 TA 이규선 (GYUSUN LEE) / 안민우 (MINWOO AHN) Modules The Module Concept Basic design unit Modules

More information

Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1

Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis Spring 2007 Lec #8 -- HW Synthesis 1 Logic Synthesis Verilog and VHDL started out

More information

QUESTION BANK FOR TEST

QUESTION BANK FOR TEST CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

More information

EECS150 - Digital Design Lecture 8 - Hardware Description Languages

EECS150 - Digital Design Lecture 8 - Hardware Description Languages EECS150 - Digital Design Lecture 8 - Hardware Description Languages September 19, 2002 John Wawrzynek Fall 2002 EECS150 - Lec08-HDL Page 1 Netlists Design flow What is a HDL? Verilog history examples Outline

More information

CAD for VLSI Design - I. Lecture 21 V. Kamakoti and Shankar Balachandran

CAD for VLSI Design - I. Lecture 21 V. Kamakoti and Shankar Balachandran CAD for VLSI Design - I Lecture 21 V. Kamakoti and Shankar Balachandran Overview of this Lecture Understanding the process of Logic synthesis Logic Synthesis of HDL constructs Logic Synthesis What is this?

More information

LAB K Basic Verilog Programming

LAB K Basic Verilog Programming LAB K Basic Verilog Programming Perform the following groups of tasks: LabK1.v 1. Create a directory to hold the files of this lab. 2. Launch your favourite editor and a command-prompt console; you will

More information

Lab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog

Lab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog Lab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work

More information

ECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016

ECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016 ECE 353 Lab 4 Verilog Review Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016 Recall What You Will Do Design and implement a serial MIDI receiver Hardware in

More information

Introduction to VHDL. Main language concepts

Introduction to VHDL. Main language concepts Introduction to VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Current standard is IEEE 1076-1993 (VHDL-93). Some tools still only support VHDL-87. Tools used in the lab

More information

EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1

EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references. EECS 427 W07 Lecture 14 1 EECS 427 Lecture 14: Verilog HDL Reading: Many handouts/references EECS 427 W07 Lecture 14 1 Online Verilog Resources ASICs the book, Ch. 11: http://www.ge.infn.it/~pratolo/verilog/verilogtutorial.pdf

More information

ECE UMass, Amherst. Verilog tutorial

ECE UMass, Amherst. Verilog tutorial ECE 232 - UMass, Amherst Verilog tutorial 1. In this tutorial, we are going to design and implement a 2-bit comparator in Verilog and simulate it using the service provided on www.edaplayground.com. In

More information