# 2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. K-Maps Can Identify Single-Gate Functions

Size: px
Start display at page:

Download "2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. K-Maps Can Identify Single-Gate Functions"

Transcription

1 University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Two-Level Logic SOP Form Gives Good Performance s you know, one can use a K-map to obtain an SOP form. If one chooses a minimal number of loops of maximal size the resulting SOP form has optimal area* ut what about speed? The speed of an SOP form is typically optimal. *See caveats in slides on K-maps. ECE 120: Introduction to Computing Steven S. Lumetta. ll rights reserved. slide 1 ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 2 The est Case is One Gate Delay* Recall our delay heuristic: the number of gate delays from any input. Let s assume that complemented literals are available with no delay. What can we express with one gate delay in CMOS? Only NND and NOR (NOT is a 1-input NND/NOR). *Ignoring the functions 0 and 1 and functions consisting of a single literal, all of which have zero gate delays. K-Maps Can Identify Single-Gate Functions single NND is an SOP expression.* So is a single NOR. n expression using a single gate is also optimal by our area heuristic. So if a function can be built with a single gate, the K-map will give us that expression. *nd a POS expression. ECE 120: Introduction to Computing Steven S. Lumetta. ll rights reserved. slide 3 ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 4

2 Is Counting ND/OR Gates Realistic? Most functions cannot be expressed as a single NND/NOR gate. So how fast is an SOP expression? Two gate delays. ND, followed by OR. ut in CMOS, we only have NND and NOR. How many gate delays do we get if we only use NND/NOR? Let s Introduce Some lgebra little oolean algebra will help us: DeMorgan s Laws () = + (+) = Want a proof? Use a truth table (4 lines each). They also generalize to more than two inputs. For example, (C) = + + C (++C) = C ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 5 ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 6 DeMorgan s Laws Relate NND/NOR to ND/OR What do DeMorgan s Laws mean? Here s one way to think about them: () = + NND is the same as OR on the complements of the inputs. (+) = NOR is the same as ND on the complements of the inputs. Graphical Representation Can e Useful, Too Let s also think about them graphically. Complement both sides first, so we have = ( + ) + = ( ) and now we can draw gates ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 7 ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 8

3 How Do We Draw an SOP Form? ND, then OR What were we talking about? h, speed of SOP forms. SOP is ND followed by OR. Something like this (with some number of ND gates, each with some number of inputs) pply DeMorgan s Laws Graphically Replace it with a NND ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 9 ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 10 pply DeMorgan s Laws Graphically Replace it with a NND Remember that the input bubbles mean inverters (NOT). Now slide them down the wires to the left until they sit in front of the NDs. pply DeMorgan s Laws Graphically Replace it with a NND Remember that the input bubbles mean inverters (NOT). Now slide them down the wires to the left until they sit in front of the NDs. ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 11 ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 12

4 SOP Form Speed is Two Gate Delays We didn t change the function of the circuit. ut now all of the gates are NND gates. So we can build any SOP function using two levels of NND. nd the speed? Two gate delays. SOP and POS Forms Give Us Two-Level Logic We can use two levels of NNDs to build any SOP expression. We refer to this approach as two-level logic. For a POS expression one can do exactly the same thing replacing OR followed by ND with NOR followed by NOR. So any POS expression also requires two gate delays (again, assuming that complemented inputs are free). ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 13 ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 14 Use a K-Map to Find POS Expressions ut how can we find a POS form? gain, use a K-map. 1. Given a function F, draw a K-map for F. 2. Use K-map to find an SOP form for F. 3. Complement the result to find F and apply DeMorgan s laws a few times, complement of SOP form is POS form. In Practice, Form Loops round 0s to Find POS In practice, just circle 0s instead of 1s. Recall that a box in a K-map when filled with a 1 corresponds to a minterm. The same box when filled with a 0 corresponds to a maxterm an expression that produces exactly one 0 row in its truth table. ECE 120: Introduction to Computing Steven S. Lumetta. ll rights reserved. slide 15 ECE 120: Introduction to Computing Steven S. Lumetta. ll rights reserved. slide 16

5 Complement Literals When Reading POS Factors ut be careful: the maxterm has all variables complemented relative to the minterm. For example, a box corresponding to minterm C (equal to 1 when =1 and =1 and C=0) corresponds to maxterm + + C (equal to 0 when =1 and =1 and C=0) SOP and POS Forms Give Us Two-Level Logic To find a POS form that has optimal area (among POS forms), follow the same approach as before, but instead of drawing loops around 1s, draw loops around 0s. gain, do not forget to complement the literals relative to their form for implicants! (nd write each loop as a sum, not as a product.) ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 17 ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 18 Which Form is etter? Solve oth and Compare Which gives better area, SOP or POS? That depends on the function. Solve both ways and compare. You will have some experience finding POS forms in discussion section. You can also use the online tool, but the exercises are not as direct as for SOP. ECE 120: Introduction to Computing 2016 Steven S. Lumetta. ll rights reserved. slide 19

### 9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing To Simplify, Write Function as a Sum of Prime Implicants One way to simplify a

### 9/10/2016. The Dual Form Swaps 0/1 and AND/OR. ECE 120: Introduction to Computing. Every Boolean Expression Has a Dual Form

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Boolean Properties and Optimization The Dual Form Swaps 0/1 and AND/OR Boolean

### Standard Forms of Expression. Minterms and Maxterms

Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:

### Chapter 2. Boolean Expressions:

Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean

### Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of

### Lecture 7 Logic Simplification

Lecture 7 Logic Simplification Simplification Using oolean lgebra simplified oolean expression uses the fewest gates possible to implement a given expression. +(+)+(+) Simplification Using oolean lgebra

### Digital Fundamentals

Digital Fundamentals Tenth Edition Floyd Chapter 3 Modified by Yuttapong Jiraraksopakun Floyd, Digital Fundamentals, th 28 Pearson Education ENE, KMUTT ed 29 The Inverter Summary The inverter performs

### Experiment 3: Logic Simplification

Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions

### 7/25/2016. Example: Addition of Unsigned Bit Patterns. ECE 120: Introduction to Computing. Adding Two Non-Negative Patterns Can Overflow

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing 2 s Complement Overflow and Boolean Logic Example: ddition of Unsigned Bit Patterns

### Chapter 2 Part 4 Combinational Logic Circuits

University of Wisconsin - Madison EE/omp Sci 352 Digital Systems undamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 hapter 2 Part 4 ombinational Logic ircuits Originals by: harles R. Kime and Tom Kamisnski

### Digital Logic Design (3)

Digital Logic Design (3) ENGG1015 1 st Semester, 2010 Dr. Kenneth Wong Dr. Hayden So Department of Electrical and Electronic Engineering Last lecture ll logic functions can be represented as (1) truth

### ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

### Menu. Algebraic Simplification - Boolean Algebra EEL3701 EEL3701. MSOP, MPOS, Simplification

Menu Minterms & Maxterms SOP & POS MSOP & MPOS Simplification using the theorems/laws/axioms Look into my... 1 Definitions (Review) Algebraic Simplification - Boolean Algebra Minterms (written as m i ):

### 10/5/2016. Review of General Bit-Slice Model. ECE 120: Introduction to Computing. Initialization of a Serial Comparator

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Example of Serialization Review of General Bit-Slice Model General model parameters

### ECE380 Digital Logic

ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For

### ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

### Chapter 3. Gate-Level Minimization. Outlines

Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

### Announcements. Chapter 2 - Part 1 1

Announcements If you haven t shown the grader your proof of prerequisite, please do so by 11:59 pm on 09/05/2018 (Wednesday). I will drop students that do not show us the prerequisite proof after this

### Midterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil

Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final

### ECE199JL: Introduction to Computer Engineering Fall 2012 Notes Set 2.4. Example: Bit-Sliced Comparison

c 22 Steven S. Lumetta. ll rights reserved. 2 EE99JL: Introduction to omputer Engineering Fall 22 Notes Set 2.4 Eample: it-sliced omparison This set of notes develops s for unsigned and 2 s complement

### Logic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 3 Additional Gates and Circuits

Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View

### QUESTION BANK FOR TEST

CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

### Learning Objectives: Topic Karnaugh Maps. At the end of this topic you will be able to;

Topic.2.3 Karnaugh Maps Learning Objectives: t the end of this topic you will be able to; Draw a Karnaugh map for a logic system with up to four inputs and use it to minimise the number of gates required;

### CprE 281: Digital Logic

CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative

### CMPE223/CMSE222 Digital Logic

CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Terminology For a given term, each

### ece5745-pla-notes.txt

ece5745-pla-notes.txt ========================================================================== Follow up on PAL/PROM/PLA Activity ==========================================================================

### Boolean algebra. June 17, Howard Huang 1

Boolean algebra Yesterday we talked about how analog voltages can represent the logical values true and false. We introduced the basic Boolean operations AND, OR and NOT, which can be implemented in hardware

### EECS150 Homework 2 Solutions Fall ) CLD2 problem 2.2. Page 1 of 15

1.) CLD2 problem 2.2 We are allowed to use AND gates, OR gates, and inverters. Note that all of the Boolean expression are already conveniently expressed in terms of AND's, OR's, and inversions. Thus,

### Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to

### Section 001. Read this before starting! You may use one sheet of scrap paper that you will turn in with your test.

Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Fall Semester,

### 12/2/2016. Error Detection May Not Be Enough. ECE 120: Introduction to Computing. Can We Use Redundancy to Correct Errors?

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Error Correction, Hamming Codes, and SEC-DED Codes Error Detection May Not Be

### Logic Design (Part 2) Combinational Logic Circuits (Chapter 3)

Digital Logic Circuits Logic Design (Part ) Combinational Logic Circuits (Chapter 3) ² We saw how we can build the simple logic gates using transistors ² Use these gates as building blocks to build more

### LECTURE 4. Logic Design

LECTURE 4 Logic Design LOGIC DESIGN The language of the machine is binary that is, sequences of 1 s and 0 s. But why? At the hardware level, computers are streams of signals. These signals only have two

### 2.6 BOOLEAN FUNCTIONS

2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses

### Digital Logic Lecture 7 Gate Level Minimization

Digital Logic Lecture 7 Gate Level Minimization By Ghada Al-Mashaqbeh The Hashemite University Computer Engineering Department Outline Introduction. K-map principles. Simplification using K-maps. Don t-care

### Boolean logic. Boolean Algebra. Introduction to Computer Yung-Yu Chuang NOT AND NOT

oolean lgebra oolean logic ased on symbolic logic, designed by George oole oolean variables take values as or. oolean expressions created from: NOT, ND, OR Introduction to Computer ung-u Chuang with slides

### University of Technology

University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows

### LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a

### Experiment 4 Boolean Functions Implementation

Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.

### There are only 16 possible 2-input gates Let s examine all of them. Some we already know, others are just silly.

ll the Gates There are only 6 possible 2-input gates Let s examine all of them. Some we already know, others are just silly. Do we really need all of these gates? How many of these gates can be implemented

### Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples

Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2-Level Transformation Review Boolean Cube Karnaugh-Map Representation and Methods Examples Incompletely specified functions

### 10/30/2016. How Do We Write Instructions? ECE 120: Introduction to Computing. Put Bits into Memory, Then Execute the Bits

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Instructions Illustrated How Do We Write Instructions? Previously, we looked at

### 10/27/2016. ECE 120: Introduction to Computing. The LC-3 Memory is Bit. Recall the Five Parts of the von Neumann Model

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing LC-3 as a von Neumann Machine Build an LC-3 Processor as a von Neumann Machine

### IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

### ENGIN 112. Intro to Electrical and Computer Engineering

ENIN 2 Intro to Electrical and Computer Engineering Lecture 6 More Boolean Algebra ENIN2 L6: More Boolean Algebra September 5, 23 A B Overview Epressing Boolean functions Relationships between algebraic

### 8/27/2016. ECE 120: Introduction to Computing. Graphical Illustration of Modular Arithmetic. Representations Must be Unambiguous

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Signed Integers and 2 s Complement Strategy: Use Common Hardware for Two Representations

### 1. Mark the correct statement(s)

1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another

### Digital Circuits ECS 371

Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 7 Office Hours: KD 36-7 Monday 9:-:3, :3-3:3 Tuesday :3-:3 Announcement HW2 posted on the course web site Chapter 4: Write down

### Combinational Logic Circuits

Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical

### 2/5/2018. Learn Four More Kinds of C Statements. ECE 220: Computer Systems & Programming. C s if Statement Enables Conditional Execution

2/5/218 University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 22: Computer Systems & Programming Control Constructs in C (Partially a Review) Learn Four More Kinds

### 8/30/2016. In Binary, We Have A Binary Point. ECE 120: Introduction to Computing. Fixed-Point Representations Support Fractions

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Fixed- and Floating-Point Representations In Binary, We Have A Binary Point Let

### Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic

Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying

### ENGIN 112 Intro to Electrical and Computer Engineering

ENGIN 2 Intro to Electrical and Computer Engineering Lecture 8 Minimization with Karnaugh Maps Overview K-maps: an alternate approach to representing oolean functions K-map representation can be used to

### Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide

### DKT 122/3 DIGITAL SYSTEM 1

Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits

### Philadelphia University Faculty of Information Technology Department of Computer Science. Computer Logic Design. By Dareen Hamoudeh.

Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By Dareen Hamoudeh Dareen Hamoudeh 1 Canonical Forms (Standard Forms of Expression) Minterms

### Review: Standard forms of expressions

Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and NOT. These operations can be combined to form complex expressions, which can

### Chap-2 Boolean Algebra

Chap-2 Boolean Algebra Contents: My name Outline: My position, contact Basic information theorem and postulate of Boolean Algebra. or project description Boolean Algebra. Canonical and Standard form. Digital

### BOOLEAN ALGEBRA. 1. State & Verify Laws by using :

BOOLEAN ALGEBRA. State & Verify Laws by using :. State and algebraically verify Absorption Laws. (2) Absorption law states that (i) X + XY = X and (ii) X(X + Y) = X (i) X + XY = X LHS = X + XY = X( + Y)

### Combinational Circuits Digital Logic (Materials taken primarily from:

Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a

### 9/3/2016. ECE 120: Introduction to Computing. Few Programmers Write Instructions (Assembly Code) Spend a Week Learning the C Programming Language

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Introduction to the C Programming Language Few Programmers Write Instructions

### S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017

S1 Teknik Telekomunikasi Fakultas Teknik Elektro FEH2H3 2016/2017 Karnaugh Map Karnaugh maps Last time we saw applications of Boolean logic to circuit design. The basic Boolean operations are AND, OR and

### At this point in our study of digital circuits, we have two methods for representing combinational logic: schematics and truth tables.

HPTER FIVE oolean lgebra 5.1 Need for oolean Expressions t this point in our study of digital circuits, we have two methods for representing combinational logic: schematics and truth tables. 0 0 0 1 0

### Identity. p ^ T p p _ F p. Idempotency. p _ p p p ^ p p. Associativity. (p _ q) _ r p _ (q _ r) (p ^ q) ^ r p ^ (q ^ r) Absorption

dam lank pring 27 E 3 Identity Pre-Lecture Problem Do it! Do it now! What are you waiting for?! Use Logical Equivalences to show!! \$! & & \$! p ^ T p p _ F p Domination p _ T T p ^ F F Idempotency p _ p

### (Refer Slide Time 6:48)

Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 8 Karnaugh Map Minimization using Maxterms We have been taking about

### Simplification of Boolean Functions

COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean

### Chapter 6. Logic Design Optimization Chapter 6

Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is

### Specifying logic functions

CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last

### Gate Level Minimization

Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =

### Chapter 2: Combinational Systems

Uchechukwu Ofoegbu Chapter 2: Combinational Systems Temple University Adapted from Alan Marcovitz s Introduction to Logic and Computer Design Riddle Four switches can be turned on or off. One is the switch

### Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions

Assignment (3-6) Boolean Algebra and Logic Simplification - General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make

### Lecture 5. Chapter 2: Sections 4-7

Lecture 5 Chapter 2: Sections 4-7 Outline Boolean Functions What are Canonical Forms? Minterms and Maxterms Index Representation of Minterms and Maxterms Sum-of-Minterm (SOM) Representations Product-of-Maxterm

### Lecture 4: Implementation AND, OR, NOT Gates and Complement

EE210: Switching Systems Lecture 4: Implementation AND, OR, NOT Gates and Complement Prof. YingLi Tian Feb. 13, 2018 Department of Electrical Engineering The City College of New York The City University

### 2/5/2018. Expressions are Used to Perform Calculations. ECE 220: Computer Systems & Programming. Our Class Focuses on Four Types of Operator in C

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 220: Computer Systems & Programming Expressions and Operators in C (Partially a Review) Expressions are Used

### CS February 17

Discrete Mathematics CS 26 February 7 Equal Boolean Functions Two Boolean functions F and G of degree n are equal iff for all (x n,..x n ) B, F (x,..x n ) = G (x,..x n ) Example: F(x,y,z) = x(y+z), G(x,y,z)

### 10/24/2016. We Can Perform Any Computation with an FSM. ECE 120: Introduction to Computing. Find the Minimum Value Among Ten Integers

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing From FSM to Computer We Can Perform Any Computation with an FSM Let s build an

### Chapter 2 Boolean algebra and Logic Gates

Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions

### 9/10/2016. Time for Some Detailed Examples. ECE 120: Introduction to Computing. Let s See How This Loop Works. One Statement/Step at a Time

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Examples of C Programs with Loops Time for Some Detailed Examples Let s do some

### Gate Level Minimization Map Method

Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically

### 211: Computer Architecture Summer 2016

211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic - Storage: Recap - Direct - Mapping - Fully Associated - 2-way Associated - Cache Friendly Code Rutgers University Liu

### Lecture 7. Summary of two-level combinational-logic. Ways of specifying circuits. Solving combinational design problems. Verilog versus VHDL

Lecture 7 Summary of two-level combinational-logic Logistics Homework due today Homework out today due next Wednesday First midterm a week Friday: Friday Jan 0 Will cover up to the of Multiplexers/DeMultiplexers

### Gate-Level Minimization. section instructor: Ufuk Çelikcan

Gate-Level Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to

Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse

### 1/29/2018. Starting a Program Executes its main Function. ECE 220: Computer Systems & Programming. The Function main Divides into Two Parts

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 220: Computer Systems & Programming Starting a Program Executes its main Function Let s take a look at a C program

### ECE199JL: Introduction to Computer Engineering Fall 2012 Notes Set 2.1. Optimizing Logic Expressions

c 22 teven. Lumetta. ll rights reserved. EE99JL: Introduction to omputer Engineering Fall 22 Notes et 2. Optimizing Logic Expressions The second part of the course covers digital design more deeply than

### UNIT-4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.

UNIT-4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?

### Bawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University

Logic Design First Stage Lecture No.5 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Boolean Operations Laws of Boolean Algebra Rules of Boolean Algebra

### 10/24/2016. Let s Name Some Groups of Bits. ECE 120: Introduction to Computing. We Just Need a Few More. You Want to Use What as Names?!

University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Memory Let s Name Some Groups of Bits I need your help. The computer we re going

### Variable, Complement, and Literal are terms used in Boolean Algebra.

We have met gate logic and combination of gates. Another way of representing gate logic is through Boolean algebra, a way of algebraically representing logic gates. You should have already covered the

### Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization

### Module -7. Karnaugh Maps

1 Module -7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or Sum-of-Minterms (SOM) 2.4 Canonical product of sum or Product-of-Maxterms(POM)

### Designing Computer Systems Boolean Algebra

Designing Computer Systems Boolean Algebra 08:34:45 PM 4 June 2013 BA-1 Scott & Linda Wills Designing Computer Systems Boolean Algebra Programmable computers can exhibit amazing complexity and generality.

### Combinational Logic & Circuits

Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other

### Lecture 22: Implementing Combinational Logic

8 Lecture 22: Implementing ombinational Logic S 5 L22 James. Hoe Dept of EE, MU April 9, 25 Today s Goal: Design some combinational logic circuits Announcements: Read Rizzoni 2.4 and 2.5 HW 8 due today

### Gate-Level Minimization

Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

### Optimized Implementation of Logic Functions

June 25, 22 9:7 vra235_ch4 Sheet number Page number 49 black chapter 4 Optimized Implementation of Logic Functions 4. Nc3xe4, Nb8 d7 49 June 25, 22 9:7 vra235_ch4 Sheet number 2 Page number 5 black 5 CHAPTER

### Objectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure

Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification:

### Unit-IV Boolean Algebra

Unit-IV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of