# Combinational Circuits

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1 Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables come from a source for which m output variables are produced by the combinational logic go to a destination Typically the source and destination are storage registers If registers are included then the circuit is considered to be sequential 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 1

2 Combinational Circuits For n input variables there are 2 n possible combinations of the binary inputs For each possible input combination there is one possible value for each output variable A combinational circuit can be specified with a truth table that lists the output values for each combination of input variables A combinational circuit also can be described by m Boolean functions, one for each output variable Each output function is expressed in terms of the n input variables 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 2

3 Combinational Circuits Have learned: Binary numbers and binary codes that represent discrete quantities of information Boolean algebra as a way to express logic functions algebraically Simplify Boolean functions to achieve economical (simpler) gate implementations Will now formulate systematic analysis and design procedures for combinational circuits Will build a useful catalog of elementary functions that are important for the understanding of digital systems 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 3

4 Analysis Procedure To analyze a combinational circuit we need to determine the function that the circuit implements First make sure that the given circuit is combinational and not sequential No feedback or memory elements Inspect the logic diagram and then create a set of Boolean functions, a truth table, or an explanation of the circuit operation If we are told what the function does then the analysis problem reduces to just verification 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 4

5 Analysis Procedure To obtain the output Boolean functions from a logic diagram: 1. Label all gate outputs that are a function of input variables with arbitrary symbols 2. Determine the Boolean functions for each gate output 3. Label the gates that are a function of previously labeled gates with other arbitrary symbols 4. Find the Boolean functions for these gates 5. Repeat steps 3 to 4 until the outputs of the circuit are obtained 6. By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 5

6 Analysis Procedure: Example T 4 = AB T 5 = AC T 6 = BC T 1 = A + B + C T 2 = ABC F 2 = T 4 + T 5 + T 6 T 3 = F' 2 T 1 F 1 = T 3 + T 2 = F' 2 T 1 + ABC = A'BC' + A'B'C + AB'C' + ABC 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 6

7 Analysis Procedure: Example 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 7

8 Design Procedure Steps required: 1. From the specifications, determine the required number of inputs and outputs Assign a symbol to each 2. Derive the truth table that defines the required relationship between inputs and outputs 3. Obtain the simplified Boolean functions for each output as a function of the input variables 4. Draw the logic diagram and verify the correctness of the design Manually or by simulation 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 8

9 Design Procedure: Example Convert binary coded decimal (BCD) to excess-3 code Input variables: A, B, C, & D Output variables: w, x, y, & z 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 9

10 Design Procedure: Example x = B'C + B'D + BC'D' = B'(C + D) + BC'D' = B'(C + D) + B(C + D)' w = A + BC + BD = A + B(C + D) 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 10

11 Design Procedure: Example z = D' y = CD + C'D' = CD + (C + D)' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 11

12 Design Procedure: Example 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 12

13 Binary Adder - Half Adder Addition of 2 bits Sum: S = x'y + xy' or S = x y Carry: C = xy 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 13

14 Binary Adder - Full Adder Full adder is required for n-bit binary numbers After the least significant bit (where only 2 bits are added), addition needs to consider the carry (3 total bits) Resulting carry is passed onto next fulladder 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 14

15 Binary Adder - Full Adder 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 15

16 Binary Adder - Full Adder Can be implemented with 2 HAs and an OR gate: S = z ( x y ) C = ( x y ) z + xy 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 16

17 Binary Adder Binary adder can add 2 n- bit binary numbers Cascade n FAs where each carry feeds into next FA Ripple Carry Slow carry propagation 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 17

18 Binary Adder - Carry Lookahead P i = A i B i G i = A i B i G i is carry generate P i is carry propagate S i = P i C i C i+1 = G i + P i C i C 0 = input carry C 1 = G 0 + P 0 C 0 C 2 = G 1 + P 1 C 1 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 C 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C Roberto Muscedere Images 2013 Pearson Education Inc. 18

19 Binary Adder - Carry Lookahead 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 19

20 Binary Adder - Carry Lookahead 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 20

21 Binary Subtraction Subtraction of unsigned binary numbers can be done by using complements A - B is done by taking the 2's complement of B and adding it to A 2's complement can be obtained by taking the 1's complement and adding 1 1's complement can be implemented with inverters 1 can be added to the sum through the input carry Addition and subtraction operations can be combined into one circuit (for both signed and unsigned values) 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 21

22 Binary Subtraction Input M controls the operation: When M = 0, the circuit is an adder Input is B M = B 0 = B, C 0 = M = 0 When M = 1, the circuit is a subtractor Input is B M = B 1 = B', C 0 = M = 1 Output V is for detecting an overflow 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 22

23 Binary Addition/Subtraction: Overflow When two numbers with n digits are added and the sum is a number occupying n+1 digits, then an overflow occurred Problem since we have finite storage With unsigned numbers an overflow is detected by looking at the carry out With signed numbers, an overflow may occur if the two numbers added are both positive or both negative Determine by looking at 2 upper most carries, if they are different, overflow occurred 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 23

24 BCD Adder Example Addition of two decimal digits in BCD and an input carry Each input digit and output digits don't exceed 9 ie = 19 (both 1's are in and out carry respectively) Apply two BCD digits to a four-bit binary adder Sum ranges from 0 through 19, in output Z and carry K Apply a correction to Z to generate the proper BCD representation in output S When Z is greater than 9, add 6 to Z with another adder 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 24

25 BCD Adder Example 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 25

26 BCD Adder Example When Z is greater than 9, we also have a carry, C, to forward to next adder C = K + Z 8 Z 4 + Z 8 Z 2 Multiply C by 6 and add to Z to get proper BCD sum S 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 26

27 Binary Multiplier Done the same way as decimal numbers Multiplicand (B) is multiplied by each bit of the multiplier (A) starting from the LSB Each such multiplication forms a partial product Successive partial products are shifted one position to the left Sum up the partial products 2-bit multiplier shown One bit multiplication is an AND operation Partial products can be implemented with AND gates Partial products are added with two halfadders 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 27

28 Binary Multiplier In general a bit of the multiplier (A) is ANDed with each bit of the multiplicand (B) in as many levels as there are bits in the multiplier The binary output in each level of AND gates is added with the partial product of the previous level to form a new partial product The last level produces the product For J multiplier bits and K multiplicand bits, we need (J * K) AND gates and (J -1) K-bit adders to produce a product of (J + K) bits 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 28

29 Binary Multiplier: Example K = 4 and J = 3 Multiplicand: (B 3 B 2 B 1 B 0 ) Multiplier: (A 2 A 1 A 0 ) Needs 12 AND gates and two 4- bit adders to produce a product of seven bits 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 29

30 Magnitude Comparator Magnitude comparator compares two numbers A and B and determines their relative magnitudes A > B, A = B, or A < B For comparing two n-bit numbers, truth table has 2 2n entries Circuit possesses a certain amount of regularity Can be designed by means of an algorithm x i = A i B i + A' i B' i = (A i B i )' (i = 0 for LSB) (A=B) = x n-1 x n-2...x 1 x 0 (A>B) = A n-1 B' n-1 +x n-1 A n-2 B' n x n-1...x 2 A 1 B' 1 +x n-1...x 1 A 0 B' 0 (B>A) = A' n-1 B n-1 +x n-1 A' n-2 B n x n-1...x 2 A' 1 B 1 +x n-1...x 1 A' 0 B Roberto Muscedere Images 2013 Pearson Education Inc. 30

31 Magnitude Comparator Gate implementation is simpler as it involves a certain amount of repetition x i generated with exclusive-nor > and < can use internal XNOR values to further simplify implementation Can simplify further: (A<=B)=(A<B)+(A=B) (A>B)=(A<=B)' (A>B)=((A<B)+(A=B))' (A>B)=(A<B)'(A=B)' 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 31

32 Decoders A binary code of n bits is capable of representing up to 2 n distinct elements of coded information A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines If the n-bit coded information has unused combinations, the decoder may have fewer outputs Called n-to-m-line decoders, where m <= 2 n They generate 2 n (or fewer) minterms of n input variables Each combination of inputs will assert a unique output 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 32

33 Decoders: Example 3-to3 to-8 Three inputs are decoded into eight outputs, each representing one of the minterms of the three input variables Inverters provide the complement of the inputs AND gates generates one of the minterms 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 33

34 Decoders: NAND Implementation Decoders can be constructed with NAND gates Output in complement form because of NAND Can include one or more enable inputs (/E) to control the circuit operation 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 34

35 Decoders Decoders with enable inputs can be connected together to form a larger decoder circuit Two 3-to-8-line decoders (w/ enable) form a 4-to-16-line decoder When w=0, the top decoder is enabled (outputs generate minterms 0000 to 0111) and the other is disabled (outputs all 0's) When w=1, the top decoder is disabled (outputs all 0's) and the other is enabled (outputs generate minterms 1000 to 1111) Demonstrates the usefulness of enable inputs in decoders and other combinational logic components 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 35

36 Decoders: Function Implementation Decoder provides the 2 n minterms of n input variables Each output is associated with a unique pattern of input bits Adding an OR gate to a decoder allows any Boolean function (in sum-of-minterms form) to be implemented Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n - line decoder and m OR gates Example: S(x, y, z) = (1, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7) 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 36

37 Encoders An encoder is a digital circuit that performs the inverse operation of a decoder An encoder has 2 n (or fewer) input lines and n output lines The output lines generate the binary code corresponding to the input value It is assumed that only one input has a value of 1 at any given time Otherwise the output produces an undefined combination Eg. When all inputs 0, output is 0 Can be implemented with OR gates whose inputs are determined directly from the truth table 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 37

38 Encoders: Octal-to to-binary Example Can be expressed by the following Boolean output functions (ORs only): z = D 1 + D 3 + D 5 + D 7 y = D 2 + D 3 + D 6 + D 7 x = D 4 + D 5 + D 6 + D Roberto Muscedere Images 2013 Pearson Education Inc. 38

39 Priority Encoder A priority encoder solves the encoders undefined combination situations by ignoring inputs less than the placement of the most significant 1 Valid indicator, V, is set when one or more inputs are equal to 1, otherwise it is 0 If not set, other outputs should not be inspected X's in the input columns represent the truth table in condensed form Don't have to list all 16 minterms 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 39

40 Priority Encoder V is an OR of all inputs Inputs, XX10 for example, represent 0010, 0110, 1010, and Roberto Muscedere Images 2013 Pearson Education Inc. 40

41 Multiplexers Multiplexer is a circuit that selects binary information from one of many input lines and directs it to a single output line Selection is controlled by a set of selection lines There are 2 n input lines and n selection lines whose bit combinations determine which input is selected Two-to-one-line multiplexer connects one of two sources to a common destination When S = 0, the upper AND gate is enabled and I 0 goes to the output When S = 1, the lower AND gate is enabled and I 1 goes to the output 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 41

42 Multiplexers Four-to-one-line multiplexer shown Function table lists the input that is passed to the output for each combination of the binary selection values Also called a data selector Multiplexer resemble a decoder since they decode the selection input lines and AND it with the data 2 n -to-1-line multiplexer is constructed from an n-to-2 n decoder by adding 2 n input lines to it, one to each AND gate Outputs of the AND gates are applied to a single OR gate May have an enable input to control the operation of the unit 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 42

43 Multiplexers Multiplexer can be combined with common selection inputs to provide multiple-bit selection logic Quadruple (or 4-bit) 2-to-1- line multiplexer shown Four multiplexers, each capable of selecting one of two input lines When E=0 and S=0, Y=A When E=0 and S=1, Y=B When E=1, Y=all 0's 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 43

44 Multiplexers: Function Implementation Multiplexer is essentially a decoder (minterms generated by selection inputs) that includes the final OR gate Minterms can be selected by the data inputs, thereby providing a method of implementing a Boolean function of n variables with a multiplexer with n-1 selection inputs and 2 n-1 data inputs General procedure for implementing: 1. Generate truth table of Boolean function 2. First n-1 variables in the table are applied to the selection inputs 3. Evaluate the output as a function of the last variable for each combination of the selection variables This function can be 0, 1, the variable, or the complement of the variable 4. Values are then applied to the data inputs in the proper order 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 44

45 Multiplexers: Function Implementation F (x, y, z) = (1, 2, 6, 7) Function of three variables can be implemented with a four-to-one-line multiplexer x, and y connected to inputs S 1, and S 0, respectively When xy=00 then F=z When xy=01 then F=z' When xy=10 then F=0 When xy=11 then F= Roberto Muscedere Images 2013 Pearson Education Inc. 45

46 Multiplexers: Function Implementation F(A,B,C,D) = (1,3,4,11,12,13,14, 15) A, B, and C connected to inputs S 2, S 1, and S 0, respectively When ABC=000, 001, and 101 then F=D When ABC=010 then F=D' When ABC=011, and 100 then F=0 When ABC=110, and 111 then F= Roberto Muscedere Images 2013 Pearson Education Inc. 46

47 Three-state or Tri-state Gate Three-state or tri-state gate is a digital circuit that exhibits three states Two are 1 and 0, but the third state is a high-impedance state or an open circuit Graphic symbol shown below Like a normal buffer but has an input control line entering the bottom When the control input, C, is 1, the gate acts like a buffer When C is 0, the output is disabled by going to a highimpedance state Large number of three-state gate outputs can be connected together 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 47

48 Multiplexers: Three-state or Tri-state Implementation Multiplexers can be made with three-state buffers Two-to-one-line multiplexer with 2 three-state buffers The two outputs are connected together to form a single output line Four-to-one-line multiplexer with 4 three-state buffers Decoder ensures no more than one three-state buffer may be in the active at any given time When the enable of the decoder is 0, all of its four outputs are 0 then this circuit is not driving Y Y can be driven by more than one circuit, but only one can be active 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 48

49 Decoders: Demultiplexer Implementation A decoder with enable input can function as a demultiplexer Circuit that receives information from a single line and directs it to one of 2 n possible output lines Decoder can function as a one-to-four-line demultiplexer E is data input line and A and B are taken as the selection inputs Decoder and demultiplexer operations are taken from the same circuit Decoder with an enable input is referred to as a decoder demultiplexer 2018 Roberto Muscedere Images 2013 Pearson Education Inc. 49

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