211: Computer Architecture Summer 2016

Transcription

1 211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic

2 - Storage: Recap - Direct - Mapping - Fully Associated - 2-way Associated - Cache Friendly Code Rutgers University Liu Liu 2

3 - Storage: Today s Topic - Review: cache hit rate - Project3 - Digital Logic: - Review: cache hit rate - Project3 Rutgers University Liu Liu 3

4 Matrix Multiplication (ijk) /* ijk */ for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; } } Inner loop: (*,j) (i,j) (i,*) A B C Row-wise Columnwise Fixed Misses per Inner Loop Iteration: A B C Rutgers University Liu Liu 4

5 /* ijk */ for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; } } Matrix Multiplication (ijk) sum+=a[0][0] * b[0][0];//what data been loaded to cache? sum+=a[0][1] * b[1][0]; sum+=a[0][2] * b[2][0]; sum+=a[0][3] * b[3][0]; sum+=a[0][4] * b[4][0]; sum+=a[0][5] * b[5][0]; sum+=a[0][6] * b[6][0]; sum+=a[0][7] * b[7][0];//first K loop ends c[0][0] = sum; sum+=a[0][0] * b[0][1];//what data been loaded to cache? sum+=a[0][1] * b[1][1]; sum+=a[0][2] * b[2][1]; sum+=a[0][3] * b[3][1]; sum+=a[0][4] * b[4][1]; sum+=a[0][5] * b[5][1]; sum+=a[0][6] * b[6][1]; sum+=a[0][7] * b[7][1];//second K loop ends Inner loop: A B C Row-wise Rutgers University Liu Liu 5 (i,*) (*,j) Columnwise (i,j) Fixed

6 Matrix Multiplication (jik) /* jik */ for (j=0; j<n; j++) { for (i=0; i<n; i++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum } } Inner loop: (*,j) (i,j) (i,*) A B C Misses per Inner Loop Iteration: Row-wise Columnwise Fixed A B C Rutgers University Liu Liu 6

7 /* jik */ for (j=0; j<n; j++) { for (i=0; i<n; i++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum } } Matrix Multiplication (jik) sum+=a[0][0] * b[0][0];//what data been loaded to cache? sum+=a[0][1] * b[1][0]; sum+=a[0][2] * b[2][0]; sum+=a[0][3] * b[3][0]; sum+=a[0][4] * b[4][0]; sum+=a[0][5] * b[5][0]; sum+=a[0][6] * b[6][0]; sum+=a[0][7] * b[7][0];//first K loop ends c[0][0] = sum; sum+=a[1][0] * b[0][0];//what data been loaded to cache? sum+=a[1][1] * b[1][0]; sum+=a[1][2] * b[2][0]; sum+=a[1][3] * b[3][0]; sum+=a[1][4] * b[4][0]; sum+=a[1][5] * b[5][0]; sum+=a[1][6] * b[6][0]; sum+=a[1][7] * b[7][0];//second K loop ends Inner loop: A B C Row-wise Rutgers University Liu Liu 7 (i,*) (*,j) Columnwise (i,j) Fixed

8 Matrix Multiplication (kij) /* kij */ for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; } } Inner loop: (i,k) (k,*) A B C (i,*) Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C Rutgers University Liu Liu 8

9 /* kij */ for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; } } Matrix Multiplication (kij) r = a[0][0]; c[0][0] += r * b[0][0]; //what data been loaded to cache? c[0][1] += r * b[0][1]; c[0][2] += r * b[0][2]; c[0][3] += r * b[0][3]; c[0][4] += r * b[0][4]; c[0][5] += r * b[0][5]; c[0][6] += r * b[0][6]; c[0][7] += r * b[0][7]; //end of first J loop r = a[1][0]; c[1][0] += r * b[0][0]; //what data been loaded to cache? c[1][1] += r * b[0][1]; c[1][2] += r * b[0][2]; c[1][3] += r * b[0][3]; c[1][4] += r * b[0][4]; c[1][5] += r * b[0][5]; c[1][6] += r * b[0][6]; c[1][7] += r * b[0][7]; //end of first J loop A B C Rutgers University Liu Liu 9 (i,k) Fixed Inner loop: (k,*) Row-wise Row-wise (i,*)

10 Matrix Multiplication (ikj) /* ikj */ for (i=0; i<n; i++) { for (k=0; k<n; k++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; } } Inner loop: (i,k) (k,*) A B C (i,*) Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C Rutgers University Liu Liu 10

11 Matrix Multiplication (jki) /* jki */ for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; } } Inner loop: (*,k) (*,j) (k,j) A B C Misses per Inner Loop Iteration: A B C Column - wise Fixed Columnwise Rutgers University Liu Liu 11

12 Matrix Multiplication (jki) /* jki */ for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; } } Inner loop: (*,k) (*,j) (k,j) A B C Unroll the loop by yourself and check if correct? Column - wise Fixed Columnwise Rutgers University Liu Liu 12

13 Improving Temporal Locality by Blocking Example: Blocked matrix multiplication block (in this context) does not mean cache block. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 A 11 A 12 X B 11 B 12 = C 11 C 12 A 21 A 22 B 21 B 22 C 21 C 22 Key idea: Sub-blocks (i.e., A xy ) can be treated just like scalars. C 11 = A 11 B 11 + A 12 B 21 C 12 = A 11 B 12 + A 12 B 22 C 21 = A 21 B 11 + A 22 B 21 C 22 = A 21 B 12 + A 22 B 22 Rutgers University Liu Liu 13

14 Improving Temporal Locality by Blocking /* kij */ for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[0][0]; r = a[0][0]; r = a[i][k]; c[0][0] += r * b[0][0]; c[0][0] += r * b[0][0]; for (j=0; j<n; j++) c[0][1] += r * b[0][1]; c[0][1] += r * b[0][1]; c[i][j] += r * b[k][j]; c[0][2] += r * b[0][2]; c[0][2] += r * b[0][2]; } c[0][3] += r * b[0][3]; c[0][3] += r * b[0][3]; } c[0][4] += r * b[0][4]; r = a[1][0]; c[0][5] += r * b[0][5]; c[1][0] += r * b[0][0]; c[0][6] += r * b[0][6]; c[1][1] += r * b[0][1]; c[0][7] += r * b[0][7]; c[1][2] += r * b[0][2]; A 11 A 12 B 11 B 12 C 11 C 12 r = a[1][0]; c[1][3] += r * b[0][3]; c[1][0] += r * b[0][0]; r = a[2][0]; X = A c[1][1] += r * b[0][1]; 21 A 22 B 21 B 22 C 21 C 22 c[1][2] += r * b[0][2]; r = a[3][0]; c[1][3] += r * b[0][3]; c[1][4] += r * b[0][4]; r = a[0][1]; c[1][5] += r * b[0][5]; c[0][0] += r * b[1][0]; C 11 = A 11 B 11 + A 12 B 21 c[1][6] += r * b[0][6]; c[1][7] += r * b[0][7]; r = a[2][0];.. r = a[7][0];.. r = a[0][1]; c[0][0] += r * b[1][0]; Rutgers University Liu Liu 14 Example: N = 8; sub-block size = 4

15 Improving Temporal Locality by Blocking /* kij */ for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[0][0]; r = a[0][0]; r = a[i][k]; c[0][0] += r * b[0][0]; c[0][0] += r * b[0][0]; for (j=0; j<n; j++) c[0][1] += r * b[0][1]; c[0][1] += r * b[0][1]; c[i][j] += r * b[k][j]; c[0][2] += r * b[0][2]; c[0][2] += r * b[0][2]; } c[0][3] += r * b[0][3]; c[0][3] += r * b[0][3]; } c[0][4] += r * b[0][4]; r = a[1][0]; c[0][5] += r * b[0][5]; c[1][0] += r * b[0][0]; c[0][6] += r * b[0][6]; c[1][1] += r * b[0][1]; c[0][7] += r * b[0][7]; c[1][2] += r * b[0][2]; A 11 A 12 B 11 B 12 C 11 C 12 r = a[1][0]; c[1][3] += r * b[0][3]; c[1][0] += r * b[0][0]; r = a[2][0]; X = A c[1][1] += r * b[0][1]; 21 A 22 B 21 B 22 C 21 C 22 c[1][2] += r * b[0][2]; r = a[3][0]; c[1][3] += r * b[0][3]; c[1][4] += r * b[0][4]; r = a[0][1]; c[1][5] += r * b[0][5]; c[0][0] += r * b[1][0]; C 11 = A 11 B 11 + A 12 B 21 c[1][6] += r * b[0][6]; c[1][7] += r * b[0][7]; r = a[2][0];.. r = a[7][0];.. r = a[0][1]; c[0][0] += r * b[1][0]; Rutgers University Liu Liu 15 Example: N = 8; sub-block size = 4

16 Digital Logic Rutgers University Liu Liu

17 Transistor: Building Block of Computers Microprocessors contain millions (billions) of transistors Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple PowerPC G5 (2003): 58 million Logically, each transistor acts as a switch Combined to implement logic functions AND, OR, NOT Combined to build higher-level structures Adder, multiplexer, decoder, register, Combined to build processor Rutgers University Liu Liu 17

18 Simple Switch Circuit Switch open: No current through circuit Light is off V out is +2.9V Switch closed: Current flows Light is on V out is 0V Switch-based circuits can easily represent two states: on/off, open/closed, voltage/no voltage. Rutgers University Liu Liu 18

19 n-type MOS Transistor MOS = Metal Oxide Semiconductor n-type two types: n-type and p-type when Gate has positive voltage, short circuit between #1 and #2 when Gate has zero voltage, open circuit between #1 and #2 Gate = 1 Gate = 0 Rutgers University Liu Liu 19

20 p-type MOS Transistor p-type is complementary to n-type when Gate has positive voltage, open circuit between #1 and #2 when Gate has zero voltage, short circuit between #1 and #2 Gate = 1 Gate = 0 Rutgers University Liu Liu 20

21 Logic Gates Use transistors to implement logical functions: AND, OR, NOT Digital symbols: recall that we assign a range of analog voltages to each digital (logic) symbol assignment of voltage ranges depends on electrical properties of transistors being used typical values for "1": +5V, +3.3V, +2.9V from now on we'll use +2.9V Rutgers University Liu Liu 21

22 Complementary MOS CMOS Circuit Uses both n-type and p-type MOS transistors p-type Attached to + voltage Pulls output voltage UP when input is zero n-type Attached to GND Pulls output voltage DOWN when input is one MOS transistors are combined to form Logic Gates For all inputs, make sure that output is either connected to GND or to +, but not both! Rutgers University Liu Liu 22

23 Inverter (NOT Gate) Truth table In Out 0 V 2.9 V 2.9 V 0 V In Out Rutgers University Liu Liu 23

24 NOR Gate A B C Note: Serial structure on top, parallel on bottom Rutgers University Liu Liu 24

25 OR Gate A B C Add inverter to NOR. Rutgers University Liu Liu 25

26 NAND Gate (AND-NOT) A B C Note: Parallel structure on top, serial on bottom Rutgers University Liu Liu 26

27 AND Gate A B C Add inverter to NAND. Rutgers University Liu Liu 27

28 Basic Logic Gates Symbols Rutgers University Liu Liu 28

29 Logical Completeness Can implement ANY truth table with AND, OR, NOT. A B C D AND combinations that yield a "1" in the truth table OR the results of the AND gates Rutgers University Liu Liu 29

30 NAND, NOR universality NAND, NOR universal because they can realize AND, OR, NOT Rutgers University Liu Liu 30

31 NAND and NOR Functional Completeness Any gate can be implemented using either NOR or NAND gates. Why is this important? When building a chip, easier to build one with all of the same gates. Rutgers University Liu Liu 31

32 DeMorgan's Law Converting AND to OR (with some help from NOT) Consider the following gate: A B A B A B A B To convert AND to OR (or vice versa), invert inputs and output. Generally, DeMorgan s Laws: 1. PQ = P + Q 2. P + Q = P Q Same as A+B! Rutgers University Liu Liu 32

33 More than 2 Inputs? AND/OR can take any number of inputs. AND = 1 if all inputs are 1. OR = 1 if any input is 1. Similar for NAND/NOR. Can implement with multiple two-input gates or with single CMOS circuit. Rutgers University Liu Liu 33

34 n inputs, 2 n outputs Decoder(next lecture) exactly one output is 1 for each possible input pattern 2-bit decoder Rutgers University Liu Liu 34

35 Multiplexer (MUX)(next lecture) n-bit selector and 2 n inputs, one output output equals one of the inputs, depending on selector 4-to-1 MUX Rutgers University Liu Liu 35

36 Full Adder(next lecture) Add two bits and carry-in, produce one-bit sum and carry-out. A B C in S C ou t Rutgers University Liu Liu 36

37 Four-bit Adder(next lecture) Rutgers University Liu Liu 37

38 Circuit Design Have a good idea. What kind of circuit might be useful? Derive a truth table for this circuit Derive a Boolean expression for the truth table Build a circuit given the Boolean expression Building the circuit involves mapping the Boolean expression to actual gates. This part is easy. Deriving the Boolean expression is easy. Deriving a good one is tricky. Rutgers University Liu Liu 38

39 Converting Truth Table to Boolean Expression Given a circuit, isolate the rows in which the output of the circuit should be true Rutgers University Liu Liu 39

40 Converting Truth Table to Boolean Expression Given a circuit, isolate that rows in which the output of the circuit should be true A product term that contains exactly one instance of every variable is called a minterm Rutgers University Liu Liu 40

41 Converting Truth Table to Boolean Expression Given the expressions for each row, build a larger Boolean expression for the entire table. This is a sum-of-products (SOP) form. Rutgers University Liu Liu 41

42 Converting Truth Table to Boolean Expression Finally build the circuit. Problem: SOP forms are often not minimal. Solution: Make it minimal. We ll go over two ways. Rutgers University Liu Liu 42

43 Boolean Identities Rutgers University Liu Liu 43

44 Boolean Algebra Example Rutgers University Liu Liu 44

45 Boolean Algebra Example 2 Find the complement of F Rutgers University Liu Liu 45

46 Using DeMorgan s Laws to Complement 1. To big bar over AND and OR of 2 or more functions 2. Replace AND with OR, OR with AND 3. 1 with 0, 0 with 1 4. F with not(f), not(f) with F Rutgers University Liu Liu 46

47 First Approach: Algebraic Simply use the rules of Boolean logic Rutgers University Liu Liu 47

48 The Result Rutgers University Liu Liu 48

49 Karnaugh Maps or K-Maps K-maps are a graphical technique to view minterms and how they relate. The map is a diagram made up of squares, with each square representing a single minterm. Minterms resulting in a 1 are marked as 1, all others are marked 0 Rutgers University Liu Liu 49

50 2 Variable K-Map Rutgers University Liu Liu 30 50

51 2 Variable K-Map Rutgers University Liu Liu 31 51

52 2 Variable K-Map Rutgers University Liu Liu 32 52

53 Finding Commonality Rutgers University Liu Liu 33 53

54 Finding the best solution Grouping become simplified products. Both are correct. A+B is preferred. Rutgers University Liu Liu 34 54

55 Simplify Example Rutgers University Liu Liu 35 55

56 Simplify Example Rutgers University Liu Liu 36 56

57 3 Variable K-Maps C Note in higher maps, several variables occupy a given axis The sequence of 1s and 0s follow a Gray Code Sequence. (WHY?) B Rutgers University Liu Liu 57

58 3 Variable K-Maps Rutgers University Liu Liu 58

59 3 Variable K-Maps C B Rutgers University Liu Liu 59

60 3 Variable K-Maps Rutgers University Liu Liu 60

61 3 Variable K-Maps Rutgers University Liu Liu 61

62 3 Variable K-Maps Rutgers University Liu Liu 62

63 Back to our earlier example.. The K-map and the algebraic produce the same result. Rutgers University Liu Liu 43 63

64 Up up and let s keep going D A B C Rutgers University Liu Liu 64

65 D Few more examples B A C Rutgers University Liu Liu 65

66 Few more examples D A B C Rutgers University Liu Liu 66