Migration From AT89C51SND1C to AT83C51SDN1C. Application Note. MP3 Microcontrollers
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1 Migration From AT89C51SND1C to AT83C51SDN1C This application note details the differences between AT89C51SND1C and AT83C51SDN1C products, and gives some tips and tricks to the user when migrating from Flash to ROM product from a hardware and firmware point of view. MP3 Microcontrollers Application Note Rev. 1
2 Memory Architecture AT83C51SDN1C Memory Architecture The AT83C51SND1C product provides the internal program/code memory in ROM memory while the AT89C51SND1C product provides it in Flash memory. Figure 1. ROM Memory Architecture FFFFh 64K Bytes ROM Memory User 0000h As shown in Figure 1 the AT83C51SDN1C ROM memory is composed of only one user space detailed as follows. User Space This space is composed of a 64K Bytes ROM memory programmed during the manufacturing process. It contains the user s application code. AT89C51SND1C Memory Architecture Figure 2. Flash Memory Architecture FFFFh Hardware Security Extra Row FFFFh F000h 4K Bytes Flash Memory Boot 64K Bytes Flash Memory User 0000h As shown in Figure 2 the AT89C51SND1C Flash memory is composed of four spaces detailed as follows. User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the user s application code. This space can be read or written by both software and hardware modes. Boot Space This space is composed of a 4K Bytes Flash memory. It contains the bootloader for In- System Programming and the routines for In Application Programming. This space can only be read or written by hardware mode using a parallel programming tool. Hardware Security Space This space is composed of one Byte: the Hardware Security Byte (HSB) divided in 2 separate nibbles. The MSN contains the X2 mode configuration bit and the Bootloader 2 AT8xC51SND1C Application Note
3 AT8xC51SND1C Application Note Jump and can be written by software while the LSN contains the lock system level to protect the memory content against piracy and can only be written by hardware. Extra Row Space User Constraints No Boot Space or Extra Row Space Hardware Security Space This space is composed of 2 Bytes: The Software Boot Vector (SBV). This Byte is used by the software bootloader to build the boot address. The Software Security Byte (SSB). This Byte is used to lock the execution of some bootloader commands. Due to its ROM technology, the AT83C51SND1C product does not allow In-System and In-Application Programming and therefore, does not implement any boot space, hardware security space and extra row space. Attempting to enable the boot memory through software or hardware boot condition will result in no effect. Then, jumping to the boot entry address (F000h) will jump in internal user ROM. Software boot condition ENBOOT bit in AUXR1 register (see Table 1) is not implemented in AT83C51SDN1C product. Note: User must take care not to write to ENBOOT bit. ISP pin (see Figure 3) is not implemented in AT83C51SDN1C product. Note: User must take care to leave this pin unconnected. Since the HSB register (see Table 3) is not implemented, the AT83C51SND1C product does not provide any programmable hardware security system. Internal ROM content is always secured because there is no way to read it externally. Moreover the AT83C51SND1C product does not implement X2B bit in HSB disallowing to start automatically in X2 mode. Note: User must take care to always set the X2 bit in CKCON register by firmware in the application start-up routine if needed. Version Register The AT83C51SND1C product NVERS register (see Table 2) is set to 0XXX XXXXb (ROM product) while it is set to 1XXX XXXXb in the AT89C51SND1C product. Note: User must take care of NVERS register usage in its code to avoid any infinite loop that may have been implemented to secure firmware from old product versions usage. 3
4 Pinout Figure 3. AT8xC51SND1C 80-pin QFP Package P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A AT89C51SND1C-RO (Flash) AT83C51SDN1C-RO (ROM) MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P1.6/SCL P1.7/SDA P FILT P X2 X1 TST U U P3.5/T1 P3.6/WR P3.7/RD A A AREFP AREFN AIN0 AIN1 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO ALE ISP/NC (1) P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P D+ D- P5.2 P P5.1 P5.0 P4.7 P4.6 Note: 1. ISP for AT89C51SND1C, NC for AT83C51SDN1C. Do not connect this pin when using AT83C51SDN1C. 4 AT8xC51SND1C Application Note
5 AT8xC51SND1C Application Note Registers Table 1. AUXR1 Register AUXR1 (S:A2h) Auxiliary Register ENBOOT - GF3 0 - DPS Number Mnemonic Description The value read from these bits are indeterminate. Do not set these bits. 5 ENBOOT (1) Set this bit to map the boot Flash in the code space between at addresses F000h to FFFFh. Enable Boot Flash Clear this bit to disable boot Flash. 4-3 GF3 2 0 The value read from this bit is indeterminate. Do not set this bit. General Flag This bit is a general-purpose user flag. Always Zero This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. 1 - for Data Pointer Extension. 0 DPS Data Pointer Select Set to select second data pointer: DPTR1. Clear to select first data pointer: DPTR0. Reset Value = XXXX 00X0b Note: 1. This bit is not implemented in AT83C51SDN1C product. Do not set this bit. Table 2. NVERS Register (Read Only) NVERS (S:FBh) Version Register V7 V6 V5 V4 V3 V2 V1 V0 Number Mnemonic Description 7-0 V0:7 Value of these bits depends on hardware version. Reset Value = 0XXX XXXXb (AT83C51SDN1C) or 1XXX XXXXb (AT89C51SND1C) 5
6 Table 3. HSB Byte Hardware Security Byte X2B BLJB LB2 LB1 LB0 Number Mnemonic Description 7 X2B (1) Program this bit to start in X2 mode. X2 Unprogram (erase) this bit to start in standard mode. 6 BLJB LB2:0 Bootloader Jump Program this bit to execute the bootloader at address F000h on next reset. Unprogram (erase) this bit to execute user s application at address 0000h on next reset. The value read from these bits is always unprogrammed. Do not program these bits. The value read from this bit is always unprogrammed. Do not program this bit. Hardware Lock s Refer to for bits description. Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase. Notes: 1. On AT89C51SND1C X2B initializes the X2 bit in CKCON during the reset phase. 2. s 0 to 3 (MSN) can only be programmed by hardware mode. 6 AT8xC51SND1C Application Note
7 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA TEL 1(408) FAX 1(408) Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) FAX (41) Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) FAX (852) Japan 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan TEL (81) FAX (81) Atmel Operations Memory 2325 Orchard Parkway San Jose, CA TEL 1(408) FAX 1(408) Microcontrollers 2325 Orchard Parkway San Jose, CA TEL 1(408) FAX 1(408) La Chantrerie BP Nantes Cedex 3, France TEL (33) FAX (33) ASIC/ASSP/Smart Cards Zone Industrielle Rousset Cedex, France TEL (33) FAX (33) East Cheyenne Mtn. Blvd. Colorado Springs, CO TEL 1(719) FAX 1(719) Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) FAX (44) RF/Automotive Theresienstrasse 2 Postfach Heilbronn, Germany TEL (49) FAX (49) East Cheyenne Mtn. Blvd. Colorado Springs, CO TEL 1(719) FAX 1(719) Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP Saint-Egreve Cedex, France TEL (33) FAX (33) literature@atmel.com Web Site Atmel Corporation Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditions located on the Company s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel s products are not authorized for use as critical components in life support devices or systems. Atmel Corporation All rights reserved. Atmel, the Atmel logo, and combinations thereof are registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names in this document may be the trademarks of others. Printed on recycled paper. /xm
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Features Single-voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 55 ns Internal Program Control and Timer 16-Kbyte Boot Block with Lockout Fast Erase Cycle Time 10 seconds Byte-by-byte
More informationARM7TDMI - based Microcontroller AT91RM3400. Errata Sheet
Errata AC Characteristics PLL Frequency Limitation (30) Boot ROM Boot Uploader: SRAM Download Limitation (29) MultiMedia Card Interface Data Endianess is Inverted from MCI to MMC or SD Card (28) Timer/Counter
More information8-bit Microcontroller. Application Note. AVR032: Linker Command Files for the IAR ICCA90 Compiler
AVR032: Linker Command Files for the IAR ICCA90 Compiler Features XLINK Commands Segment Explanation and Location Linker File Examples for: AT90S2313 AT90S8515 AT90S8515 with External RAM and Memory Mapped
More informationBattery-Voltage. 4-megabit (512K x 8/ 256K x 16) Single 2.7-volt. Flash Memory AT49BV4096A AT49LV4096A
Features Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time 70 ns Internal Erase/Program Control Sector Architecture One 8K Word (16K Bytes) Boot Block with
More information2-megabit (256K x 8) 5-volt Only Flash Memory AT29C020
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 Bytes/Sector) Internal Address and Data Latches for
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More information512K (64K x 8) 5-volt Only Flash Memory AT29C512
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 512 Sectors (128 Bytes/Sector) Internal Address and Data Latches for 128
More information4-megabit (512K x 8) 5-volt Only 256-byte Sector Flash Memory AT29C040A
Features Fast Read Access Time 90 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 2048 Sectors (256 Bytes/Sector) Internal Address and Data Latches for
More information2-wire Serial EEPROM AT24C1024. Features. Description. Pin Configurations. 1M (131,072 x 8)
Features Low-voltage Operation 2.7 (V CC = 2.7V to 5.5V) Internally Organized 3,072 x 8 2-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol
More information1-megabit (128K x 8) 5-volt Only Flash Memory AT29C010A
Features Fast Read Access Time 70 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (128 Bytes/Sector) Internal Address and Data Latches for
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More informationCryptoMemory 64 Kbit AT88SC6416C. Summary. Features. Table 1. Pin Configuration
Features One of a Family of Devices with User Memories from 1-Kbit to 1-Mbit 64-Kbit (8-Kbyte) EEPROM User Memory Sixteen 512-byte (4-Kbit) Zones Self-timed Write Cycle (5 ms) Single Byte or 128-byte Page
More information4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT49BV040 AT49LV040
Features Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time 70 ns Internal Program Control and Timer 16K Bytes Boot Block with Lockout Fast Chip Erase Cycle Time
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More information1-megabit (128K x 8) 5-volt Only Flash Memory AT49F001A AT49F001AN AT49F001AT AT49F001ANT. Features. Description. Pin Configurations
Features Single-voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 45 ns Internal Program Control and Timer Sector Architecture One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes
More informationUART. Embedded RISC Microcontroller Core Peripheral
Features New Enhanced Baud Rate Generator Generates Any Required Baud Rate Maximum 6 Mbps (0.35 µm) High Baud Rates at Low Crystal Clock Frequencies 6-, 7-, 8- or 9-bit Data Noise Filtering and Noise Error
More information4-megabit (512K x 8) 3-volt Only 256-byte Sector Flash Memory AT29LV040A
Features Single Voltage, Range 3V to 3.6V Supply 3-volt Only Read and Write Operation Software Protected Programming Fast Read Access Time 150 ns Low Power Dissipation 15 ma Active Current 40 µa CMOS Standby
More information64K (8K x 8) High Speed Parallel EEPROM with Page Write and Software Data Protection AT28HC64BF
Features Fast Read Access Time 70 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Fast Write Cycle Times Page Write Cycle Time: 2 ms Maximum (Standard) 1 to 64-byte Page
More information2-wire Serial EEPROM AT24C01A AT24C02 AT24C04 AT24C08 AT24C16
Features Low-voltage and Standard-voltage Operation 2.7(V CC =2.7Vto5.5V) 1.8(V CC =1.8Vto5.5V) Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) 2-wire Serial
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Parallel EEPROM Data Protection Advantages of EEPROMs EEPROMs provide the memory solution wherever reprogrammable, nonvolatile memory is required. They are easy to use, requiring little or no support hardware
More information8-bit Microcontroller. Application Note. AVR410: RC5 IR Remote Control Receiver
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More information1-megabit (128K x 8) Single 2.7-volt. Flash Memory AT49BV001A AT49BV001AN AT49BV001AT AT49BV001ANT. Battery-Voltage. Features.
Features Single Supply for Read and Write: 2.7 to 3.6V Fast Read Access Time 55 ns Internal Program Control and Timer Sector Architecture One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes
More informationCryptoMemory 256 Kbit AT88SC25616C. Summary
Features One of a Family of Devices with User Memories from 1-Kbit to 1-Mbit 256-Kbit (32-Kbyte) EEPROM User Memory Sixteen 2-Kbyte (16-Kbit) Zones Self-timed Write Cycle (5 ms) Single Byte or 128-byte
More informationTwo-Wire Serial EEPROM AT24C164 (1)
Features Low Voltage and Standard Voltage Operation 2.7 (V CC = 2.7V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 2048 x 8 (16K) Two-Wire Serial Interface Schmitt Trigger, Filtered Inputs for
More information512K (64K x 8) 5-volt Only Flash Memory AT49F512
Features Single Voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 55 ns Internal Program Control and Timer 8K Bytes Boot Block With Lockout Fast Erase Cycle Time 10 Seconds Byte-by-byte
More informationAT17LV(A) Series FPGA Configuration Memory. Application Note. Programming Specification for AT17LV(A) Series FPGA Configuration Memories
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More informationDIP Top View * RESET A16 A15 A12 VCC A17 A14 A13 A8 A9 A11 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A10 I/O7 I/O6 I/O5 I/O4 I/O3 I/O1 I/O2 GND
Features Single-voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 55 ns Internal Program Control and Timer Sector Architecture One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes
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Contents Atmel FPGA Integrated Development System (IDS) contains the following items: IDS Installation Guide CD-ROM containing all necessary software and online documents Security block (for Viewlogic
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More information2-wire Serial EEPROMs AT24C128 AT24C256
Features Low-voltage and Standard-voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2. (V CC = 2.V to 5.5V) 2.5 (V CC = 2.5V to 5.5V). (V CC =.V to 3.6V) Internally Organized 6,34 x and 32,6 x 2-wire Serial
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