High-Level Power Modeling of CPLDs and FPGAs

Transcription

1 Hgh-Level Power Modelng of CPLs and FPGAs L Shang and Nraj K. Jha epartment of Electrcal Engneerng Prnceton Unversty {lshang, jha}@ee.prnceton.edu Abstract In ths paper, we present a hgh-level power modelng technque to estmate the power consumpton of reconfgurable devces such as complex programmable logc devces (CPLs and feld-programmable gate arrays (FPGAs. For smplcty of reference, we smply refer to these devces as FPGAs. Frst, we capture the relatonshp between FPGA power dsspaton and I/O sgnal statstcs. We then use an adaptve regresson method to model the FPGA power consumpton. Such a hgh-level model can be used n the nner loop of a system-level synthess tool to estmate the power consumed by dfferent FPGA resources for dfferent potental system-level synthess solutons. It can also be used to verfy the power budgets durng embedded system desgn. Wth our hgh-level power model, the FPGA power consumpton can be obtaned very qucly. Expermental results ndcate that the average relatve error s only 3.1% compared to low-level FPGA power smulaton methods. 1. Introducton Reconfgurable devces [1-5], such as CPLs and FPGAs, are parallel and general hardware platforms. For embedded systems produced n lmted quanttes, FPGAs are much more flexble and cost-effectve alternatves to applcaton-specfc ntegrated crcuts (ASICs. More mportantly, modern applcatons, such as multmeda and wreless communcaton, have dfferent objectves under dfferent operatng modes. A mult-mode system archtecture can be supported by FPGAs n a natural way wth the help of dynamc reconfguraton. Wth the success of battery-based personal computng devces and wreless communcaton systems, low power has become a ey ssue n embedded system desgn. Although ts flexblty maes FPGA a good soluton for portable applcatons, the power consumpton problem cannot be neglected. Frst, less effcent utlzaton of avalable resources maes an FPGA less power-effcent than an ASIC. Second, snce routng resources n an FGPA nclude many swtches, the nterconnect load capactance of an FPGA s 10X to 100X compared to the Acnowledgements: hs wor was supported by ARPA under contract no. AAB07-00-C-L516. capactance n an ASIC [12]. In order to effectvely use FPGAs n low power systems, effcent FPGA power estmaton methods are needed. However, the problem of FPGA power estmaton s not that well-studed. he rest of ths paper s organzed as follows. In Secton 2, we dscuss prevous wors on FPGA and ASIC power estmaton. In Secton 3, we ntroduce our hghlevel power model. In Secton 4, we dscuss hgh-level FPGA power modelng n detal. In Secton 5, we present an adaptve regresson-based hgh-level power modelng technque. We demonstrate the feasblty of our methods expermentally n Secton 6. Fnally, we conclude n Secton Related Wor Some power estmaton technques for ASICs have been presented n [6-10]. In [7], technques are presented for estmatng swtchng actvty and power consumpton n regster-transfer level (RL crcuts. A framewor for exact and approxmate swtchng actvty estmaton n a sequental crcut s provded n [8]. A looup table based ASIC power estmaton method s proposed n [9,10]. o crcumvent the problem of an exponentally ncreasng storage for table looup, a four-dmensonal table s used to model power consumpton. Wors n [11-14] address the power estmaton/ optmzaton problem n FPGAs. A power estmaton method, whch s based on power modelng of dfferent components n an FPGA, s proposed n [12]. In ths approach, the nternal structure of the FPGA needs to be fully explored. ue to the perphery effect and estmaton error n swtchng actvty and nterconnect capactance, the total power estmaton error may be up to 30%. he method n [14] characterzes the power dsspaton of FPGAs usng Manhattan dstances between confgurable logc blocs (CLBs to model the nterconnect power consumpton. he error s usually less than 5% when compared to actual power measurement. However, snce an teratve approach s used for updatng the values of unnown sgnal parameters, the teraton process may not converge. Both the above methods need nternal FPGA confguraton nformaton, and use nternal sgnals to model power consumpton. However, snce many new macro modules, such as Bloc RAM [1], embedded

2 system bloc (ESB [2] and standard nterfaces etc., have been ntegrated nto FPGAs, fully explorng the nternal archtecture of an FPGA has become very challengng. Wth these nternal sgnal modelng approaches, dfferent modules may need ther own descrpton models. Hence, t becomes dffcult to construct a sngle fxed hgh-level power model template. 3. Overvew of Our Wor In ths paper, we propose a hgh-level FPGA power modelng approach wth the followng characterstcs. he model s based on nput and output sgnal statstcs to estmate the nternal power consumpton of FPGAs. Models for dfferently-confgured crcuts are based on the same power macromodel template. hus, the same modelng procedure s appled to dfferent crcuts, whether combnatonal or sequental. An adaptve regresson method s used to tacle the problem of based trang sequences. A good tradeoff between accuracy and effcency s acheved. here are two mportant concerns n hgh-level FPGA power modelng. Frst, hgh-level power estmators need to be more effcent than gate-level power estmators. he hgh-level power model we propose can be used n the nner loop of system-level synthess, puttng power estmaton n the crtcal path of synthess. hus, estmaton effcency s a must. We use a regresson functon to estmate the FPGA power consumpton. In our approach, spatal correlaton nformaton s utlzed to partton nput sgnals nto dfferent subsets. Statstcs for three nput sgnal parameters for each subset and one output sgnal parameter are used n our regresson method to construct the hgh-level power model. A shortcomng of hgh-level power estmaton methods n general s that a trang set of nput vectors wth gven statstcal dstrbutons s typcally used n developng the power macromodels. Hence, the macromodel s based towards the trang set. If the nput trace observed n practce has a dfferent statstcal dstrbuton than the trang set, the power estmaton result may not be accurate. urng normal operaton, there may be hundreds of dfferent typcal nput traces for dfferent applcatons. We cannot use a statc off-lne method to buld a power macromodel for each of these nput traces. In our approach, we use adaptve regresson methods to address ths problem. An adaptve regresson method has prevously been used for ASICs [19], but not for FPGAs. A low power CPL, called Coolrunner [15], s used for expermentally valdatng our technque. Coolrunner s an deal choce for battery-operated portable devces. rang sequences wth dfferent statstcal dstrbutons are generated for tmng and power smulaton. In order to capture the tmng nformaton for dfferent confguratons, we chose Scrocco [16], a real-delay tmng smulator. A low-level power smulator [17] s nvoed to estmate the power consumpton. Snce ths low-level power smulator captures all the nternal swtchng nformaton for ths devce, ts accuracy s comparable to physcal power measurements. hen wth all the collected nformaton, we use an adaptve regresson method to construct a hgh-level power model. Although our experments are based on the Coolrunner, our method s also sutable for other reconfgurable devces, ncludng other CPLs and FPGAs. here are two reasons for ths. Frst, our method does not need to explore the nternal structure of the reconfgurable devces. Only nput and output statstcal parameters are used to construct the hgh-level power model. Second, although the detaled nternal structures of dfferent reconfgurable devces are dfferent, most reconfgurable devces, ncludng CPLs and FPGAs, have the same macro structure: embedded logc blocs connected wth global and local nterconnecton resources. Netlst Synthess confguraton Real-delay smulaton models Adaptve hgh-level regresson power model Macromodel template analyss 1.Complexty analyss 2.Parameters selecton Real-delay smulator Statstcs analyzer Low-level power smulator Regresson analyss Statc hgh-level regresson power model Adaptve regresson analyss Statstcal parameters rang trace generator Parameter partton Parameter matrx Verfcaton model Gven nput trace Statstcs analyzer Fg.1: Hgh-level power modelng for FPGAs he adaptve regresson-based hgh-level power modelng flow s shown n Fg. 1. Frst, the macromodel template analyzer s nvoed to perform complexty analyss and other preprocessng steps. hen, trang sequences wth dfferent statstcal characterstcs are generated. hese sequences are used for real-delay tmng smulaton. Wth these results, the statstcs analyzer s nvoed to partton the nput sgnals nto subsets, and create a parameter matrx. A low-level power smulator tool s also nvoed to estmate FPGA power consumpton. he power results and parameter matrx form the nputs of the regresson analyss step. Usng feedbac from the verfcaton model, a statc hgh-level regresson power model s constructed. urng the power estmaton perod, the nput trace s analyzed to decde whether adaptve regresson analyss should be used. If

3 so, the nput trace s sampled, and the sampled data are sent to the low-level power estmator, whle the statc hgh-level regresson power model estmates the FPGA power consumpton wth the whole nput sequence. Adaptve regresson analyss s nvoed fnally to construct the adaptve hgh-level regresson power model. 4. Hgh-Level Power Modelng In ths secton, we gve detals of the consttuent parameters used n our power model. 4.1 Parttonng of nput sgnals In [10], smlar to our method, four nds of parameters are used to model the nput and output sgnal statstcs of ASICs. However, the method n [10] gnores the nature of the sgnals. In practcal crcuts, dfferent nput sgnals may or may not be correlated. For example, f the crcut nputs nclude both data and control sgnals, each may have a very dfferent statstcal dstrbuton. hus, one should avod usng one average statstcal parameter to cover both types of sgnals. In our nput sgnal parttonng approach, we study the spatal correlaton behavor between dfferent nput sgnals based on the nput traces wth dfferent statstcal dstrbutons. If the correlaton between two nput sgnals s less than a pre-defned correlaton threshold, we partton them to dfferent nput subsets, as shown n Fg. 2. hen, we use statstcal parameters to model the sgnals n each subset, as dscussed next. Input sgnals Subset Input sgnals partton Correlaton boundary Input sgnals Input sgnals Fg. 2: Input sgnals partton Input sgnals 4.1 Input subset sgnal probablty he FPGA power consumpton can vary sgnfcantly wth the statstcal dstrbuton of the nput data. Hence, whte nose nput sequence cannot be appled to model the power consumpton of FPGAs. In our approach, after spatal correlaton parttonng s done usng typcal nput traces, the average sgnal probablty for each nput sgnal subset s calculated and used n hgh-level power modelng. 4.2 Input subset sgnal transton densty For each nput subset, the average sgnal transton densty [10] s calculated to model the swtchng actvty for all the sgnals n the subset, whch s defned as: = subset N nn ( lm subset where nn ( swtches durng tme. sgnals n subset. (1 s the number of tmes nput sgnal n N subset s the number of nput 4.3 Input subset sgnal spatal correlaton he average nput subset parwse correlaton parameter [8] s defned as: prob{ n n = 1} SC = (, + 1 subset N subset + 1 where the parameters are self-evdent. 4.4 Output sgnal transton densty he last parameter s the average output sgnal transton densty. In order to construct a more accurate power macromodel, we use real-delay tmng smulaton and capture the transton densty of the output sgnals. hs allows us to capture output gltchng nformaton, whch also reflects the nternal FPGA gltchng behavor. 4.5 Regresson macromodelng functon Our hgh-level power model s based on the average nput subset sgnal probablty (P n, average nput subset sgnal transton densty ( n, average nput subset sgnal spatal correlaton (SC n, and average output sgnal transton densty ( out. Frst-order, quadratc and cubc regresson templates are three possble approaches to model the FPGA power, whch have dfferent executon complexty and accuracy. In the smplest model, a frstorder polynomal template s expressed as: Power where FPGA C n 1 = ( = 0 Pn C P Pn out out SCn c out c SCn SC (2 (3 are regresson coeffcents, and n s the total number of nput subsets. In order to acheve a good trade-off between effcency and accuracy, we desgn a hybrd model n our approach, whch s based on the senstvty of dfferent parameters. Frst, we evaluate the senstvty of FPGA power consumpton to the dfferent parameters. A low order term s chosen for parameters to whch the FPGA power s less senstve, whle a hgh order term s used for parameters to whch the FPGA power s more senstve. he pseudo-code of our algorthm s shown n Fg. 3. In ths algorthm, p denotes the total number of terms and q the total number of frst-order terms (e.g., s a frstorder term n Equaton (3. εthreshold s a predefned error threshold. he error mmzaton rato (EMR s defned as the error mmzed per term dvded by the error threshold:

4 εn 1 εn EMR = ε threshold 1. Create_canddate_term_pool( term1,term2,...,term p 2. Reg_fun_tem = Create_frst_order_template( term1,..., termq 3. Powerlow_level = Low_level_power_est( real_delay_smulaton 4. Powerhgh_level = Regresson_power_est( Reg_fun_tem 5. Error_calculaton( Powerlow_level,Powerhgh_level 6. Whle( ( error ε threshold terms termupperbound EMR EMR 7. erm_pr_sen_sortng( term_pool 8. new_term = term_pool.begn( 9. Reg_fun_tem Reg_template( Reg_fun_tem,new_term 10. Powerhgh_level = = Regresson_power_est( Reg_fun_tem 11. Error_calculaton( Powerlow_level,Powerhgh_level 12. terms EMR _ calculaton( 14. } output( Reg_fun_tem, error} (4 lowerbound Fg. 3: he power macromodelng algorthm In the frst step of the algorthm, a pool of terms s created, and the senstvty of FPGA power to each term s evaluated dynamcally n the followng teratons. hen, n Steps 2-5, the tal regresson model s constructed and the pertnent error compared to low-level power estmaton results s calculated. If the error s larger than ε threshold, a heurstc procedure s nvoed n Step 6. he prorty of terms n the pool s decded dynamcally accordng to ther senstvty (Step 7, and the term (quadratc or cubc wth the hghest prorty s chosen and ncluded n the macromodel (Steps 8 and 9. he error and EMR are evaluated (Steps 11 and 13. At the end of each teraton, three crtera are used to mae a decson on whether the heurstc procedure should be stopped. he three crtera are: frst, the error s less than a predefned error threshold, ε threshold, or second, the total number of terms has exceeded a predefned upper bound on the number of terms, or thrd, the EMR s less than a predefned threshold, EMR lowerbound. Snce dfferent crcuts mapped to an FPGA have dfferent power consumpton behavor, usng our algorthm, we can flexbly construct hgh-level power estmaton models wth dfferent complexty for them, achevng a good trade-off between effcency and accuracy. For our example crcuts, a typcal hgh-level power estmaton functon was found to be: Power FPGA n 1 = ( = 0 C P P SC Pn, SCn Pn, SCn SC out out Pn Havng derved a hgh-level power estmaton functon, we need to estmate the regresson coeffcents C. Hence, we generate dfferent random nput sequences wth dfferent values of P n, n, and SC n, coverng a wde range of nput statstcs. For each nput sequence, a lowerlevel power smulator and real-delay tmng smulator s nvoed to estmate the average FPGA power consumpton and average output sgnal transton densty out. hese results are used to calculate the regresson c P (5 { coeffcents as follows. We frst set up a matrx equaton based on the nputs: P x0, P1 x 1,... = Pr xr 2,... Pr xr 1,... where P l, l = 0,1,..., r 1, x0, s C0 x 1, s C xr 2, s Cs 1 x r 1, s Cs denotes the power smulaton results for the l th nput sequence, x j,, j = 0,..., r 1, = 1,..., s represents the th parameter s j th statstcal value, and C t, t = 0,1,..., s, s the regresson coeffcent we need to estmate. enote the matrx by [X]. If [X] [X] s of full ran, then [18]: Co C1... = Cs 1 Cs P 0 1 P 1 [ X ] [ X ] [ X ]... (7 P P r 2 r 1 o evaluate the accuracy of the macro-model, we defne relatve error as: ε = where r 1(( Pˆ P / P = 0 r P 2 s are the smulated power consumpton, and P s are the estmated values. 5. Adaptve Regresson-Based Power Estmaton he method and algorthm descrbed so far are based on statc macromodels, whch do not change from one desgn that uses the macro logc bloc to another. However, such a statc macromodel s based towards the set of trang patterns used. It s most accurate when the trang patterns reflect well the typcal nput sequences n a specfc desgn mplementaton. However, ths may not always be true. he macro logc bloc and ts hgh-level power model are lely to be stored n a desgn lbrary, whch s used for dfferent applcatons, n whch the data statstcs can vary dramatcally. On the other hand, snce low-level power estmaton s tme-consumng, as we mentoned earler, f the hgh-level power models are to be used n the nner loop of system-level synthess, only fast and relatvely accurate power estmaton s acceptable. We use an adaptve regresson modelng approach to tacle the above problem, as shown n Fg. 4. Frst, the real-delay tmng smulator s nvoed for the gven nput trace. We compute the relevant statstcs of the nput sequence n Step 2 to determne f the nput sequence under consderaton has smlar statstcal characterstcs as the trang set used to derve the statc hgh-level power model (Step 3. If so, statc regresson modelng s used (Step 4. Otherwse, we nvoe the adaptve regresson modelng engne n Step 5, where the nput sequence s sampled. A low-level power estmator s nvoed to estmate the FPGA power consumpton wth (6 (8

5 the sampled sequence (Step 6. he statc hgh-level power model s also used to estmate the power consumed by the FPGA for the whole nput trace (Step 7. Fnally, n Step 8, an adaptve regresson engne s nvoed to generate the adaptve hgh-level power model. Snce the length of the sampled sequences s much shorter than the whole typcal nput trace, the tme consumed n runnng the low-level power smulator s acceptable. By adaptng the statc hgh-level power model usng sampled vectors, we can acheve a good trade-off between accuracy and effcency. Netlst Synthess confguraton Real-delay smulaton models Statc hgh-level power model Step 7. All vectors Step 8. ynamc model adaptaton Power estmaton result Step 4. Gven nput trace Step 1. Real-delay smulator Step 2. Statstcs engne Step 3. Statstcs analyss Step 5. Vector par sam plng Step 6. Sampled vectors Low-level power smulator Regresson engne Fg. 4: Adaptve regresson method flow he method we use s smlar to the one used n [19] for ASICs. Let S be the set of all nput vector pars for a macro logc bloc such that S = N. We sample a subset s S, such that s = n. Let x be the power estmaton result obtaned from the statc hgh-level power model, and y be the power estmaton result obtaned from the low-level power smulator. A lnear functon of hgh-level power estmaton results,, s used to estmate the low-level power smulaton results,, as follows. y y = nα + β x whereα and β are constants. hus, mmzng y ~ get ~ α = y β x and ~ β = ( y y( x x 2 ( x x ( α βx 2 x (9 least-square-error, we (10 where y and x are the average of y and x. hen the modfed power estmate, P, s gven by [19] 1 ~ ~ P = ( y + ( N n α + β x N s (11 6. Expermental Results In ths secton, we present the expermental results to demonstrate the effcacy of our hgh-level power modelng approach. We should frst eep n mnd that FPGA and ASIC lbrares are dfferent. In an ASIC lbrary, f a component s presented as a hard core, t means that the layout and technology are fxed. When such a component s used n a system, wth the same nput sequence, the tmng and power behavor wll be the same. hs may not be true for a component from the FPGA lbrary. Snce FPGAs consttute a parallel hardware platform, multple tass may execute concurrently on the same devce. Combnatons of dfferent tass change the tas confguraton. For the same macro logc bloc, the power consumpton under dfferent confguratons may be dfferent,.e., power estmaton cannot be strctly modeled wth the same parameters or functons. herefore, for hgh-level power modelng, multple tass need to be consdered together, and macro logc bloc combnatons, whch occur wth a hgh probablty, need to be explored. he second pont s that the hgh-level power models we construct are sutable for both combnatonal and sequental logc. Although n sequental logc, the tal states are dffcult to ascertan, the estmaton error ntroduced by unnown tal states s mmzed n a long smulaton. A seres of experments was performed to verfy our hgh-level power estmaton model on a Sun Enterprse 4500 server wth 4 ggabyte memory. he example crcuts are ( 8-bt ALU wth control logc, ( 32-bt adder, ( FIR flter, (v IIR flter, (v Huffman encoder, (v ALU, controller and encoder, and (v ALU, controller and FIR flter. he results for these examples are shown n ables I and II. he crcuts are referred to as Crcut 1-7, respectvely. Ex. able I: Accuracy of the hgh-level power models erms Relatve error Max. error Offlne CPU tme(hrs Onlne CPU tme(sec Crcut % 1.7% Crcut % 4.4% Crcut % 3.4% Crcut % 4.1% Crcut % 7.9% Crcut % 6.7% Crcut % 5.5% In able I, for each example, we show fve results for statc regresson-based hgh-level power models: number of terms we use n the model, relatve error, maxmum error, tme used to construct the model, and tme used to estmate power consumpton. For these examples, the average relatve error s 1.7%.

6 able II: Accuracy of the adaptve regresson-based hgh-level power models Ex. erms Onlne Relatve Samplng CPU error rato tme(sec Crcut % 5% 5.8 Crcut % 5% 8.4 Crcut % 5% 5.5 Crcut % 5% 8.0 Crcut % 5% 6.9 Crcut % 5% 11.7 Crcut % 5% 8.7 In able II, we show results for adaptve regressonbased power models for nput traces wth very dfferent statstcal characterstcs than those used to derve the statc macromodel. he table ncludes the number of terms, relatve error, and the vector-pars samplng rato (.e., the percentage of vector pars from the nput trace that are sampled. Comparng these results wth those n able I, we note that adaptve modelng leads to relatve errors that are qute comparable to those from the statc macromodel. hus, t s ndeed able to adapt to dfferent nput traces wthout much loss n accuracy. For these examples, the average relatve error s only 3.1%. Fgure 5 demonstrates the agreement between hgh-level and low-level power estmaton for part of the expermental results. Fg. 5: Hgh-level vs. low-level power estmaton 7. Conclusons We have presented effcent adaptve regresson-based hgh-level power models to estmate FPGA power consumpton. For each FPGA confguraton, only four types of nput/output statstcs are needed, and only one compact functon s needed to estmate the power consumpton. hus, the memory space requred to store the hgh-level power model s also small. he methods and algorthms we use are general: ( the same power macromodel template can be used for all modeled crcuts. ( hey do not need to explore the nternal structure of the reconfgurable devces. ( In order to mprove on-lne power estmaton accuracy, we use adaptve regresson methods to lessen the problem of based trang sequences, and acheve a good trade-off between effcency and accuracy. References [1] Vrtex data sheet, [2] APEX data sheet, [3] FPSLIC, [4] S. rmberger,. Carberry, A. Johnson, and J. Wong, A tme-multplexed FPGA, n Proc. Feld-Programmable Custom Computng Machnes, pp , Apr [5] K. Compton and S. Hauc, Confgurable computng: A survey of systems and software, submtted to ACM Computng Surveys, [6] P. E. Landman and J. M. Rabaey, Archtectural power analyss: he dual bt type method, IEEE rans. VLSI Systems, vol. 3, pp , June [7] A. Raghunathan, S. ey, and N. K. Jha, Regster-transfer level estmaton technques for swtchng actvty and power consumpton, n Proc. Int. Conf. Computer-Aded esgn, pp , Nov [8] C-Y. su, J. Montero, M. Pedram, S. evadas, A. M. espan, and B. Ln, Power estmaton n sequental logc crcuts, IEEE rans. VLSI Systems, vol. 3, no. 3, pp , Sept [9] S. Gupta and F. N. Najm, Analytcal model for hgh level power modelng of combnatonal and sequental crcuts, n Proc. Alessandro Volta Memoral Wsp. Low Power esgn, pp , Mar [10] S. Gupta and F. Najm, Power modelng for hgh-level power estmaton, IEEE rans. VLSI systems, vol. 8, no. 1, pp , Feb [11] K. Roy, Power-dsspaton drven FPGA place and route under tmng constrants, IEEE rans. Crcuts & Systems, vol. 46, no. 5, pp , May [12] E. A. Kusse, Analyss and crcut desgn for low power programmable logc modules, Master s thess, ept. of Electrcal Engneerng and Computer Scence, Unversty of Calforna at Bereley, [13] V. George, H. Zhang and J. Rabaey, esgn of a low energy FPGA, n Proc. Int. Symp. Low Power Electroncs & esgn, pp , Aug [14]. Osmuls, J.. Muehrng, B. Veale, J. M. West, H. L, S. Vanchayobon, S. -H. Ko, J. K. Antono, and S. K. hall, A probablstc power predcton tool for the Xlnx 4000-seres FPGA, n Proc. 5 th Int. Wsp. Embedded/strbuted HPC Systems and Applcatons (EHPC 2000, IPPS 2000 Worshops, pp , May [15] CoolRunner, [16] Scrocco smulator, [17] Power estmator for CoolRunner, [18] R.H. Myerslasscal and Modern Regresson wth Applcaton, uxbury Press, BelmontA, 2 nd edton, [19] C.-. Hseh, Q. Wu.-S. ng, and M. Pedram, Statstcal samplng and regresson analyss for R-level power evaluaton, n Proc. Int. Conf. Computer-Aded esgn, pp , Nov