Recall: Sequential Consistency of Directory Protocols How to get exclusion zone for directory protocol? Recall: Mechanisms for reducing depth

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1 S Graduate omputer Architecture Lecture 1 April 11 th, 1 Distributed Shared Memory (con t) Synchronization rof John D. Kubiatowicz Recall: Sequential onsistency of Directory rotocols How to get exclusion zone for directory protocol? learly need to make sure that invalidations really invalidate copies» Keep state to handle reordering at client (previous slide s problem) While acknowledgements outstanding, cannot handle read requests» NAK read requests» Queue read requests Example for invalidationbased scheme: block owner (home node) provides appearance of atomicity by waiting for all invalidations to be ack d before allowing access to new value As a result, write commit point becomes point at which WData leaves home node (after last ack received) Much harder in update schemes! REQ NAK Req WData Req HOME Inv Ack Ack Inv Reader Inv Ack Reader Reader Recall: Deadlock Issues with rotocols :intervention L 1: req H a:revise R :reply b:response 1: req :intervention L H R :reply :response 1: req :intervention a:revise L H R b:response 1 1 onsider Dual graph of message dependencies Nodes: Networks, Arcs: rotocol actions Number of networks = length of longest dependency Must always make sure response (end) can be absorbed! Networks Sufficient to Avoid Deadlock 1 a a b b Need Networks to Avoid Deadlock Need Networks to Avoid Deadlock Recall: Mechanisms for reducing depth 1: req :intervention a:revise L H R b:response 1: req :intervention a:revise L H R NAK b:response 1: req :intervention a:revise L H R :SendInt To R b:response 1 X 1 1 a a Original: Need Networks to Avoid Deadlock Optional NAK When blocked Need Networks to Transform to Request/Resp: Need Networks to

2 A opular Middle Ground Example Two-level Hierarchies Two-level hierarchy Individual nodes are multiprocessors, connected nonhiearchically e.g. mesh of SMs oherence across nodes is directory-based directory keeps track of nodes, not individual processors oherence within nodes is snooping or directory orthogonal, but needs a good interface of functionality Examples: onvex Exemplar: directory-directory Sequent, Data General, HAL: directory-snoopy SM on a chip? Main Mem B1 Snooping Adapter M/D A M/D A Network1 Directory adapter B (a) Snooping-snooping Network B1 Snooping Adapter (c) Directory-directory Main Mem M/D A M/D A Network1 Directory adapter Dir. B1 Main Mem Assist M/D A M/D A Network1 Dir/Snoopy adapter Network Assist (b) Snooping-directory Bus (or Ring) (d) Directory-snooping B1 Main Mem Dir. M/D A M/D A Network1 Dir/Snoopy adapter Advantages of Multiprocessor Nodes otential for cost and performance advantages amortization of node fixed costs over multiple processors» applies even if processors simply packaged together but not coherent can use commodity SMs less nodes for directory to keep track of much communication may be contained within node (cheaper) nodes prefetch data for each other (fewer remote misses) combining of requests (like hierarchical, only two-level) can even share caches (overlapping of working sets) benefits depend on sharing pattern (and mapping)» good for widely read-shared: e.g. tree data in Barnes-Hut» good for nearest-neighbor, if properly mapped» not so good for all-to-all communication Disadvantages of oherent M Nodes Bandwidth shared among nodes all-to-all example applies to coherent or not Bus increases latency to local memory With coherence, typically wait for local snoop results before sending remote requests Snoopy bus at remote node increases delays there too, increasing latency and reducing bandwidth May hurt performance if sharing patterns don t comply 8

3 Insight into Directory Requirements If most misses involve O() transactions, might as well broadcast! Study Inherent program characteristics: frequency of write misses? how many sharers on a write miss how these scale Also provides insight into how to organize and store directory information ache Invalidation atterns LU Invalidation atterns to 11 1 to 1 1 to 19 to to 8 to 1 to to 9 to to 8 to 1 to to 9 to # of invalidations Ocean Invalidation atterns to 11 1 to 1 1 to 19 to to 8 to 1 to to 9 to to 8 to 1 to to 9 to # of invalidations 9 1 ache Invalidation atterns Sharing atterns Summary Barnes-Hut Invalidation atterns to 11 1 to 1 1 to 19 to to 8 to 1 to to 9 to to 8 to 1 to to 9 to # of invalidations Radiosity Invalidation atterns to 11 1 to 1 1 to 19 to to 8 to 1 to to 9 to to 8 to 1 to to 9 to # of invalidations 11 Generally, few sharers at a write, scales slowly with ode and read-only objects (e.g, scene data in Raytrace)» no problems as rarely written Migratory objects (e.g., cost array cells in LocusRoute)» even as # of Es scale, only 1- invalidations Mostly-read objects (e.g., root of tree in Barnes)» invalidations are large but infrequent, so little impact on performance Frequently read/written objects (e.g., task queues)» invalidations usually remain small, though frequent Synchronization objects» low-contention locks result in small invalidations» high-contention locks need special support (SW trees, queueing locks) Implies directories very useful in containing traffic if organized properly, traffic and latency shouldn t scale too badly Suggests techniques to reduce storage overhead 1

4 Organizing Directories How to Find Directory Information How to find source of directory information entralized Directory Schemes Distributed Flat Hierarchical centralized memory and directory - easy: go to it but not scalable distributed memory and directory flat schemes» directory distributed with memory: at the home» location based on address (hashing): network xaction sent directly to home hierarchical schemes»?? How to locate copies Memory-based ache-based 1 1 How Hierarchical Directories Work (Tracks which of its children level-1 directories have a copy of the memory block. Also tracks which local memory blocks are cached outside this subtree. Inclusion is maintained between level-1 directories and level- directory.) level- directory processing nodes level-1 directory (Tracks which of its children processing nodes have a copy of the memory block. Also tracks which local memory blocks are cached outside this subtree. Inclusion is maintained between processor caches and directory.) Find Directory Info (cont) distributed memory and directory flat schemes» hash hierarchical schemes» node s directory entry for a block says whether each subtree caches the block» to find directory info, send search message up to parent routes itself through directory lookups» like hiearchical snooping, but point-to-point messages between children and parents Directory is a hierarchical data structure leaves are processing nodes, internal nodes just directory logical hierarchy, not necessarily phyiscal» (can be embedded in general network) 1 1

5 How Is Location of opies Stored? Hierarchical Schemes through the hierarchy each directory has presence bits child subtrees and dirty bit Flat Schemes vary a lot different storage overheads and performance characteristics Memory-based schemes» info about copies stored all at the home with the memory block» Dash, Alewife, SGI Origin, Flash ache-based schemes» info about copies distributed among copies themselves each copy points to next» Scalable oherent Interface (SI: IEEE standard) 1 Flat, Memory-based Schemes info about copies co-located with block at the home just like centralized scheme, except distributed erformance Scaling traffic on a write: proportional to number of sharers latency on write: can issue invalidations to sharers in parallel Storage overhead simplest representation: full bit vector, (called Full-Mapped Directory ), i.e. one presence bit per node storage overhead doesn t scale well with ; -byte line implies» nodes: 1.% ovhd.» nodes: % ovhd.; 1 nodes: % ovhd. for M memory blocks in memory, storage overhead is proportional to *M:» Assuming each node has memory M local = M/, M local» This is why people talk about full-mapped directories as scaling with the square of the number of processors 18 M Reducing Storage Overhead Optimizations for full bit vector schemes increase cache block size (reduces storage overhead proportionally) use multiprocessor nodes (bit per mp node, not per processor) still scales as *M, but reasonable for all but very large machines» -procs, per cluster, 18B line:.% ovhd. Reducing width addressing the term? Reducing height addressing the M term? M = M local Storage Reductions Width observation: most blocks cached by only few nodes don t have a bit per node, but entry contains a few pointers to sharing nodes» alled Limited Directory rotocols =1 => 1 bit ptrs, can use 1 pointers and still save space sharing patterns indicate a few pointers should suffice (five or so) need an overflow strategy when there are more sharers Height observation: number of memory blocks >> number of cache blocks most directory entries are useless at any given time ould allocate directory from pot of directory entries» If memory line doesn t have a directory, no-one has copy» What to do if overflow? Invalidate directory with invaliations organize directory as a cache, rather than having one entry per memory block 19

6 ase Study: Alewife Architecture ost Effective Mesh Network ro: Scales in terms of hardware ro: Exploits Locality Directory Distributed along with main memory Bandwidth scales with number of processors on: Non-Uniform Latencies of ommunication Have to manage the mapping of processes/threads onto processors due Alewife employs techniques for latency minimization and latency tolerance so programmer does not have to manage ontext Switch in 11 cycles between processes on remote memory request which has to incur communication network latency ache ontroller holds tags and implements the coherence protocol 1 LimitLESS rotocol (Alewife) Limited Directory that is Locally Extended through Software Support Handle the common case (small worker set) in hardware and the exceptional case (overflow) in software rocessor with rapid trap handling (executes trap code within cycles of initiation) State Shared rocessor needs complete access to coherence related controller state in the hardware directories Directory ontroller can invoke processor trap handlers Machine needs an interface to the network that allows the processor to launch and intercept coherence protocol packets The rotocol Transition to Software Alewife: p=-entry limited directory with software extension (LimitLESS) Read-only directory transaction: Incoming RREQ with n p Hardware memory controller responds If n > p: send RREQ to processor for handling Trap routine can either discard packet or store it to memory Store-back capability permits message-passing and block transfers otential Deadlock Scenario with rocessor Stalled and waiting for a remote cache-fill Solution: Synchronous Trap (stored in local memory) to empty input queue

7 Transition to Software (on t) Overflow Trap Scenario First Instance: Full-Map bit-vector allocated in local memory and hardware pointers transferred into this and vector entered into hash table Otherwise: Transfer hardware pointers into bit vector Meta-State Set to Trap-On-Write While emptying hardware pointers, Meta-State: Trans-In-rogress Incoming Write Request Scenario Empty hardware pointers to memory Set Acktr to number of bits that are set in bit-vector Send invalidations to all caches except possibly requesting one Free vector in memory Upon invalidate acknowledgement (Acktr == ), send Write-ermission and set Memory State to Read-Write Flat, ache-based Schemes How they work: home only holds pointer to rest of directory info distributed linked list of copies, weaves through caches» cache tag has pointer, points to next cache with a copy on read, add yourself to head of the list (comm. needed) on write, propagate chain of invals down the list Scalable oherent Interface (SI) IEEE Standard doubly linked list ache ache Main Memory (Home) Node Node 1 Node ache Scaling roperties (ache-based) Traffic on write: proportional to number of sharers Latency on write: proportional to number of sharers! don t know identity of next sharer until reach current one also assist processing at each node along the way (even reads involve more than one other assist: home and first sharer on list) Storage overhead: quite good scaling along both axes Only one head ptr per memory block» rest is all prop to cache size Very complex!!! Summary of Directory Organizations Flat Schemes: Issue (a): finding source of directory data go to home, based on address Issue (b): finding out where the copies are memory-based: all info is in directory at home cache-based: home has pointer to first element of distributed linked list Issue (c): communicating with those copies memory-based: point-to-point messages (perhaps coarser on overflow)» can be multicast or overlapped cache-based: part of point-to-point linked list traversal to find them» serialized Hierarchical Schemes: all three issues through sending messages up and down tree no single explict list of sharers only direct communication is between parents and children 8

8 Summary of Directory Approaches Directories offer scalable coherence on general networks no need for broadcast media Many possibilities for organizing directory and managing protocols Hierarchical directories not used much high latency, many network transactions, and bandwidth bottleneck at root Both memory-based and cache-based flat schemes are alive for memory-based, full bit vector suffices for moderate scale» measured in nodes visible to directory protocol, not processors will examine case studies of each Role of Synchronization Types of Synchronization Mutual Exclusion Event synchronization» point-to-point» group» global (barriers) How much hardware support? high-level operations? atomic instructions? specialized interconnect? 9 omponents of a Synchronization Event Acquire method Acquire right to the synch» enter critical section, go past event Waiting algorithm Wait for synch to become available when it isn t busy-waiting, blocking, or hybrid Release method Enable other processors to acquire right to the synch Waiting algorithm is independent of type of synchronization makes no sense to put in hardware Strawman Lock Busy-Wait lock: ld register, location /* copy location to register */ cmp location, # /* compare with */ bnz lock /* if not, try again */ st location, #1 /* store 1 to mark it locked */ ret /* return control to caller */ unlock: st location, # /* write to location */ ret /* return control to caller */ Why doesn t the acquire method work? Release method? 1

9 What to do if only load and store? Here is a possible two-thread solution: Thread A Thread B Set A=1; Set B=1; while (B) {//X if (!A) {//Y do nothing; ritical Section; ritical Section; Set B=; Set A=; Does this work? Yes. Both can guarantee that: Only one will enter critical section at a time. At X: if B=, safe for A to perform critical section, otherwise wait to find out what will happen At Y: if A=, safe for B to perform critical section. Otherwise, A is in critical section or waiting for B to quit But: Really messy Generalization gets worse Atomic Instructions Specifies a location, register, & atomic operation Value in location read into a register Another value (function of value read or not) stored into location Many variants Varying degrees of flexibility in second part Simple example: test&set Value in location read into a specified register onstant 1 stored into location Successful if value loaded into register is Other constants could be used instead of 1 and How to implement test&set in distributed cache coherent machine? Wait until have write privileges, then perform operation without allowing any intervening operations (either locally or remotely) lock: t&s register, location bnz lock /* if not, try again */ ret /* return control to caller */ unlock: st location, # /* write to location */ ret /* return control to caller */ Time (s) T&S Lock Microbenchmark: SGI hal Test&set, c = Test&set, exponential backof f, c =. Test&set, exponential backof f, c = Ideal 9 Number of processors lock; delay(c); unlock; Zoo of hardware primitives test&set (&address) { /* most architectures */ result = M[address]; M[address] = 1; return result; swap (&address, register) { /* x8 */ temp = M[address]; M[address] = register; register = temp; compare&swap (&address, reg1, reg) { /* 8 */ if (reg1 == M[address]) { M[address] = reg; return success; else { return failure; load-linked&store conditional(&address) { /* R, alpha */ loop: ll r1, M[address]; movi r, 1; /* an do arbitrary comp */ sc r, M[address]; beqz r, loop;

10 Mini-Instruction Set debate atomic read-modify-write instructions IBM : included atomic compare&swap for multiprogramming x8: any instruction can be prefixed with a lock modifier High-level language advocates want hardware locks/barriers» but it s goes against the RIS flow,and has other problems SAR: atomic register-memory ops (swap, compare&swap) MIS, IBM ower: no atomic operations but pair of instructions» load-locked, store-conditional» later used by ower and DE Alpha too 8: S: ompare and compare and swap» No-one does this any more Rich set of tradeoffs Other forms of hardware support Separate lock lines on the bus Lock locations in memory Lock registers (ray Xmp,Intel Single-hip ) Hardware full/empty bits (Tera, Alewife) QOLB (machines supporting SI protocol) Bus support for interrupt dispatch 8 Enhancements to Simple Lock Reduce frequency of issuing test&sets while waiting Test&set lock with backoff Don t back off too much or will be backed off when lock becomes free Exponential backoff works quite well empirically: i th time = k*c i Busy-wait with read operations rather than test&set Test-and-test&set lock Keep testing with ordinary load» cached lock variable will be invalidated when release occurs When value changes (to ), try to obtain lock with test&set» only one attemptor will succeed; others will fail and start testing again 9 Busy-wait vs Blocking Busy-wait: I.e. spin lock Keep trying to acquire lock until read Very low latency/processor overhead! Very high system overhead!» ausing stress on network while spinning» rocessor is not doing anything else useful Blocking: If can t acquire lock, deschedule process (I.e. unload state) Higher latency/processor overhead (1s of cycles?)» Takes time to unload/restart task» Notification mechanism needed Low system overheadd» No stress on network» rocessor does something useful Hybrid: Spin for a while, then block -competitive: spin until have waited blocking time

11 Improved Hardware rimitives: LL-S Goals: Test with reads Failed read-modify-write attempts don t generate invalidations Nice if single primitive can implement range of r-m-w operations Load-Locked (or -linked), Store-onditional LL reads variable into register Follow with arbitrary instructions to manipulate its value S tries to store back to location succeed if and only if no other write to the variable since this processor s LL» indicated by condition codes; If S succeeds, all three steps happened atomically If fails, doesn t write or generate invalidations must retry aquire 1 Simple Lock with LL-S lock: ll reg1, location /* LL location to reg1 */ sc location, reg /* S reg into location*/ beqz reg, lock /* if failed, start again */ ret unlock: st location, # /* write to location */ ret an do more fancy atomic ops by changing what s between LL & S But keep it small so S likely to succeed Don t include instructions that would need to be undone (e.g. stores) S can fail (without putting transaction on bus) if: Detects intervening write even before trying to get bus Tries to get bus but another processor s S gets bus first LL, S are not lock, unlock respectively Only guarantee no conflicting write to lock variable between them But can use directly to implement simple operations on shared variables Ticket Lock Only one r-m-w per acquire Two counters per lock (next_ticket, now_serving) Acquire: fetch&inc next_ticket; wait for now_serving == next_ticket» atomic op when arrive at lock, not when it s free (so less contention) Release: increment now-serving erformance low latency for low-contention - if fetch&inc cacheable O(p) read misses at release, since all spin on same variable FIFO order» like simple LL-S lock, but no inval when S succeeds, and fair Backoff? Wouldn t it be nice to poll different locations... Array-based Queuing Locks Waiting processes poll on different locations in an array of size p Acquire» fetch&inc to obtain address on which to spin (next array element)» ensure that these addresses are in different cache lines or memories Release» set next location in array, thus waking up process spinning on it O(1) traffic per acquire with coherent caches FIFO ordering, as in ticket lock, but, O(p) space per lock Not so great for non-cache-coherent machines with distributed memory» array location I spin on not necessarily in my local memory Example: MS lock (Mellor-rummey and Scott)

12 Time (s) Lock erformance on SGI hallenge Array-based LL-S LL-S, exponential Ticket Ticket, proportional Loop: lock; delay(c); unlock; delay(d); Time (s) Number of processors Number of processors Number of processors (a) Null (c =, d = ) (b) ritical-section (c =. s, d = ) (c) Delay (c =. s, d = 1.9 s) Time (s) oint to oint Event Synchronization Software methods: Interrupts Busy-waiting: use ordinary variables as flags Blocking: use semaphores Full hardware support: full-empty bit with each word in memory Set when word is full with newly produced data (i.e. when written) Unset when word is empty due to being consumed (i.e. when read) Natural for word-level producer-consumer synchronization» producer: write if empty, set to full; consumer: read if full; set to empty Hardware preserves atomicity of bit manipulation with read or write roblem: flexibility» multiple consumers, or multiple writes before consumer reads?» needs language support to specify when to use» composite data structures? Barriers Software algorithms implemented using locks, flags, counters Hardware barriers Wired-AND line separate from address/data bus» Set input high when arrive, wait for output to be high to leave In practice, multiple wires to allow reuse Useful when barriers are global and very frequent Difficult to support arbitrary subset of processors» even harder with multiple processes per processor Difficult to dynamically change number and identity of participants» e.g. latter due to process migration Not common today on bus-based machines A Simple entralized Barrier Shared counter maintains number of processes that have arrived increment when arrive (lock), check until reaches numprocs roblem? struct bar_type {int counter; struct lock_type lock; int flag = ; bar_name; BARRIER (bar_name, p) { LOK(bar_name.lock); if (bar_name.counter == ) bar_name.flag = ; /* reset flag if first to reach*/ mycount = bar_name.counter++; /* mycount is private */ UNLOK(bar_name.lock); if (mycount == p) { /* last to arrive */ bar_name.counter = ; /* reset for next barrier */ bar_name.flag = 1; /* release waiters */ else while (bar_name.flag == ) {; /* busy wait for release */ 8

13 A Working entralized Barrier onsecutively entering the same barrier doesn t work Must prevent process from entering until all have left previous instance ould use another counter, but increases latency and contention Sense reversal: wait for flag to take different value consecutive times Toggle this value only when all processes reach BARRIER (bar_name, p) { local_sense =!(local_sense); /* toggle private sense variable */ LOK(bar_name.lock); mycount = bar_name.counter++; /* mycount is private */ if (bar_name.counter == p) UNLOK(bar_name.lock); bar_name.flag = local_sense; /* release waiters*/ else { UNLOK(bar_name.lock); while (bar_name.flag!= local_sense) {; 9 entralized Barrier erformance Latency entralized has critical path length at least proportional to p Traffic About p bus transactions Storage ost Very low: centralized counter and flag Fairness Same processor should not always be last to exit barrier No such bias in centralized Key problems for centralized barrier are latency and traffic Especially with distributed memory, traffic goes to same node Improved Barrier Algorithms for a Bus Software combining tree Only k processors access the same location, where k is degree of tree Flat ontention Little contention Tree structured Separate arrival and exit trees, and use sense reversal Valuable in distributed network: communicate along different paths On bus, all traffic goes on same bus, and no less total traffic Higher latency (log p steps of work, and O(p) serialized bus xactions) Advantage on bus is use of ordinary reads/writes instead of locks Barrier erformance on SGI hallenge Time (s) entralized ombining tree Tournament Dissemination Number of processors entralized does quite well» Will discuss fancier barrier algorithms for distributed machines Helpful hardware support: piggybacking of reads misses on bus» Also for spinning on highly contended locks 1

14 Lock-Free Synchronization What happens if process grabs lock, then goes to sleep??? age fault rocessor scheduling Etc Lock-free synchronization: Operations do not require mutual exclusion of multiple insts Nonblocking: Some process will complete in a finite amount of time even if other processors halt Wait-Free (Herlihy): Every (nonfaulting) process will complete in a finite amount of time Systems based on LL&S can implement these Using of ompare&swap for queues compare&swap (&address, reg1, reg) { /* 8 */ if (reg1 == M[address]) { M[address] = reg; return success; else { return failure; Here is an atomic add to linked-list function: addtoqueue(&object) { do { // repeat until no conflict ld r1, M[root] // Get ptr to current head st r1, M[object] // Save link in new object until (compare&swap(&root,r1,object)); root next next next New Object Transactional Memory Transaction-based model of memory Interface: start transaction(); read/write data commit transaction(): If conflicts detected, commit will abort and must be retried What is a conflict?» If values you read are written by others before commit Hardware support for transactions Typically uses cache coherence protocol to help process Brief discussion of Transactional Memory LogTM: Log-based Transactional Memory Kevin Moore, Jayaram Bobba, Michelle Moravan, Mark Hill & David Wood Use of ache oherence protocol to detect transaction conflicts Transactional Interface: begin_transaction(): Request that subsequent statements for a transaction commit_transaction(): Ends successful transaction begun by matching begin_transaction(). Discards any transaction state saved for potential abort abort_transaction(): Transfers control to a previously register conflict handler which should undo and discard work since last begin_transaction()

15 Specific Logging Mechanism Summary erformance Enhancements Reduce number of hops Reduce occupancy of transactions in memory controller Deadlock Issues with rotocols Many protocols are not simply request-response onsider Dual graph of message dependencies» Nodes: Networks, Arcs: rotocol actions» onsider maximum depth of graph to discover number of networks Distributed Directory Structure Flat: Each address has a home node Hierarchical: directory spread along tree Mechanism for locating copies of data Memory-based schemes» info about copies stored all at the home with the memory block ache-based schemes» info about copies distributed among copies themselves 8 Synchronization Summary Rich interaction of hardware-software tradeoffs Must evaluate hardware primitives and software algorithms together primitives determine which algorithms perform well Evaluation methodology is challenging Use of delays, microbenchmarks Should use both microbenchmarks and real workloads Simple software algorithms with common hardware primitives do well on bus Will see more sophisticated techniques for distributed machines Hardware support still subject of debate Theoretical research argues for swap or compare&swap, not fetch&op Algorithms that ensure constant-time access, but complex 9