9ZXL0651. Features/Benefits. General Description. Recommended Application. Key Specifications. Output Features. Block Diagram DATASHEET

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1 DATASHEET 9ZXL65 General Description The 9ZXL65 is a low-power 6-output differential buffer that meets all the performance requirements of the Intel DB2Z specification. It consumes 5% less power than standard HCSL devices and has internal terminations to allow direct connection to 85 ohm transmission lines. The 9ZXL65 is backwards compatible to PCIe Gen and Gen2 and QPI 6.4GT/s specifications. A fixed, internal feedback path maintains low drift for critical QPI applications. Recommended Application 6-utput Low-Power HCSL Buffer for PCIe Gen-2-3 and QPI utput Features 6 -.7V low-power HCSL (LP-HCSL) output pairs w/integrated terminations Block Diagram Features/Benefits Low-Power-HCSL outputs w/zo = 85 ; save power and board space - no termination resistors required. Ideal for blade servers. Space-saving 4-pin VFQFPN package Fixed feedback path for input-to-output delay 6 E# pins; Hardware control of each output PLL or bypass mode; PLL can dejitter incoming clock Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's Spread Spectrum Compatible; tracks spreading input clock for low EMI Key Specifications Cycle-to-cycle jitter <5 utput-to-output skew <65 Input-to-output delay variation <5 PCIe Gen3 phase jitter <. RMS QPI 9.6GT/s 2UI phase jitter <.2 RMS E(5:)# DFB_UT_NC DIF_IN DIF_IN# Z-PLL (SS Compatible) DIF(5:) HIBW_BYPM_LBW# CKPWRGD/PD# SMBDAT SMBCLK Logic IDT 9ZXL65 REV C 45

2 9ZXL65 Pin Configuration NC VDD ve5# DIF_5# DIF_5 VDD DIF_4# DIF_4 ve4# VDD VDDA 9ZXL65 3 NC ^vhibw_bypm_lbw# 2 29 VDD CKPWRGD_PD# 3 28 ve3# GND 4 27 DIF_3# VDDR 5 26 DIF_3 EPAD is GND DIF_IN 6 25 VDD DIF_IN# 7 24 DIF_2# SMBDAT 8 23 DIF_2 SMBCLK 9 22 ve2# DFB_UT_NC# 2 VDD DFB_UT_NC VDD ve# DIF_ DIF_# VDD DIF_ DIF_# ve# VDD 4-VFQFPN ^ prefix indicates internal Pull-Up Resistor v prefix indicates Internal Pull-Dow n Resistor ^v prefix indicates Interal Pull-Up/Dow n Resistor (biased to VDD/2) 5mm x 5mm.4mm pin pitch Pin Power Management Table CKPWRGD_PD# DIF_IN/ DIF_IN# SMBus EN bit DIF(5:)/ DIF(5:)# PLL STATE IF NT IN BYPASS MDE X X Low/Low FF Running Low/Low N Running N PLL perating Mode HiBW_BypM_LoBW# MDE Low PLL Lo BW Mid Bypass High PLL Hi BW NTE: PLL is FF in Bypass Mode Power Connections Pin Number VDD GND Description 4 Analog PLL 5 4 Analog Input 2,6,2,24,27,3,32,36,4 4 DIF clocks PLL perating Mode Readback Table HiBW_BypM_LoBW# Byte, bit 7 Byte, bit 6 Low (Low BW) Mid (Bypass) High (High BW) Tri-level Input Thresholds Level Voltage Low <.8V Mid.2<Vin<.8V High Vin > 2.2V 9ZXL65 SMBus Address + Read/Write bit IDT 2 9ZXL65 REV C 45

3 9ZXL65 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTIN VDDA PWR 3.3V power for the PLL core. 2 ^vhibw_bypm_lbw# LATCHE Trilevel input to select High BW, Bypass or Low BW mode. D IN See PLL perating Mode Table for Details. 3 CKPWRGD_PD# Trays 3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode. 4 GND GND Ground pin. 5 VDDR PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. 6 DIF_IN IN.7 V Differential True input 7 DIF_IN# IN.7 V Differential Complementary Input 8 SMBDAT I/ Data pin of SMBUS circuitry, 5V tolerant 9 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant DFB_UT_NC# UT Complementary half of differential feedback output, provides feedback signal to the PLL for synchronization with input clock to eliminate phase error. This pin should NT be connected on the circuit board, the feedback is internal to the package. DFB_UT_NC UT True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input clock to eliminate phase error. This pin should NT be connected on the circuit board, the feedback is internal to the package. 2 VDD PWR Power supply, nominal 3.3V 3 ve# IN Active low input for enabling DIF pair. This pin has an internal pull-down. =disable outputs, = enable outputs 4 DIF_ UT.7V differential true clock output 5 DIF_# UT.7V differential Complementary clock output 6 VDD PWR Power supply, nominal 3.3V 7 DIF_ UT.7V differential true clock output 8 DIF_# UT.7V differential Complementary clock output 9 ve# IN Active low input for enabling DIF pair. This pin has an internal pull-down. =disable outputs, = enable outputs 2 VDD PWR Power supply, nominal 3.3V 2 VDD PWR Power supply, nominal 3.3V 22 ve2# IN Active low input for enabling DIF pair 2. This pin has an internal pull-down. =disable outputs, = enable outputs 23 DIF_2 UT.7V differential true clock output 24 DIF_2# UT.7V differential Complementary clock output 25 VDD PWR Power supply, nominal 3.3V 26 DIF_3 UT.7V differential true clock output 27 DIF_3# UT.7V differential Complementary clock output 28 ve3# IN Active low input for enabling DIF pair 3. This pin has an internal pull-down. =disable outputs, = enable outputs 29 VDD PWR Power supply, nominal 3.3V 3 NC N/A No Connection. 3 VDD PWR Power supply, nominal 3.3V 32 ve4# IN Active low input for enabling DIF pair 4. This pin has an internal pull-down. =disable outputs, = enable outputs 33 DIF_4 UT.7V differential true clock output 34 DIF_4# UT.7V differential Complementary clock output 35 VDD PWR Power supply, nominal 3.3V 36 DIF_5 UT.7V differential true clock output 37 DIF_5# UT.7V differential Complementary clock output 38 ve5# IN Active low input for enabling DIF pair 5. This pin has an internal pull-down. =disable outputs, = enable outputs 39 VDD PWR Power supply, nominal 3.3V 4 NC N/A No Connection. 4 EPAD GND Ground Pad. IDT 3 9ZXL65 REV C 45

4 9ZXL65 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9ZXL65. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES VDD, VDDA, 3.3V Core Supply Voltage VDDR VDD for core logic and PLL 4.6 V,2 Input Low Voltage V IL GND-.5 V Input High Voltage V IH Except for SMBus interface V DD +.5V V Input High Voltage V IHSMB SMBus clock and data pins 5.5V V Storage Temperature Ts C Junction Temperature Tj 25 C Input ESD protection ESD prot Human Body Model 2 V Guaranteed by design and characterization, not % tested in production. 2 peration under these conditions is neither implied nor guaranteed. Electrical Characteristics Clock Input Parameters T A = T CM ; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Differential inputs Input High Voltage - DIF_IN V IHDIF (single-ended measurement) mv Differential inputs Input Low Voltage - DIF_IN V ILDIF (single-ended measurement) V SS mv Input Common Mode Voltage - DIF_IN V CM Common Mode Input Voltage 3 mv Peak to Peak value Input Amplitude - DIF_IN V SWING (single-ended measurement) 3 45 mv Input Slew Rate - DIF_IN dv/dt Measured differentially.35 V/ns,2 Input Leakage Current I IN V IN = V DD, V IN = GND -5 5 ua Input Duty Cycle d tin Measurement from differential wavefrom % Input Jitter - Cycle to Cycle J DIFIn Differential Measurement 25 Guaranteed by design and characterization, not % tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero IDT 4 9ZXL65 REV C 45

5 9ZXL65 Electrical Characteristics Input/Supply/Common Parameters T A = T CM ; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Ambient perating Temperature T CM Commmercial range 35 7 C Single-ended inputs, except SMBus, low Input High Voltage V IH threshold and tri-level inputs 2 V DD +.3 V Single-ended inputs, except SMBus, low Input Low Voltage V IL threshold and tri-level inputs GND V I IN Single-ended inputs, V IN = GND, V IN = VDD -5 5 ua Input Current I INP Single-ended inputs V IN = V; Inputs with internal pull-up resistors V IN = VDD; Inputs with internal pull-down resistors -2 2 ua Input Frequency F ibyp V DD = 3.3 V, Bypass mode 5 MHz 2 F ipll V DD = 3.3 V, MHz PLL mode 9. MHz 2 Pin Inductance L pin 7 nh C IN Logic Inputs, except DIF_IN.5 5 pf Capacitance C INDIF_IN DIF_IN differential clock inputs pf,4 C UT utput pin capacitance 6 pf From V Clk Stabilization T DD Power-Up and after input clock STAB stabilization or de-assertion of PD# to st clock.53 ms,2 Input SS Modulation Frequency f MDIN Allowable Frequency (Triangular Modulation) 3 33 khz DIF start after E# assertion E# Latency t LATE# DIF stop after E# deassertion cycles,3 DIF output enable after Tdrive_PD# t DRVPD PD# de-assertion 3 us,3 Tfall t F Fall time of control inputs ns,2 Trise t R Rise time of control inputs ns,2 SMBus Input Low Voltage V ILSMB.8 V SMBus Input High Voltage V IHSMB 2. V DDSMB V SMBus utput Low Voltage V I PULLUP.4 V SMBus Sink Current I V L 4 ma Nominal Bus Voltage V DDSMB 3V to 5V +/- % V SCLK/SDATA Rise Time t RSMB (Max VIL -.5) to (Min VIH +.5) ns SCLK/SDATA Fall Time t FSMB (Min VIH +.5) to (Max VIL -.5) 3 ns SMBus perating Frequency f MAXSMB Maximum SMBus operating frequency khz,5 Guaranteed by design and characterization, not % tested in production. 2 Control input must be monotonic from 2% to 8% of input swing. 3 Time from deassertion until outputs are >2 mv 4 DIF IN input 5 The differential input clock must be running for the SMBus to be active IDT 5 9ZXL65 REV C 45

6 9ZXL65 Electrical Characteristics DIF.7V Low Power HCSL utputs T A = T CM ; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Slew rate Trf Scope averaging on V/ns, 2, 3 Slew rate matching Trf Slew rate matching, Scope averaging on 7 2 %, 2, 4 Voltage High VHigh Statistical measurement on single-ended signal using oscilloscope math function. (Scope mv Voltage Low VLow averaging on) Max Voltage Vmax Measurement on single ended signal using mv Min Voltage Vmin absolute value. (Scope averaging off) -3 Vswing Vswing Scope averaging off mv, 2 Crossing Voltage (abs) Vcross_abs Scope averaging off mv, 5 Crossing Voltage (var) -Vcross Scope averaging off 4 4 mv, 6 Guaranteed by design and characterization, not % tested in production. C L = 2pF, Zo = 85Ω differential trace impedance). 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential V. This results in a +/-5mV window around differential V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute. Electrical Characteristics Current Consumption T A = T CM ; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES I DDVDDR MHz, VDDR rail 4 6 ma perating Current I DDVDDAPLL MHz, VDDA rail, PLL Mode 4 2 ma I DDVDDABYP MHz, VDDA rail, Bypass Mode 3 5 ma I DDVDD MHz, VDD rail 4 5 ma I DDVDDRPD Power Down, VDDR Rail ma Powerdown Current I DDVDDAPD Power Down, VDDA Rail.6 3 ma I DDVDDPD Power Down, VDD Rail.3 2 ma Guaranteed by design and characterization, not % tested in production. 2 C L = 2pF, Zo = 85Ω differential trace impedance IDT 6 9ZXL65 REV C 45

7 9ZXL65 Electrical Characteristics Skew and Differential Jitter Parameters T A = T CM ; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES In-to-ut Skew in PLL MHz CLK_IN, DIF[x:] t SP_PLL nominal C, 3.3V - 53,2,4,5,8 In-to-ut Skew in Bypass MHz CLK_IN, DIF[x:] t PD_BYP nominal 35 C, 3.3V ns,2,3,5,8 In-to-ut Skew Varation in PLL mode CLK_IN, DIF[x:] t DSP_PLL across voltage and temperature -5 5,2,3,5,8 In-to-ut Skew Varation in Bypass mode CLK_IN, DIF[x:] t DSP_BYP across voltage and temperature ,2,3,5,8 Random Differential Tracking error beween two CLK_IN, DIF[x:] t DTE 3 5 9ZX devices in Hi BW Mode,2,3,5,8 CLK_IN, DIF[x:] t DSSTE Random Differential Spread Spectrum Tracking error beween two 9ZX devices in Hi BW Mode 5 75,2,3,5,8 utput-to-utput Skew across all outputs DIF{x:] t SKEW_ALL (Common to Bypass and PLL mode) 39 65,2,3,8 PLL Jitter Peaking j peak-hibw LBW#_BYPASS_HIBW = 2.5 db 7,8 PLL Jitter Peaking j peak-lobw LBW#_BYPASS_HIBW = 2 db 7,8 PLL Bandwidth pll HIBW LBW#_BYPASS_HIBW = 4 MHz 8,9 PLL Bandwidth pll LBW LBW#_BYPASS_HIBW =.4 MHz 8,9 Duty Cycle t DC Measured differentially, PLL Mode % Measured differentially, Bypass Mode Duty Cycle Distortion t %, Jitter, Cycle to cycle t jcyc-cyc PLL mode 4 5, Additive Jitter in Bypass Mode 25, Notes for preceding table: C L = 2pF, Zo = 85Ω differential trace impedance. Input to output skew is measured at the first output edge following the corresponding input. 2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. 3 All Bypass Mode Input-to-utput specs refer to the timing between an input edge and the specific output edge created by it. 4 This parameter is deterministic for a given device 5 Measured with scope averaging on to find mean value. 6. t is the period of the input clock 7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 8. Guaranteed by design and characterization, not % tested in production. 9 Measured at 3 db down or half power point. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. Measured from differential waveform IDT 7 9ZXL65 REV C 45

8 9ZXL65 Electrical Characteristics Phase Jitter Parameters T A = T CM ; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBL CNDITINS MIN TYP MAX INDUSTRY LIMIT UNITS Notes t jphpcieg PCIe Gen (p-p),2,3 t jphpcieg2 PCIe Gen 2 Lo Band khz < f <.5MHz,2 PCIe Gen 2 High Band MHz < f < Nyquist (5MHz),2 PCIe Gen 3 t jphpcieg (PLL BW of 2-4MHz, 2-5MHz, CDR = MHz),2,4 Phase Jitter, PLL Mode QPI & SMI ( PLL BW of 7.4MHz /33MHz, 4.8Gb/s, Gb/s 2UI),5 Additive Phase Jitter, Bypass mode t jphqpi_smi QPI & SMI ( PLL BW of 7.8MHz /33MHz, 4.8Gb/s, 6.4Gb/s 2UI) QPI & SMI (MHz, 8.Gb/s, 2UI) QPI & SMI (MHz, 9.6Gb/s, 2UI) ,5..7.2,5 t jphpcieg PCIe Gen 5 N/A (p-p),2,3 t jphpcieg2 PCIe Gen 2 Lo Band.. N/A khz < f <.5MHz,2,6 PCIe Gen 2 High Band.. N/A.5MHz < f < Nyquist (5MHz),2,6 PCIe Gen 3 t jphpcieg3.. N/A (PLL BW of 2-4MHz, 2-5MHz, CDR = MHz),2,4,6 QPI & SMI ( PLL BW of 7.4MHz /33MHz, 4.8Gb/s,.25.3 N/A 6.4Gb/s 2UI),5,6 t jphqpi_smi Applies to all outputs. 2 See for complete specs QPI & SMI ( PLL BW of 7.8MHz /33MHz, 4.8Gb/s, 6.4Gb/s 2UI) QPI & SMI (MHz, 8.Gb/s, 2UI) QPI & SMI (MHz, 9.6Gb/s, 2UI) 3 Sample size of at least K cycles. This figures extrapolates to 8 M cycles for a BER of Subject to final ratification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool..5 N/A.. N/A.. N/A 6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2,5,5,6,5,6,5,6 IDT 8 9ZXL65 REV C 45

9 9ZXL65 Clock Periods Differential utputs with Spread Spectrum Disabled SSC FF Center Freq. MHz Clock Periods Differential utputs with Spread Spectrum Enabled Test Loads Measurement Window Clock us.s.s.s us Clock -SSC - ppm + ppm +SSC -c2c jitter ppm +c2c jitter Short-Term Long-Term Long-Term Short-Term AbsPer Period AbsPer Average Average Average Average Min Nominal Max Min Min Max Max DIF ns,2,3 SSC N Center Freq. MHz Measurement Window Clock us.s.s.s us Clock -SSC - ppm + ppm +SSC -c2c jitter ppm +c2c jitter Short-Term Long-Term Long-Term Short-Term AbsPer Period AbsPer Average Average Average Average Min Nominal Max Min Min Max Max DIF ns,2,3 Notes: Guaranteed by design and characterization, not % tested in production. 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK42BQ/CK4B+ accuracy requirements (+/-ppm). The 9ZXL65 itself does not contribute to ppm error. 3 Driven by SRC output of main clock, MHz PLL Mode or Bypass mode Units Units Notes Notes Rs inches Rs 85ohm Differential Zo 2pF 2pF Low-Power HCSL utput buffer w/internal termination Differential utput Terminations DIF Zo (Ω) Rs (Ω) 7 85 Note: No resistors are required for connection to 85ohm transmission lines. IDT 9 9ZXL65 REV C 45

10 9ZXL65 General SMBus Serial Interface Information for 9ZXL65 How to Write Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X- IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite Beginning Byte = N Data Byte Count = X Beginning Byte N Byte N + X - P stop bit X Byte How to Read Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X- IDT clock sends Byte through Byte X (if X (H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite Beginning Byte = N RT Repeat start Slave Address RD ReaD N P Not acknowledge stop bit X Byte Data Byte Count=X Beginning Byte N Byte N + X - IDT 9ZXL65 REV C 45

11 9ZXL65 SMBusTable: PLL Mode, and Frequency Select Register Byte Pin # Name Control Function Type Default Bit 7 2 PLL Mode PLL perating Mode Rd back R See PLL perating Mode Latch Bit 6 2 PLL Mode PLL perating Mode Rd back R Readback Table Latch Bit 5 Reserved Bit 4 Reserved Bit 3 PLL_SW_EN Enable S/W control of PLL BW RW HW Latch SMBus Control Bit 2 PLL Mode PLL perating Mode RW See PLL perating Mode Bit PLL Mode PLL perating Mode RW Readback Table Bit Reserved Note: Setting bit 3 to '' allows the user to overide the Latch value from pin 5 via use of bits 2 and. Use the values from the PLL perating Mode Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. A warm reset of the system will have to accomplished if the user changes these bits. SMBusTable: utput Control Register Byte Pin # Name Control Function Type Default Bit 7 Reserved Bit 6 26/27 DIF_3_En utput Control - '' overrides E# pin RW Low/Low Enable Bit 5 23/24 DIF_2_En utput Control - '' overrides E# pin RW Bit 4 Reserved Bit 3 Reserved Bit 2 7/8 DIF En utput Control - '' overrides E# pin RW Low/Low Enable Bit 4/5 DIF En utput Control - '' overrides E# pin RW Bit Reserved SMBusTable: utput Control Register Byte 2 Pin # Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 36/37 DIF_5_En utput Control - '' overrides E# pin RW Low/Low Enable Bit 33/34 DIF_4_En utput Control - '' overrides E# pin RW Bit Reserved SMBusTable: Reserved Register Byte 3 Pin # Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit Reserved Bit Reserved SMBusTable: Reserved Register Byte 4 Pin # Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit Reserved Bit Reserved IDT 9ZXL65 REV C 45

12 9ZXL65 SMBusTable: Vendor & Revision ID Register Byte 5 Pin # Name Control Function Type Default Bit 7 - RID3 R X Bit 6 - RID2 R X REVISIN ID A rev = Bit 5 - RID R X Bit 4 - RID R X Bit 3 - VID3 R - - Bit 2 - VID2 R - - VENDR ID Bit - VID R - - Bit - VID R - - SMBusTable: DEVICE ID Byte 6 Pin # Name Control Function Type Default Bit 7 - Device ID 7 (MSB) R Bit 6 - Device ID 6 R Bit 5 - Device ID 5 R Bit 4 - Device ID 4 R FB Hex Bit 3 - Device ID 3 R Bit 2 - Device ID 2 R Bit - Device ID R Bit - Device ID R SMBusTable: Byte Count Register Byte 7 Pin # Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 - BC4 RW Bit 3 - BC3 Writing to this register configures how RW Default value is 8 hex, so 9 Bit 2 - BC2 RW bytes ( to 8) will be read back many bytes will be read back. Bit - BC RW by default. Bit - BC RW SMBusTable: Reserved Register Byte 8 Pin # Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit Reserved Bit Reserved IDT 2 9ZXL65 REV C 45

13 9ZXL65 Marking Diagram ICS XL65AL YYWW C LT Notes:. L denotes RoHS compliant package. 2. LT denotes the lot number. 3. C : country of origin. 4. YYWW is the last two digits of the year and week that the part was assembled. IDT 3 9ZXL65 REV C 45

14 9ZXL65 Package utline and Package Dimensions (NDG4) Package dimensions are kept current with JEDEC Publication No. 95 IDT 4 9ZXL65 REV C 45

15 9ZXL65 rdering Information Part / rder Number Shipping Package Package Temperature 9ZXL65AKLF Trays 4-pin VFQFPN to +7 C 9ZXL65AKLFT Tape and Reel 4-pin VFQFPN to +7 C "LF" suffix to the part number denotes Pb-Free configuration, RoHS compliant. A is the device revision designator (will not correlate with the datasheet revision). While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT 5 9ZXL65 REV C 45

16 9ZXL65 Revision History Rev. Issue Date Issuer Description Page # A /3/23 RDW Updated Electrical Tables with characterization data and moved to final. Various B /25/24. Updates to Byte 6, bits 7:4; default should be. RDW 2. Updated device ID in Byte 6 from 8B to FB. 2. Corrected Test Loads to remove references to IREF and Rp. These are C 3/3/25 RDW not present on parts that have LP-HCSL outputs. 9 IDT 6 9ZXL65 REV C 45

17 9ZXL65 SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support Corporate Headquarters Integrated Device Technology, Inc Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

18 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IDT (Integrated Device Technology): 9ZXL65AKLFT 9ZXL65AKLF 9ZXL65EKILFT 9ZXL65EKILF