Nineteen Output Differential Buffer for PCIe Gen3 9DB1933 DATASHEET

Transcription

1 DATASHEET 9DB933 Recommended Application 9 output PCIe Gen3 zero-delay/fanout buffer General Description The 9DB933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen and Gen. The 9DB933 is driven by a differential SRC output pair from an IDT 93S4, 93SQ4, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. Output Features 9 -.7V current mode differential HCSL output pairs Features/Benefits 8 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment dedicated and 3 group OE# pins/hardware control of the outputs PLL or bypass mode/pll can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Supports undriven differential outputs in Power Down mode for power management Key Specifications Cycle-to-cycle jitter <5ps Output-to-output skew < 5 ps PCIe Gen3 phase jitter <.ps RMS Functional Block Diagram OE(7_8)# OE(5_6)# OE(4:5)#, OE_34# 3 DIF_IN DIF_IN# PLL (SS Compatible) 9 DIF(8:) HIGH_BW# CKPWRGD/PD# SMB_A SMB_A SMB_A_PLLBYP# SMBDAT SMBCLK Logic IREF IDT

2 Pin Configuration SMB_A_PLLBYP# DIF_IN# DIF_IN OE_7_8# DIF_8# DIF_8 DIF_7# DIF_7 GND IREF 54 OE4# GNDA 53 DIF_3# VDDA 3 5 DIF_3 HIGH_BW# 4 5 OE3# VDD 5 5 DIF_# DIF_ 6 49 DIF_ DIF_# 7 48 OE# DIF_ 8 47 VDD DIF_# 9 46 GND 9DB933AKLF GND 45 DIF_# VDD 44 DIF_ DIF_ 43 OE# DIF_# 3 4 DIF_# DIF_3 4 4 DIF_ DIF_3# 5 4 OE# DIF_ DIF_9# DIF_4# 7 38 DIF_9 OE_34# 8 37 OE9# VDD DIF_6# DIF_ 6 OE_5_6# DIF_5# DIF_5 CKPWRGD/PD# DIF_4# DIF_4 SMB_A SMB_A DIF_8# DIF_8 OE8# DIF_7# DIF_7 OE7# GND VDD DIF_6# DIF_6 OE6# DIF_5# DIF_5 OE5# SMBDAT SMBCLK Power Down Functionality INPUTS OUTPUTS CKPWRGD/ DIF_IN/ PLL State PD# DIF_IN# DIF/DIF# Running Running ON Hi-Z OFF Power Groups Pin Number VDD GND Description 3 PLL, Analog 5,,7,47,63,8,46,64 DIF clocks IDT

3 Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. GNDA PWR Ground pin for the PLL core. 3 VDDA PWR 3.3V power for the PLL core. 4 HIGH_BW# IN 3.3V input for selecting PLL Band Width = High, = Low 5 VDD PWR Power supply, nominal 3.3V 6 DIF_ OUT.7V differential true clock output 7 DIF_# OUT.7V differential Complementary clock output 8 DIF_ OUT.7V differential true clock output 9 DIF_# OUT.7V differential Complementary clock output GND PWR Ground pin. VDD PWR Power supply, nominal 3.3V DIF_ OUT.7V differential true clock output 3 DIF_# OUT.7V differential Complementary clock output 4 DIF_3 OUT.7V differential true clock output 5 DIF_3# OUT.7V differential Complementary clock output 6 DIF_4 OUT.7V differential true clock output 7 DIF_4# OUT.7V differential Complementary clock output 8 OE_34# IN Active low input for enabling DIF pairs,,, 3 and 4. =disable outputs, = enable outputs 9 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant OE5# IN Active low input for enabling DIF pair 5. =disable outputs, = enable outputs DIF_5 OUT.7V differential true clock output 3 DIF_5# OUT.7V differential Complementary clock output 4 OE6# IN Active low input for enabling DIF pair 6. =disable outputs, = enable outputs 5 DIF_6 OUT.7V differential true clock output 6 DIF_6# OUT.7V differential Complementary clock output 7 VDD PWR Power supply, nominal 3.3V 8 GND PWR Ground pin. 9 OE7# IN Active low input for enabling DIF pair 7. =disable outputs, = enable outputs 3 DIF_7 OUT.7V differential true clock output 3 DIF_7# OUT.7V differential Complementary clock output 3 OE8# IN Active low input for enabling DIF pair 8. =disable outputs, = enable outputs 33 DIF_8 OUT.7V differential true clock output 34 DIF_8# OUT.7V differential Complementary clock output 35 SMB_A IN SMBus address bit (LSB) 36 SMB_A IN SMBus address bit IDT 3

4 Pin Description (cont.) PIN # PIN NAME PIN TYPE DESCRIPTION 37 OE9# IN Active low input for enabling DIF pair 9. =disable outputs, = enable outputs 38 DIF_9 OUT.7V differential true clock output 39 DIF_9# OUT.7V differential Complementary clock output 4 OE# IN Active low input for enabling DIF pair. =disable outputs, = enable outputs 4 DIF_ OUT.7V differential true clock output 4 DIF_# OUT.7V differential Complementary clock output 43 OE# IN Active low input for enabling DIF pair. =disable outputs, = enable outputs 44 DIF_ OUT.7V differential true clock output 45 DIF_# OUT.7V differential Complementary clock output 46 GND PWR Ground pin. 47 VDD PWR Power supply, nominal 3.3V 48 OE# IN Active low input for enabling DIF pair. =disable outputs, = enable outputs 49 DIF_ OUT.7V differential true clock output 5 DIF_# OUT.7V differential Complementary clock output 5 OE3# IN Active low input for enabling DIF pair 3. =disable outputs, = enable outputs 5 DIF_3 OUT.7V differential true clock output 53 DIF_3# OUT.7V differential Complementary clock output 54 OE4# IN Active low input for enabling DIF pair 4. =disable outputs, = enable outputs 55 DIF_4 OUT.7V differential true clock output 56 DIF_4# OUT.7V differential Complementary clock output 57 CKPWRGD/PD# IN A rising edge samples latched inputs and release Power Down Mode, a low puts the part into power down mode and tristates all outputs. 58 DIF_5 OUT.7V differential true clock output 59 DIF_5# OUT.7V differential Complementary clock output 6 OE_5_6# IN Active low input for enabling DIF pair 5 and 6. = tri-state outputs, = enable outputs 6 DIF_ 6 OUT.7V differential true clock output 6 DIF_6# OUT.7V differential Complementary clock output 63 VDD PWR Power supply, nominal 3.3V 64 GND PWR Ground pin. 65 DIF_7 OUT.7V differential true clock output 66 DIF_7# OUT.7V differential Complementary clock output 67 DIF_8 OUT.7V differential true clock output 68 DIF_8# OUT.7V differential Complementary clock output 69 OE_7_8# IN Active low input for enabling DIF pair 7, 8. = tri-state outputs, = enable outputs 7 DIF_IN IN.7 V Differential TRUE input 7 DIF_IN# IN.7 V Differential Complementary Input 7 SMB_A_PLLBYP# IN SMBus address bit. When Low, the part operates as a fanout buffer with the PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with the PLL operating. = fanout mode (PLL bypassed), = ZDB mode (PLL used) IDT 4

5 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES 3.3V Core Supply Voltage VDDA 4.6 V, 3.3V Logic Supply Voltage VDD 4.6 V, Input Low Voltage V IL GND-.5 V Input High Voltage V IH Except for SMBus interface V DD +.5V V Input High Voltage V IHSMB SMBus clock and data pins 5.5V V Storage Temperature Ts C Junction Temperature Tj 5 C Input ESD protection ESD prot Human Body Model V Guaranteed by design and characterization, not % tested in production. Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Parameters TA = T COM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Ambient Operating Temperature T COM Commmercial range 7 C Single-ended inputs, except SMBus, low Input High Voltage V IH threshold and tri-level inputs V DD +.3 V Single-ended inputs, except SMBus, low Input Low Voltage V IL threshold and tri-level inputs GND V I IN Single-ended inputs, V IN = GND, V IN = VDD -5 5 ua Input Current I INP Single-ended inputs V IN = V; Inputs with internal pull-up resistors V IN = VDD; Inputs with internal pull-down resistors - ua Input Frequency F ibyp V DD = 3.3 V, Bypass mode 66 MHz F ipll V DD = 3.3 V, MHz PLL mode 9 MHz Pin Inductance L pin 7 nh C IN Logic Inputs, except DIF_IN.5 5 pf Capacitance C INDIF_IN DIF_IN differential clock inputs.5.7 pf,4 C OUT Output pin capacitance.5 6 pf Clk Stabilization T STAB From V DD Power-Up and after input clock stabilization or de-assertion of PD# to st clock..8 ms, Input SS Modulation Frequency f MODIN Allowable Frequency (Triangular Modulation) 3 33 khz DIF start after OE# assertion OE# Latency t LATOE# DIF stop after OE# deassertion 4 cycles,3 DIF output enable after Tdrive_PD# t DRVPD PD# de-assertion 3 us,3 Tfall t F Fall time of control inputs 5 ns, Trise t R Rise time of control inputs 5 ns, SMBus Input Low Voltage V ILSMB.8 V SMBus Input High Voltage V IHSMB. V DDSMB V SMBus Output Low Voltage V I PULLUP.4 V SMBus Sink Current I V OL 4 ma Nominal Bus Voltage V DDSMB 3V to 5V +/- % V SCLK/SDATA Rise Time t RSMB (Max VIL -.5) to (Min VIH +.5) ns SCLK/SDATA Fall Time t FSMB (Min VIH +.5) to (Max VIL -.5) 3 ns SMBus Operating Frequency f MASMB Maximum SMBus operating frequency khz,5 Guaranteed by design and characterization, not % tested in production. Control input must be monotonic from % to 8% of input swing. 3 Time from deassertion until outputs are > mv 4 DIF_IN input 5 The differential input clock must be running for the SMBus to be active IDT 5

6 Electrical Characteristics - Clock Input Parameters TA = T COM or T IND; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Differential inputs Input High Voltage - DIF_IN V IHDIF (single-ended measurement) mv Differential inputs Input Low Voltage - DIF_IN V ILDIF (single-ended measurement) V SS mv Input Common Mode Voltage - DIF_IN V COM Common Mode Input Voltage 3 mv Input Amplitude - DIF_IN V SWING Peak to Peak value 3 45 mv Input Slew Rate - DIF_IN dv/dt Measured differentially.4 8 V/ns, Input Leakage Current I IN V IN = V DD, V IN = GND -5 5 ua Input Duty Cycle d tin Measurement from differential wavefrom % Input Jitter - Cycle to Cycle J DIFIn Differential Measurement 5 ps Guaranteed by design and characterization, not % tested in production. Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics - DIF.7V Current Mode Differential Outputs T A = T COM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Slew rate Trf Scope averaging on 4 V/ns,, 3 Slew rate matching Trf Slew rate matching, Scope averaging on %,, 4 Voltage High VHigh Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging mv Voltage Low VLow on) Max Voltage Vmax Measurement on single ended signal using absolute mv Min Voltage Vmin value. (Scope averaging off) -3 7 Vswing Vswing Scope averaging off mv, Crossing Voltage (abs) Vcross_abs Scope averaging off mv, 5 Crossing Voltage (var) -Vcross Scope averaging off 4 4 mv, 6 Guaranteed by design and characterization, not % tested in production. IREF = VDD/(3xR R ). For R R = 475Ω (%), I REF =.3mA. I OH = 6 x I REF and V OH Z O =5Ω (Ω differential impedance). Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential V. This results in a +/-5mV window around differential V. 4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics - Current Consumption TA = T COM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Operating Supply Current I DD3.3OP All outputs C L = Full load; 47 5 ma Powerdown Current I DD3.3PDZ All differential pairs tri-stated 3 4 ma Guaranteed by design and characterization, not % tested in production. IDT 6

7 Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics TA = T COM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES PLL Bandwidth BW -3dB point in High BW Mode 3 4 MHz -3dB point in Low BW Mode.7.4 MHz PLL Jitter Peaking t JPEAK Peak Pass band Gain.4 db Duty Cycle t DC Measured differentially, PLL Mode %, Duty Cycle Distortion t DCD Measured differentially, Bypass - %,,5 Skew, Input to Output t pdbyp Bypass Mode, nominal 5 C, 3.3V, V T = 5% t pdpll PLL Mode, nominal 5 C, 3.3V, V T = 5% DIF_IN, DIF [x:] t pd_byp (over specified voltage / temperature operating Input-to-Output Skew Variation in Bypass mode ranges) DIF_IN, DIF [x:] t pd_pll (over specified voltage / temperature operating Input-to-Output Skew Variation in PLL mode ranges) ps,,4 3 5 ps,,3 5 6 ps 5 35 ps,,4,6, 7,8,9, 3,,3,6, 7,8,9, 3 DIF[:] t JPH Differential Phase Jitter (RMS Value) ps,7, Differential Spread Spectrum Tracking Error (peak DIF[:] t SSTERROR 4 8 ps,7, to peak) Skew, Output to Output t sk3 V T = 5% 5 ps PLL mode 4 5 ps, Jitter, Cycle to cycle t jcyc-cyc Additive Jitter in Bypass Mode 5 5 ps, Guaranteed by design and characterization, not % tested in production. C LOAD = pf Measured from differential cross-point to differential cross-point 3 PLL mode Input-to-Output skew is measured at the first output edge following the corresponding input. 4 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 5 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 6 VT = 5% of Vout 7 This parameter is deterministic for a given device 8 Measured with scope averaging on to find mean value. 9 Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device. This parameter is measured at the outputs of two separate 9DB933 devices driven by a single main clock. The 9DB933's must be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the t is the period of the input clock Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9DB933 devices This parameter is measured at the outputs of two separate 9DB933 devices driven by a single main clock in Spread Spectrum mode. The 9DB933's must be set to high bandwidth. The spread spectrum characteristics are: maximum of.5%, 3-33KHz modulation frequency, linear 3 This parameter is an absolute value. It is not a double-sided figure. IDT 7

8 Electrical Characteristics - PCIe Phase Jitter Parameters TA = T COM; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes t jphpcieg PCIe Gen ps (p-p),,3 Phase Jitter, PLL Mode t jphpcieg PCIe Gen Lo Band ps.4 3 khz < f <.5MHz (rms), PCIe Gen High Band ps MHz < f < Nyquist (5MHz) (rms), PCIe Gen 3 ps t jphpcieg3.6 (PLL BW of -4MHz, CDR = MHz) (rms),,4 t jphpcieg PCIe Gen 3 5 ps (p-p),,3 Additive Phase Jitter, Bypass Mode PCIe Gen Lo Band khz < f <.5MHz t jphpcieg PCIe Gen High Band.5MHz < f < Nyquist (5MHz) PCIe Gen 3 t jphpcieg3 (PLL BW of -4MHz, CDR = MHz) Applies to all outputs. See for complete specs 3 Sample size of at least K cycles. This figures extrapolates to 8ps M cycles for a BER of -. 4 Subject to final radification by PCI SIG. ps (rms) ps (rms) ps (rms),,,,4 IDT 8

9 Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window Clock us.s.s.s us Clock Symbol Lg- -SSC -ppm error ppm + ppm error +SSC Lg+ Absolute Short-term Long-Term Long-Term Short-term Period Period Average Average Average Average Period Definition Minimum Minimum Minimum Absolute Absolute Absolute Nominal Maximum Maximum Maximum Period Period Period Units Notes DIF DIF ns,,3 Clock Periods Differential Outputs with Spread Spectrum Disabled Measurement Window Clock us.s.s.s us Clock Symbol Lg- -SSC -ppm error ppm + ppm error +SSC Lg+ Absolute Short-term Long-Term Long-Term Short-term Period Period Period Average Average Average Average Definition Minimum Minimum Minimum Absolute Absolute Absolute Nominal Maximum Maximum Maximum Period Period Period Units Notes DIF DIF ns,,3 Guaranteed by design and characterization, not % tested in production. All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK4B+/CK4BQ accuracy requirements. The 9DB933 itself does not contribute to ppm error. 3 Driven by SRC output of main clock, PLL or Bypass mode IDT 9

10 DIF Reference Clock Common Recommendations for Differential Routing Dimension or Value Unit Figure L length, route as non-coupled 5ohm trace.5 max inch L length, route as non-coupled 5ohm trace. max inch L3 length, route as non-coupled 5ohm trace. max inch Rs 33 ohm Rt 49.9 ohm Down Device Differential Routing L4 length, route as coupled microstrip ohm differential trace min to 6 max inch L4 length, route as coupled stripline ohm differential trace.8 min to 4.4 max inch Differential Routing to PCI Express Connector L4 length, route as coupled microstrip ohm differential trace.5 to 4 max inch L4 length, route as coupled stripline ohm differential trace.5 min to.6 max inch Figure : Down Device Routing L L Rs L4 L4' L' L' HCSL Output Buffer Rs Rt Rt PCI Express Down Device REF_CLK Input L3' L3 Figure : PCI Express Connector Routing L L Rs L4 L4' L' L' HCSL Output Buffer Rs Rt Rt PCI Express Add-in Board REF_CLK Input L3' L3 IDT

11 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R R R3 R4 Note.45v.v none ICS8743i- input compatible Standard LVDS Ra = Rb = R Ra = Rb = R Figure 3 L Ra L R3 L4 R4 L4' L' L' HCSL Output Buffer Rb Ra Rb Down Device REF_CLK Input L3' L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.K 5% R6a, R6b K 5% Cc. µf Vcm.35 volts Figure Volts Cc L4 R5a R5b Cc L4' R6a R6b PCIe Device REF_CLK Input IDT

12 General SMBus serial interface information for the 9DB933 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + - ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address DC (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (h) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + - ICS clock sends Byte through byte (if (h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address DC (h) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N + - P stop bit Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address DC (h) WR WRite Beginning Byte = N RT Repeat start Slave Address DD (h) RD ReaD Data Byte Count = Beginning Byte N Byte Note: Addresses show assumes pin 9 is low. N P Not acknowledge stop bit Byte N + - IDT

13 SMBusTable: Reserved Register Byte Pin # Name Control Function Type Default Bit 7 - Reserved R Bit 6 - Reserved R Bit 5 - Reserved R Bit 4 - Reserved R Bit 3 - Reserved R Bit - Reserved R Bit - Reserved R Bit - Reserved R SMBusTable: Output Control Register Byte Pin # Name Control Function Type Default Bit 7 DIF_7 Output Control RW Hi-Z Enable Bit 6 DIF_6 Output Control RW Hi-Z Enable Bit 5 DIF_5 Output Control RW Hi-Z Enable Bit 4 DIF_4 Output Control RW Hi-Z Enable Bit 3 DIF_3 Output Control RW Hi-Z Enable Bit DIF_ Output Control RW Hi-Z Enable Bit DIF_ Output Control RW Hi-Z Enable Bit DIF_ Output Control RW Hi-Z Enable SMBusTable: Output and PLL BW Control Register Byte Pin # Name Control Function Type Default Bit 7 see note PLL_BW# adjust RW High BW Low BW Bit 6 see note BYPASS# test mode / PLL RW Bypass PLL Bit 5 DIF_3 Output Control RW Hi-Z Enable Bit 4 DIF_ Output Control RW Hi-Z Enable Bit 3 DIF_ Output Control RW Hi-Z Enable Bit DIF_ Output Control RW Hi-Z Enable Bit DIF_9 Output Control RW Hi-Z Enable Bit DIF_8 Output Control RW Hi-Z Enable Note: Bit 7 is wired OR to the HIGH_BW# input, any selects High BW Note: Bit 6 is wired OR to the SMB_A_PLLBYP# input, any selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Byte 3 Pin # Name Control Function Type Default Bit 7 Readback - OE9# Input Bit 6 Readback - OE8# Input Bit 5 Readback - OE7# Input Bit 4 Readback - OE6# Input Bit 3 Readback - OE5# Input Bit Readback - OE_34# Input Bit 8 Readback - HIGH_BW# In Bit 7 Readback - SMB_A_PLLBYP# In IDT 3

14 SMBusTable: Output Enable Readback Register Byte 4 Pin # Name Control Function Type Default Bit 7 69 Readback - OE7_8# Input Bit 6 6 Readback - OE5_6# Input Bit 5 Reserved Bit 4 54 Readback - OE4# Input Bit 3 5 Readback - OE3# Input Bit 48 Readback - OE# Input Bit 43 Readback - OE# Input Bit 4 Readback - OE# Input SMBusTable: Vendor & Revision ID Register Byte 5 Pin # Name Control Function Type Default Bit 7 - RID3 R - - Bit 6 - RID R - - REVISION ID Bit 5 - RID R - - Bit 4 - RID R - - Bit 3 - VID3 R - - Bit - VID R - - VENDOR ID Bit - VID R - - Bit - VID R - - SMBusTable: DEVICE ID (94 Decimal or C Hex) Byte 6 Pin # Name Control Function Type Default Bit 7 - Device ID 7 (MSB) RW Reserved Bit 6 - Device ID 6 RW Reserved Bit 5 - Device ID 5 RW Reserved Bit 4 - Device ID 4 RW Reserved Bit 3 - Device ID 3 RW Reserved Bit - Device ID RW Reserved Bit - Device ID RW Reserved Bit - Device ID RW Reserved SMBusTable: Byte Count Register Byte 7 Pin # Name Control Function Type Default Bit 7 - BC7 RW - - Bit 6 - BC6 RW - - Bit 5 - BC5 RW - - Writing to this register Bit 4 - BC4 RW - - configures how many Bit 3 - BC3 RW - - bytes will be read back. Bit - BC RW - - Bit - BC RW - - Bit - BC RW - - IDT 4

15 SMBusTable: Output Control Register Byte 8 Pin # Name Control Function Type Default Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 DIF_8 Output Control RW Hi-Z Enable Bit 3 DIF_7 Output Control RW Hi-Z Enable Bit DIF_6 Output Control RW Hi-Z Enable Bit DIF_5 Output Control RW Hi-Z Enable Bit DIF_4 Output Control RW Hi-Z Enable SMBusTable: Reserved Register Byte 9 Pin # Name Control Function Type Default Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 RESERVED Bit RESERVED Bit RESERVED Bit RESERVED SMBus Address Mapping SMBus Address (Hex) D Main Clock (CKxxx) 9DB33 9DB433 9DB633 9DB833 9DB33 9DB933 D D4 D6 D8 DA DC DE Note: Indicates Bypass Mode. PLL is OFF. IDT 5

16 Index Area N Top V iew Seating Plane A Anvil Singulation OR Sawn Singulation A3 L E E (N -)x e D (Ref.) N (Ref.) ND & N Even e (T yp.) If N D & N are Even (N -)x (Ref.) b e D Chamfer 4x.6 x.6 max OPTIONAL. 8 C A C (Re f.) e N D & N Odd D D Thermal Base THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PAGE DIMENSIONS DIMENSIONS (mm) SYMBOL 7L SYMBOL MIN. MA. N 7 A.8. N D 8 A.5 N E 8 A3.5 Reference b.8.3 e D x E BASIC.5 BASIC. x. D MIN. / MA E MIN. / MA L MIN. / MA..3.5 Ordering Information Part / Order Number Shipping Packaging Package Temperature 9DB933AKLF Tubes 7-pin MLF to +7 C 9DB933AKLFT Tape and Reel 7-pin MLF to +7 C LF after the package code denotes the Pb-Free configuration, RoHS compliant. A is the device revision designator (will not correlate with the datasheet revision). IDT 6

17 Revision History Rev. Issue Date Who Description Page #. 7/7/ RDW Initial release - A 7// RDW. Updated 'PWD' to 'Default' in SMBus column headings. Updated electrical tables with char data 3. Added SMBusAddressing Table to page 5 5-8,3-5 Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc. 64 Silver Creek Valley Road San Jose, CA 9538 United States (outside U.S.) Asia Pacific and Japan IDT Singapore Pte. Ltd. Kallang Sector #7-/6 KolamAyer Industrial Park Singapore Phone: Fax: Europe IDT Europe Limited 3 Kingston Road Leatherhead, Surrey KT 7TU England Phone: Fax: Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 7