STEVAL-IME003V1. STHV748 Ultrasound Pulser IC evaluation board. Description. Features

Transcription

1 STEVAL-IME003V STHV748 Ultrasound Pulser IC evaluation board Data brief Description The STEVAL-IME003V evaluation board is designed around the STHV748 4-channel high voltage pulser, a state-of-the-art device designed for ultrasound imaging applications. The output waveforms can be displayed directly on an oscilloscope by connecting the scope probe to the relative s. 6 preset waveforms are available to test the HV pulser under varying conditions. Features 4-channel outputs: high voltage and low voltage connectors Load simulator using signal equivalent circuits Possibility to set up own load simulator 6 preset waveforms USB connector to connect STM3 with PC and supply power to it 4 MB serial Flash memory to host FPGA code and waveforms Memory expansion connector to add external serial Flash Connectors to supply high voltage and low voltage to the STHV748 output stage LEDs to monitor the power management stage Human machine interface to select, start and stop the generation of the preset waveforms 5 LEDs to monitor board behavior RoHS compliant August 05 DocID009 Rev / For further information contact your local STMicroelectronics sales office

2 Schematic diagram STEVAL-IME003V Schematic diagram Figure : STEVAL-IME003V hierarchical blocks / DocID009 Rev

3 3V3 STEVAL-IME003V Figure : STEVAL-IME003V FPGA bank 0 configuration Schematic diagram - + DocID009 Rev 3/

4 Schematic diagram Figure 3: STEVAL-IME003V FPGA bank configuration STEVAL-IME003V 4/ DocID009 Rev

5 STEVAL-IME003V Figure 4: STEVAL-IME003V FPGA bank configuration Schematic diagram DocID009 Rev 5/

6 U4C FPGA - Bank IO L0N_M0_CMPMISO T5 IO L0P_CCLK R5 IO L0N_CMPMOSI XC6SLX6-CSG34C MCU_FPGA_GPIO0 MCU_FPGA_GPIO MCU_FPGA_GPIO MCU_FPGA_GPIO3 MCU_FPGA_GPIO4 MCU_FPGA_GPIO5 MCU_FPGA_GPIO6 MCU_FPGA_GPIO7 V6 IO L0P_CMPCLK U6 T3 IO L03N_MOSI_CSI_B_MISO0 R3 U5 IO L05N V5 IO L05P U5 V4 IO LN_D_MISO3 IO L03P_D0_DIN_MISO_MISO IO LP_D_MISO IO L3N_D0 IO L3P_M IO L4N_D IO L4P_D T4 P N V3 U3 IO L5N N IO L5P M IO L6N_VREF T IO L6P R IO L9N V T IO L9P T P IO L0N P N0 IO L0P N0 N9 IO LN N9 M0 IO LP M0 V IO L3N V U IO L3P U T0 IO L9N_GCLK IO L9P_GCLK3 IO L30N_GCLK0_USERCCLK V0 IO L30P_GCLK_D3 IO L3N_GCLK30_D5 IO L3P_GCLK3_D4 IO L3N_GCLK8 IO L3P_GCLK9 R0 U0 T8 R8 V9 T9 IO L40N N8 IO L40P M8 IO L4N_VREF V8 IO L4P U8 IO L43N V7 U7 IO L43P U7 P8 IO L44N P8 N7 IO L44P N7 V6 IO L45N V6 T6 IO L45P T6 T7 IO L46N T7 R7 IO L46P R7 P7 IO L47N P7 N6 IO L47P N6 T5 IO L48N_RDWR_B_VREF IO L48P_D7 IO L49N_D4 IO L49P_D3 IO L6N_D6 IO L6P_D5 MCU_FPGA_GPIO[0:7] R5 V5 U5 T3 R3 IO L63N V4 IO L63P T4 IO L64N_D9 IO L64P_D8 IO L65N_CSO_B V3 IO L65P_INIT_B U3 P6 N5 FPGA_MODE0 CCLK FPGA_SPI_MOSI FPGA_SPI_MISO FPGA_SPI_MISO3 FPGA_SPI_MISO FPGA_MODE PROG_LED5 PROG_LED4 MCU_FPGA_GPIO6 MCU_FPGA_GPIO7 MCU_FPGA_GPIO4 MCU_FPGA_GPIO5 PROG_LED PROG_LED3 MCU_FPGA_GPIO MCU_FPGA_GPIO3 MCU_FPGA_GPIO0 MCU_FPGA_GPIO PROG_LED0 PROG_LED PROG_LED PROG_LED3 PROG_LED6 PROG_LED7 PROG_LED0 PROG_LED PROG_LED4 PROG_LED5 PROG_LED8 PROG_LED9 FPGA_SPI_SEL FPGA_INIT_B TP TEST POINT MCU_FPGA_GPIO[0:7] FPGA CONFIGURATION FPGA_INIT_B FPGA_MODE0 FPGA_MODE Configuration mode selection: FPGA_MODE0 = Parallel (Low) or Serial (High ) FPGA_MODE = Master (Low) or Slave (High) When FPGA_INIT_B (bidirectional open-drain) is Low the configuration memory s i being cleared. When held Low, the start of configuration is delayed. During configuration, a Low on this output indicates that a configuration dat error has occurred. SPI FLASH CTRL SIGNALS CCLK FPGA_SPI_MISO FPGA_SPI_MOSI FPGA_SPI_SEL FPGA_SPI_MISO FPGA_SPI_MISO3 J0 CON0 EXT SPI FLASH Place D9 close to J R7 56 +VFPGA_IO_3V3 Place R38 close to the FPGA device D9 R6 0K 040 TO CORRECT GREEN R38 33R 040 C33 Details: TDK (C0X7RA06K) - DIGIKEY ( ND) Dimension EIA 0 PROG_LED0 R7 R8 K K43 040DNP R9 PROG_LED R K43 040DNP C33 0uF 0V 0805 R K VFPGA_IO_3V3 C34 00nF MCU_FPGA_INIT_B MCU_FPGA_MODE FPGA_SPI_CCLK FPGA_SPI_MISO FPGA_SPI_MOSI FPGA_SPI_SEL FPGA_SPI_MISO FPGA_SPI_MISO3 MCU_FPGA_PROG R39 NA 040 R40 NA 040 PROG_LED PROG_LED3 PROG_LED4 PROG_LED5 PROG_LED6 PROG_LED7 R4 68R R 040 R3 68R 040 R5 68R 040 R7 68R 040 R9 68R 040 R3 68R 040 R33 68R 040 PROG0 D6 PROG D8 PROG D0 PROG3 D PROG4 D4 PROG5 D6 PROG6 D8 PROG7 D0 PROG_LED8 PROG_LED9 PROG_LED0 PROG_LED PROG_LED PROG_LED3 PROG_LED4 PROG_LED5 R5 68R 040 R0 68R 040 R4 68R 040 R6 68R 040 R8 68R 040 R30 68R 040 R3 68R 040 R34 68R 040 Kingbright KP-36SYC RS: LED 0805 PROG8 D7 PROG9 D9 PROG 0 D PROG D3 PROG D5 PROG 3 D7 PROG 4 D9 PROG 5 D Schematic diagram Figure 5: STEVAL-IME003V FPGA configuration STEVAL-IME003V SPI EXTERNAL PROGRAMMING HEADER AM00069v 6/ DocID009 Rev

7 STEVAL-IME003V Figure 6: STEVAL-IME003V FPGA bank 3 configuration Schematic diagram DocID009 Rev 7/

8 Schematic diagram Figure 7: STEVAL-IME003V FPGA power and configuration STEVAL-IME003V 8/ DocID009 Rev

9 HVP DVDD VDDP VDDM HVM INA INA IN3A INB INB IN3B INC INC IN3C IND IND IN3D IN4 THSD_EN INA INA IN3A INB INB IN3B INC INC IN3C IND IND IN3D IN4 HVP DVDD VDDP VDDM HVM THSD_EN R53 R60 C88 C04 C0 C77 70p 00V 0603 C86 C96 HVM HVM HVP 00 R6 C 70p 00V 0603 LVOUT_A LVOUT_B LVOUT_D LVOUT_C STHV74 8 J6, J7, J, J3, J5, J6, J9 and J30 Detail s Tyco Electronics ( ) - RS ( ) J BS J0 BS J J3 C80 R54 XDCR_A IN3A XDCR_D 70p 00V 0603 C8 00 C79 R55 R56 INA C78 IN3D 00 INA IND C8 U XDCR_B AGND IN4 DVDD RefHVM HVM_A _A INB INB IN3B BS J3 HVOUT_A A RefHVP HVP_A HVP_B Ref _B HVOUT_B _B HVM_B Ref D_CTRL D3 DFLS00 D33 DFLS00 J6 J9 J30 D35 DFLS00 D38 DFLS00 J7 D3 DFLS00 D36 DFLS00 BS J5 BS J9 IND DVDD RefHVP STHV748 INC INC IN3C 39 XDCR_C BS J3 C07 3.9n J6 C75 0p 0805 TP3 TESTPOINT THSD 00 R6 HVM HVP HVM C0 C3 C87 C9 D, D, D3,D4, D5, D6, D7, D8 diode DFLS00 rs-code C77, C80, C, C Details DigiKey ( ND) Murata (GRM88R7A7KA0D ) R58 0k J6, J7, J, J3, J5, J6, J9 and J30 Detail s Tyco Electronics ( ) - RS ( ) DVDD THSD_EN 3 THSD J4 CON3 STEVAL-IME003V Figure 8: STEVAL-IME003V configuration of the STHV748 Schematic diagram VDDP VDDM DGND 48 HVM_D 46 _D 45 HVOUT_D 44 _D 43 HVP_D 4 HVP_C 40 _C 38 Ref Ref RefHVM DVDD IN_D IN_D IN3_D VDDP GNDPW XDCR_D LVOUT_D LVOUT_A XDCR_A GNDPW VDDM IN3_A IN_A IN_A EN SUB HVOUT_C 37 _C 36 HVM_C 35 C76 C94 C00 C90 C0 C74 0p 0805 J5 C4 0p 0805 C84 3.9n C06 3.9n C9 n C98 n BS J4 BS J8 BS J7 BS J33 R57 0k C08 D34 DFLS00 C09 D37 DFLS00 BS J8 BS J34 C83 C85 3.9n C93 n C99 n C5 0p 0805 C89 C95 C05 C 70p 00V 0603 C97 C03 R63 R59 00k AGND 33 THSD 3 IN_C 3 IN_C 30 IN3_C 9 VDDM 8 GNDPW 7 XDCR_C 6 LVOUT_C 5 LVOUT_B 4 XDCR_B 3 GNDPW VDDP IN3_B 0 IN_B 9 IN_B 8 IN4 7 VDDM VDDP AM00050v DocID009 Rev 9/

10 Schematic diagram Figure 9: STEVAL-IME003V configuration of the STM3 STEVAL-IME003V 0/ DocID009 Rev

11 STEVAL-IME003V Revision history Table : Document revision history Date Version Changes -Aug-0 Initial release. 07-Aug-05 Updated title on the cover page. Revision history DocID009 Rev /

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