Power Management and Analog Companions (PMAAC) Application Note. AT73C240 Power-On and Power-Off Sequences. 1. Scope. 2. Operating Conditions

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1 AT73C240 Power-On and Power-Off Sequences 1. Scope This document decribes the sequences to apply to the AT73C240 product in order to operate the Power-On and Power-Off modes. The AT73C240 is a fully integrated, low-cost, combined stereo audio DAC and audio power amplifier circuit. The stereo DAC section is a complete high performance, stereo, audio digital-to-analog converter. It comprises a multibit sigma-delta modulator with dither, continuous time analog filters and analog output drive circuitry. Master clock is 256 or 384 times the input data rate, allowing choice of input data rate up to 48 khz, including standard audio rates of 48, 44.1, 32, 16 and 8 khz. The DAC section is followed by a volume and mute control and can be simultaneously played back directly through a stereo 32 Ohm headset pair of drivers. The stereo 32 Ohm headset pair of drivers also includes a mixer of a LINEL and LINER pair of stereo inputs. The Audio Power Amplifier is a differential amplifier designed in CMOS technology. It is capable of driving an 8 Ohm Loudspeaker at maximum power of 440mW. The volume, mute, power down, de-emphasis controls and audio formats are digitally programmable via a serial bus and the digital audio data are provided through a multiformat I2S interface. Power Management and Analog Companions (PMAAC) Application Note 2. Operating Conditions Table 2-1. Operating Condition Table For AT73C240 Product Parameter/Function Pads Min Max Unit Storage Temperature C Operating Temperature C Audio Power Input Voltage VBAT V Digital Input Voltage VDIG V Analog Input Voltage AVDD, AVDDHS V 3. Glossary DAC -- Digital to Analog Converter SPI -- Serial Peripheral Interface TWI -- Two Wire Interface I²S -- Integrated Interchip Sound Interface

2 4. AT73C240 Block Diagram Figure 4-1. AT73C240 Block Diagram PAINP HPN HPP CBP VBAT PAINN VREF GNDB AT73C240 VDIG -36 to +12dB / 3dB step Audio PA Voltage Reference AVDD AVDDHS LINER PGA SPI_DOUT INGND -36 to +12dB / 3dB step Status Registers SPI SPI_DIN / TWD SPI_CLK / TWCK LINEL PGA SPI_CSB / TW_ADD -6 to +6dB / 3dB step -46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step MCLK HSL 32 + driver VCM -6 to +6dB / 3dB step HSR 32 + driver DAC DAC Volume Control Volume Control + + Volume Control Volume Control Digital Filter Digital Filter Serial Audio I/F RSTB SMODE SDIN LRFS GNDA -46.5dB to 0dB / 1.5dB step -34.5dB to +12dB / 1.5dB step BCLK MONOP MONON MONO + GNDD 2 Application Note

3 Application Note 5. Hardware Setup 5.1 Application Block Diagram In this Application Note we describe Power-On and Power-Off sequences in the case of the use of the following application diagram. Figure 5-1. AT73C240 Application Block Diagram PAINN 3.6 V Battery (Li-Ion or 3 x NiMh or NiCd) 100n 22u C16 VBAT CBP AT73C240 VDIG 100n 2.8V from LDO C17 2.8V from LDO 8 Ohm Loudspeaker C7 HPP Audio PA HPN AVDD AVDDHS 100n C18 C19 10µF stereo line input (e.g. FM Radio) R L C12 470n C15 470n 470n C8 C3 470n PAINP MONOP MONON LINER LINEL REF DIG VREF VCM C9 10u C11 10u SPI_DOUT SPI_DIN/TWD SPI_CLK/TWCK SPI_CSB/TW_ADD SPI / TWI SMODE 32 Ohm Headset or Line Out C6 100u C5 100u 10u HSR HSL INGND Audio DAC MCLK SDIN LRFS BCLK RSTB Reset active low I2S C10 GNDA GNDD 5.2 Setup To perform any tests and measurements, it is necessary to have the following setup: VDIG = AVDDHS = AVDD = 2.8V VBAT = 3.6V SPI/TWI and I²S Interfaces connected The examples explained after are defined with the following DAC setup OVRSEL = 1 NBITS = 10 DEEMPEN = 1 DITHEN = 1 DINTSEL = 00 SPARE = 1 Write Bit [4] at 0x09 Address [DAC_CSFC Register] Write Bits [1:0] at 0x0A Address [DAC_MISC Register] Write Bit [2] at 0x0A Address [DAC_MISC Register] Write Bit [3] at 0x0A Address [DAC_MISC Register] Write Bits [4:5] at 0x0A Address [DAC_MISC Register] Write Bit [2] at 0x0B Address [Private Register] 3

4 6. Power-On and Power-Off Sequences 6.1 Playback Mode The Playback Mode corresponds to a data transfer from the i²s interface to the headset connector. Below is a diagram that shows the data path. Figure 6-1. AT73C240 Playback Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Power-On Sequence HEADSET ON - ROLC & LOLC = -5dB Write all Bits at 0x07 address - ONLNOR & ONLNOL = 1 Write Bits [2:3] = 0x00 address - ONMSTR & PRCHG = 1 Write Bits [1:0] = 0x0C address I²S ON - LMPG = -34.5dB Write Bits [5:0] = 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x04 address - RESFILZ & RSTZ = 1 Write Bits [1:0] = 0x10 address - PRCHG = 0 Write Bit [1] = 0x0C address Wait 1ms INCREASE GAIN - ONDACL & ONDACR = 1 Write Bits [4:5] = 0x00 address - ROLC & LOLC = xxx Write these bits to obtain desired output gain value - LMPG & RMPG = xxx Write these bits to obtain desired output gain value 4 Application Note

5 Application Note Power-Off Sequence DECREASE GAIN - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LMPG = -34.5dB Write Bits [5:0] = 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x04 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = 0x00 address - RESFILZ = 0 Write Bit [1] = 0x10 address - RSTZ = 1 Write Bit [0] = 0x10 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = 0x0C address - ONLNOR & ONLNOL = 0 Write Bits [2:3] = 0x00 address 5

6 6.2 Playback Amplified Mode The Playback Amplified mode corresponds to a data transfer from the i²s interface to the power amplifier output connector. Below is a diagram that shows the data path. Figure 6-2. AT73C240 Playback Amplified Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Power-On Sequence SET GAIN AT THE MINIMUM - LMPG = -34.5dB Write Bits [5:0] = 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x04 address MASTER ON - ONMSTR & PRCHG = 1 Write Bits [1:0] = 0x0C address I²S ON - RESFILZ & RSTZ = 1 Write Bits [1:0] = 0x10 address - PRCHG = 0 Write Bit [1] = 0x0C address Wait 1ms PA ON - ONPADRV = 1 Write Bit [6] = 0x00 address - APAPRECH = 1 Write Bit [4] = 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = 0x11 address - APAON = 1 Write Bit [5] = 0x11 address Wait 10ms - APAGAIN = xxdb Write these bits to obtain desired output gain value - LMPG & RMPG = xxdb Write these bits to obtain desired output gain value 6 Application Note

7 Application Note Power-Off Sequence DECREASE GAIN - LMPG = -34.5dB Write Bits [5:0] = 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x04 address PA OFF - ONPADRV = 0 Write Bit [6] = 0x00 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = 0x00 address - RESFILZ = 0 Write Bit [1] = 0x10 address - RSTZ = 1 Write Bit [0] = 0x10 address MASTER OFF - ONMSTR = 0 Write Bit [0] = 0x0C address 7

8 6.3 Playback + Playback Amplified Mode This mode corresponds to a data transfer from the i²s interface to the headset and to the power amplifier output connectors. Below is a diagram that shows the data path. Figure 6-3. AT73C240 Playback + Playback Amplified Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Power-On Sequence SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at 0x07 address - ONPADRV = 1 Write Bit [6] = 0x00 address HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = 0x00 address - ONMSTR & PRCHG = 1 Write Bits [1:0] = 0x0C address I²S ON - LMPG = -34.5dB Write Bits [5:0] = 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x04 address - RESFILZ & RSTZ = 1 Write Bits [1:0] = 0x10 address - PRCHG = 0 Write Bit [1] = 0x0C address Wait 1ms - ONDACL & ONDACR = 1 Write Bits [4:5] = 0x00 address PA ON - APAPRECH = 1 Write Bit [4] = 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = 0x11 address - APAON = 1 Write Bit [5] = 0x11 address 8 Application Note

9 Application Note Wait 10ms - APAGAIN = xxdb Write these bits to obtain desired output gain value - ROLC & LOLC = xxx Write these bits to obtain desired output gain value - LMPG & RMPG = xxx Write these bits to obtain desired output gain value Power-Off Sequence DECREASE GAIN PA OFF I²S OFF - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LMPG = -34.5dB Write Bits [5:0] = 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x04 address - ONPADRV = 0 Write Bit [6] = 0x00 address - ONDACL & ONDACR = 0 Write Bits [4:5] = 0x00 address - RESFILZ = 0 Write Bit [1] = 0x10 address - RSTZ = 1 Write Bit [0] = 0x10 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = 0x0C address - ONLNOR & ONLNOL = 0 Write Bits [2:3] = 0x00 address 9

10 6.4 Bypass Mode This mode corresponds to a data transfer from the line-in input connectors to the headset connector. Below is a diagram that shows the data path. Figure 6-4. AT73C240 Bypass Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Power-On Sequence SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x02 address HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = 0x00 address - ONMSTR = 1 Write Bit [0] = 0x0C address LINE_IN ON Power-Off Sequence SET GAIN AT MINIMUM - ONLNIR & ONLNIL = 1 Write Bits [1:0] = 0x00 address - RLIG & LLIG= xxdb Write these bits to obtain desired output gain value - ROLC & LOLC = xxdb Write these bits to obtain desired output gain value - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x02 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = 0x00 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = 0x0C address 10 Application Note

11 Application Note - ONLNOR & ONLNOL = 0 Write Bits [2:3] = 0x00 address 11

12 6.5 Bypass Amplified Mode This mode corresponds to a data transfer from the line-in input connectors to the power amplifier output connector. Below is a diagram that shows the explained path. Figure 6-5. AT73C240 Bypass Amplified Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Power-On Sequence SET GAIN AT MINIMUM - LLIG = -33dB Write Bits [4:0] = 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x02 address - ONPADRV = 1 Write Bit [6] = 0x00 address MASTER ON - ONMSTR = 1 Write Bits [0] = 0x0C address LINE_IN ON - ONLNIR & ONLNIL = 1 Write Bits [1:0] = 0x00 address PA ON - ONPADRV = 1 Write Bit [6] = 0x00 address - APAPRECH = 1 Write Bit [4] = 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = 0x11 address - APAON = 1 Write Bit [5] = 0x11 address Wait 10ms 12 Application Note

13 Application Note Power-Off Sequence SET GAIN AT MINIMUM PA OFF - APAGAIN = xxdb Write these bits to obtain desired output gain value - RLIG & LLIG= xxdb Write these bits to obtain desired output gain value - LLIG = -33dB Write Bits [4:0] = 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x02 address - ONPADRV = 0 Write Bit [6] = 0x00 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = 0x00 address MASTER OFF - ONMSTR = 0 Write Bit [0] = 0x0C address 13

14 6.6 Bypass + Bypass Amplified Mode This mode corresponds to a data transfer from the line-in input connectors to the headset and to the power amplifier output connectors. Below is a diagram that shows the data path. Figure 6-6. AT73C240 Bypass + Bypass Amplified Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Power-On Sequence SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x02 address - ONPADRV = 1 Write Bit [6] = 0x00 address HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = 0x00 address - ONMSTR = 1 Write Bit [0] = 0x0C address LINE_IN ON - ONLNIR & ONLNIL = 1 Write Bits [1:0] = 0x00 address PA ON - ONPADRV = 1 Write Bit [6] = 0x00 address - APAPRECH = 1 Write Bit [4] = 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = 0x11 address - APAON = 1 Write Bit [5] = 0x11 address 14 Application Note

15 Application Note Wait 10ms Power-Off Sequence SET GAIN AT MINIMUM PA OFF - APAGAIN = xxdb Write these bits to obtain desired output gain value - RLIG & LLIG= xxdb Write these bits to obtain desired output gain value - ROLC & LOLC = xxdb Write these bits to obtain desired output gain value - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x02 address - ONPADRV = 0 Write Bit [6] = 0x00 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = 0x00 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = 0x0C address - ONLNOR & ONLNOL = 0 Write Bits [2:3] = 0x00 address 15

16 7. Switching Modes Sequences 7.1 Playback Mode to Playback Amplified Mode This section shows how to switch from the Playback Mode to Playback Amplified Mode. Below is a diagram that shows the switching modes. Figure 7-1. AT73C240 Playback Mode to Playback Amplified Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Switch Sequence AT73C240 is already starts in Playback Mode as defined in Section 6.1. DECREASE GAIN - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LMPG = -34.5dB Write Bits [5:0] = 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x04 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = 0x00 address - RESFILZ = 0 Write Bit [1] = 0x10 address - RSTZ = 1 Write Bit [0] = 0x10 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = 0x0C address - ONLNOR & ONLNOL = 0 Write Bits [2:3] = 0x00 address MASTER ON - ONMSTR & PRCHG = 1 Write Bits [1:0] = 0x0C address 16 Application Note

17 Application Note I²S ON - RESFILZ & RSTZ = 1 Write Bits [1:0] = 0x10 address - PRCHG = 0 Write Bit [1] = 0x0C address Wait 1ms - ONDACL & ONDACR = 1 Write Bits [4:5] = 0x00 address PA ON - ONPADRV = 1 Write Bit [6] = 0x00 address - APAPRECH = 1 Write Bit [4] = 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = 0x11 address - APAON = 1 Write Bit [5] = 0x11 address Wait 10ms - APAGAIN = xxdb Write these bits to obtain desired output gain value - LMPG = xxdb Write these bits to obtain desired output gain value - RMPG = xxdb Write these bits to obtain desired output gain value 17

18 7.2 Playback Amplified Mode to Playback Mode This section shows how to switch from the Playback Amplified Mode to Playback Mode. Below is a diagram that shows the switching modes. Figure 7-2. AT73C240 Playback Amplified Mode to Playback Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Switch Sequence AT73C240 is already starts in Playback Amplified Mode as defined in Section 6.2. DECREASE GAIN - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LMPG = -34.5dB Write Bits [5:0] = 0x03 address - RMPG = -34.5dB Write Bits [5:0] = 0x04 address PA OFF - ONPADRV = 0 Write Bit [6] = 0x00 address I²S OFF - ONDACL & ONDACR = 0 Write Bits [4:5] = 0x00 address - RESFILZ = 0 Write Bit [1] = 0x10 address - RSTZ = 1 Write Bit [0] = 0x10 address MASTER OFF - ONMSTR = 0 Write Bit [0] = 0x0C address HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = 0x00 address - ONMSTR & PRCHG = 1 Write Bits [1:0] = 0x0C address 18 Application Note

19 Application Note I²S ON - RESFILZ & RSTZ = 1 Write Bits [1:0] = 0x10 address - PRCHG = 0 Write Bit [1] = 0x0C address Wait 1ms - ONDACL & ONDACR = 1 Write Bits [4:5] = 0x00 address INCREASE GAIN - ROLC & LOLC = xxx Write these bits to obtain desired output gain value - LMPG & RMPG = xxx Write these bits to obtain desired output gain value 19

20 7.3 Bypass Mode to Bypass Amplified Mode This section shows how to switch from the Bypass Mode to Bypass Amplified Mode. Below is a diagram that shows the switching modes. Figure 7-3. AT73C240 Bypass Mode to Bypass Amplified Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Switch Sequence AT73C240 is already starts in Bypass Mode as defined in Section 6.4. SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x02 address - ONPADRV = 1 Write Bit [6] = 0x00 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = 0x00 address HEADSET OFF - ONMSTR = 0 Write Bit [0] = 0x0C address - ONLNOR & ONLNOL = 0 Write Bits [2:3] = 0x00 address MASTER ON - ONMSTR = 1 Write Bits [0] = 0x0C address LINE_IN ON - ONLNIR & ONLNIL = 1 Write Bits [1:0] = 0x00 address PA ON 20 Application Note

21 Application Note - ONPADRV = 1 Write Bit [6] = 0x00 address - APAPRECH = 1 Write Bit [4] = 0x11 address Wait 50ms - APAPRECH = 0 Write Bit [4] = 0x11 address - APAON = 1 Write Bit [5] = 0x11 address Wait 10ms - APAGAIN = xxdb Write these bits to obtain desired output gain value - RLIG & LLIG= xxdb Write these bits to obtain desired output gain value 21

7.4 Bypass Amplified Mode to Bypass Mode This section shows how to switch from the Bypass Amplified Mode to Bypass Mode. Below is a diagram that shows the switching modes. Figure 7-4.

22 7.4 Bypass Amplified Mode to Bypass Mode This section shows how to switch from the Bypass Amplified Mode to Bypass Mode. Below is a diagram that shows the switching modes. Figure 7-4. AT73C240 Bypass Amplified Mode to Bypass Mode Diagram SPI / TWI AT73C240 I2S Interface DAC Headset Line Input Mono Power Amplifier Switch Sequence AT73C240 is already starts in Bypass Amplified Mode as defined in Section 6.5. SET GAIN AT MINIMUM - ROLC & LOLC = -5dB Write all Bits at 0x07 address - LLIG = -33dB Write Bits [4:0] = 0x01 address - RLIG = -33dB Write Bits [4:0] = 0x02 address - ONPADRV = 1 Write Bit [6] = 0x00 address LINE_IN OFF - ONLNIR & ONLNIL = 0 Write Bits [1:0] = 0x00 address PA OFF - ONPADRV = 0 Write Bit [6] = 0x00 address MASTER OFF - ONMSTR = 0 Write Bit [0] = 0x0C address HEADSET ON - ONLNOR & ONLNOL = 1 Write Bits [2:3] = 0x00 address - ONMSTR = 1 Write Bit [0] = 0x0C address 22 Application Note

23 Application Note LINE_IN ON - ONLNIR & ONLNIL = 1 Write Bits [1:0] = 0x00 address INCREASE GAIN - ROLC & LOLC = xxx Write these bits to obtain desired output gain value - LLIG = xxdb Write these bits to obtain desired output gain value - RLIG = xxdb Write these bits to obtain desired output gain value 23

24 8. Revision History Doc. Rev Date Comments Change Request Ref. 6466A 04-JUn-09 Creation 24 Application Note

25 Application Note 25

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