Striking the Balance Driving Increased Density and Cost Reduction in Printed Circuit Board Designs
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1 Striking the Balance Driving Increased Density and Cost Reduction in Printed Circuit Board Designs Tim Swettlen & Gary Long Intel Corporation Tuesday, Oct 22, 2013
2 Legal Disclaimer The presentation is intended only to provide the general insights, opinions, and internally developed guidelines and procedures of Intel Corporation (Intel) and is not to be relied upon for any purpose other than educational. The information in this presentation may need to be adapted to your specific situation or work environment. Any named third party suppliers are provided for information only. Intel accepts no liability for the quality of third party suppliers and cannot guarantee the correct or suitable operation of third party products. The recipient of this presentation remains solely responsible for the design, manufacture, sale, and functionality of its product, including any liability arising from product infringement or product warranty. TO THE EXTENT INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS. Intel assumes no liability and disclaims any express or implied warranty regarding the information in the presentation, including any liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel accepts no liability that you, or a third party might suffer due to your failure to heed the warning in this disclaimer. Intel makes no representation or warranties regarding the presentation's accuracy or completeness and accepts no duty to update the presentation based on more current information. Intel may make changes to this presentation and to any dates, target dates, specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications. The Intel products in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user. Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2013, Intel Corporation. All rights reserved.
3 OUTLINE Introduction HDI Market Growth and Trends HDI Technology Envelopes and Design Rules HDI Capability Benefits and Dependencies of HDI Design HDI Cost Analysis Intel HDI Design Conversion Study Conclusion Question and Answer 3
4 HDI Market Growth and Trends Source: Prismark Aug 2013 Report The top growth segments in the PCB industry are all utilizing HDI designs
5 HDI Market Growth and Trends Source: Prismark Aug 2013 Report Handsets are dominated by HDI and Flex designs
6 HDI Market Growth and Trends Source: Prismark Aug 2013 Report Personal computer applications are a fast growing segment for HDI and flex designs
7 HDI Technology Envelopes Mainstream = Entry level low cost technology for HDI designs Advanced = Best technology available in high volume
8 Basic HDI Design Rules Design rules will get more difficult even as cost per area reduces.
9 HDI capability levels used for analysis 10 layer anylayer design
10 % of suppliers capable at the defined HDI excellent capability levels 10 layer anylayer design
11 % of suppliers capable at the defined HDI moderate capability levels 10 layer anylayer design Better capability = better yields, lower cost, better technology
12 Benefits and Dependencies of HDI Design Less via perforations in power planes for improved power delivery Tighter coupling between power and ground planes reducing spreading inductance Elimination of via stubs for improved signal performance Ability to ground stitch without dramatic impact to routing density HDI allows for smaller form factors which are needed to offset the higher cost/area for HDI PCBs
13 HDI Cost Analysis HDI costs are still reducing year over year, while PTH costs remain flat requiring less reduction in area to achieve equivalent costs
14 HDI Cost Analysis Intel should cost analysis of 17 current Ultrabook, 2 in1, or tablet designs HDI can achieve similar cost/pcb to PTH designs
15 HDI Cost Analysis Intel should cost analysis of 17 current Ultrabook, 2 in1, or tablet designs HDI can achieve similar cost/pcb to PTH designs by reducing total board area
16 Intel HDI Design Conversion Study Form Factor reduction requires analyzing the total BOM for reduction opportunities
17 Conclusion HDI capability and capacity is on a rapid growth curve. There are power delivery and signaling benefits which can be utilized. The key to cost equalization is form factor reduction. Industry should drive conversion to HDI to accelerate cost reduction and utilize benefits to HDI technology even faster than today s predictions.
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19 contacts:
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