ICS9DB Output PCI Express* Buffer with CLKREQ# Function DATASHEET. Description. Features/Benefits

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1 DATASHEET ICS9DB106 Description The ICS9DB106 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB106 is driven by a differential SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS or ICS It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. Output Features 6-0.7V current mode differential output pairs (HSCL) SMBus for complete device control Features/Benefits CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications PLL or bypass mode/pll can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL s Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Key Specifications Cycle-to-cycle jitter < 35ps Output-to-output skew < 45ps Funtional Block Diagram CLKREQ1# CLKREQ4# CLK_INT CLK_INC SPREAD COMPATIBLE PLL PCIE1 PCIE4 PLL_BW SMBDAT SMBCLK CONTROL LOGIC PCIE(0,2,3,5) IREF IDT TM /ICS TM ICS9DB106 REV F 12/14/07 1

2 Pin Configuration PLL_BW 1 CLK_INT 2 CLK_INC 3 **CLKREQ1# 4 PCIET0 5 PCIEC0 6 VDD 7 GND 8 PCIET1 9 PCIEC1 10 PCIET2 11 PCIEC2 12 VDD 13 SMBDAT 14 ICS9DB VDDA 27 GNDA 26 IREF 25 **CLKREQ4# 24 PCIET5 23PCIEC5 22 VDD 21 GND 20 PCIET4 19 PCIEC4 18 PCIET3 17 PCIEC3 16 VDD 15 SMBCLK Note:Pins preceeded by '**' have internal 120K ohm pull down resistors 28-pin SSOP & TSSOP Power Groups Pin Number VDD GND Description 7, 13, 16, 22 8,21 PCI Express Outputs TBD TBD SMBUS N/A 27 IREF Analog VDD & GND for PLL core IDT TM /ICS TM ICS9DB106 REV F 12/14/07 2

3 Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 PLL_BW IN 3.3V input for selecting PLL Band Width 0 = low, 1= high 2 CLK_INT IN "True" reference clock input. 3 CLK_INC IN "Complementary" reference clock input. 4 **CLKREQ1# IN Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated 5 PCIET0 OUT True clock of differential PCI_Express pair. 6 PCIEC0 OUT Complement clock of differential PCI_Express pair. 7 VDD PWR Power supply, nominal 3.3V 8 GND IN Ground pin. 9 PCIET1 OUT True clock of differential PCI_Express pair. 10 PCIEC1 OUT Complement clock of differential PCI_Express pair. 11 PCIET2 OUT True clock of differential PCI_Express pair. 12 PCIEC2 OUT Complement clock of differential PCI_Express pair. 13 VDD PWR Power supply, nominal 3.3V 14 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant 15 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant 16 VDD PWR Power supply, nominal 3.3V 17 PCIEC3 OUT Complement clock of differential PCI_Express pair. 18 PCIET3 OUT True clock of differential PCI_Express pair. 19 PCIEC4 OUT Complement clock of differential PCI_Express pair. 20 PCIET4 OUT True clock of differential PCI_Express pair. 21 GND PWR Ground pin. 22 VDD PWR Power supply, nominal 3.3V 23 PCIEC5 OUT Complement clock of differential PCI_Express pair. 24 PCIET5 OUT True clock of differential PCI_Express pair. 25 **CLKREQ4# IN Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated 26 IREF OUT This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 27 GNDA PWR Ground pin for the PLL core. 28 VDDA PWR 3.3V power for the PLL core. Note: Pins preceeded by '**' have internal 120K ohm pull down resistors IDT TM /ICS TM ICS9DB106 REV F 12/14/07 3

4 Absolute Max Symbol Parameter Min Max Units VDDA 3.3V Core Supply Voltage V DD + 0.5V V VDD 3.3V Output Supply Voltage GND V DD + 0.5V V Ts Storage Temperature C Tambient Ambient Operating Temp 0 70 C Tcase Case Temperature 115 C Input ESD protection ESD prot human body model 2000 V Electrical Characteristics - Input/Supply/Common Output Parameters T A = 0-70 C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS Notes Input High Voltage V IH 3.3 V +/-5% 2 V DD V 1 Input Low Voltage V IL 3.3 V +/-5% V SS V 1 Input High Current I IH V IN = V DD -5 5 ua 1 Input Low Current I IL1 V IN = 0 V; Inputs with no pullup resistors -5 ua 1 I IL2 V IN = 0 V; Inputs with pull-up resistors -200 ua 1 Operating Supply Current I DD3.3OP Full Active, C L = Full load; ma 1 all differential pairs tri-stated ma 1 Input Frequency F i V DD = 3.3 V MHz Pin Inductance L pin 7 nh 1 Input Capacitance C IN Logic Inputs 5 pf 1 C OUT Output pin capacitance 4.5 pf 1 From VDD reaching 3.1V and Clk Stabilization T STAB input clock stable 1.8 ms 1 Input Spread Spectrum Modulation Frequency Triangular Modulation khz 1 SMBus Voltage V DD V 1 Low-level Output Voltage V I PULLUP 0.4 V 1 Current sinking at V OL = 0.4 V I PULLUP 4 ma 1 SCLK/SDATA (Max VIL ) to T RI2C Clock/Data Rise Time (Min VIH ) 1000 ns 1 SCLK/SDATA (Min VIH ) to T Clock/Data Fall Time FI2C (Max VIL ) 300 ns 1 1 Guaranteed by design and characterization, not 100% tested in production. IDT TM /ICS TM ICS9DB106 REV F 12/14/07 4

5 Electrical Characteristics - PCIE 0.7V Current Mode Differential Outputs T A = 0-70 C; V DD = 3.3 V +/-5%; C L =2pF, R S =33.2Ω, R P =49.9Ω, Ι REF = 475Ω PARAMETER SYMBOL CONDITIONS MIN TYP MA UNITS NOTES Current Source Output Impedance Zo 1 V O = V x 3000 Ω 1 Voltage High VHigh Statistical measurement on single ,3 Voltage Low VLow ended signal using oscilloscope math function mv 1,3 Max Voltage Vovs Measurement on single ended ,3 mv Min Voltage Vuds signal using absolute value ,3 Crossing Voltage (abs) Vcross(abs) mv 1,3 Crossing Voltage (var) d-vcross Variation of crossing over all edges 140 mv 1,3 Long Accuracy ppm see Tperiod min-max values 0 ppm 1,2 Average period T period MHz nominal ns MHz spread ns 2 Absolute min period T absmin MHz nominal/spread ns 1,2 Rise Time t r V OL = 0.175V, V OH = 0.525V ps 1 Fall Time t f V OH = 0.525V V OL = 0.175V ps 1 Rise Time Variation d-t r 125 ps 1 Fall Time Variation d-t f 125 ps 1 Input to Output Delay t pd PLL Mode ps 1 t pdbyp Bypass mode ns 1 Measurement from differential Duty Cycle d t3 wavefrom % 1 Output-to-Output Skew t sk3 V T = 50% 45 ps 1 PLL mode, Jitter, Cycle to cycle t jcyc-cyc Measurement from differential 35 ps 1 wavefrom BYPASS mode as additive jitter 35 ps 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements 3 I REF = V DD /(3xR R ). For R R = 475Ω (1%), I REF = 2.32mA. I OH = 6 x I REF and V OH = Z O =50Ω. IDT TM /ICS TM ICS9DB106 REV F 12/14/07 5

6 Electrical Characteristics - PLL Parameters T A = 0-70 C; Supply Voltage V DD = 3.3 V +/-5% Group Parameter Description Min Typ Max Units Notes PLL Jitter Peaking j peak-hibw (PLL_BW = 1) db 1,4 PLL Jitter Peaking j peak-lobw (PLL_BW = 0) db 1,4 PLL Bandwidth pll HIBW (PLL_BW = 1) MHz 1,5 PLL Bandwidth pll LOBW (PLL_BW = 0) MHz 1,5 PCIe Gen 1 phase jitter ( MHz) ps 1,2,3 PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz ps rms 1,2,3 Jitter, Phase t jphasepll (PLL_BW=1) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz ps rms 1,2,3 (PLL_BW=0) PCIe Gen 2 jitter (8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz ps rms 1,2,3 NOTES: 1. Guaranteed by design and characterization, not 100% tested in production. 2. See for complete specs 3. Device driven by 932S421BGLF or equivalent 4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking. 5. Measured at 3 db dow n or half pow er point. IDT TM /ICS TM ICS9DB106 REV F 12/14/07 6

7 SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value Unit Figure L1 length, Route as non-coupled 50 ohm trace. 0.5 max inch 1 L2 length, Route as non-coupled 50 ohm trace. 0.2 max inch 1 L3 length, Route as non-coupled 50 ohm trace. 0.2 max inch 1 Rs 33 ohm 1 Rt 49.9 ohm 1 Down Device Differential Routing Dimension or Value Unit Figure L4 length, Route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 1 L4 length, Route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1 Differential Routing to PCI Express Connector Dimension or Value Unit Figure L4 length, Route as coupled microstrip 100 ohm differential trace to 14 max inch 2 L4 length, Route as coupled stripline 100 ohm differential trace min to 12.6 max inch 2 Figure 1 Down device routing. L1 L2 Rs L1 L2 Rs Rt Rt L4 L4 HSCL Output Buffer L3 L3 PCI Ex Board Down Device REF_CLK Input Figure 1 Figure 2 PCI Express Connector Routing. L1 L2 Rs L1 L2 Rs Rt Rt L4 L4 HSCL Output Buffer L3 L3 PCI Ex Add In Board REF_CLK Input Figure 2 IDT TM /ICS TM ICS9DB106 REV F 12/14/07 7

8 Alternative termination for LVDS and other common differential signals. Figure 3. Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45 v 0.22v none 100 ICS874003i-02 input compatible Standard LVDS R1a = R1b = R1 Figure_3. L1 L2 R1a L1 L2 R1b R3 R2a R2b L4 L4 R4 HSCL Output Buffer L3 L3 Down Device REF_CLK Input R2a = R2b = R2 Cable connected AC coupled application, figure 4 Component Value Note R5a,R5b 8.2K 5% R6a,R6b Cc 1K 5% 0.1 uf Vcm volts 3.3 Volts R5a R5b L4 L4 Cc Cc R6a R6b Figure_4. PCIe Device REF_CLK Input IDT TM /ICS TM ICS9DB106 REV F 12/14/07 8

9 General SMBus serial interface information for the ICS9DB106 How to Write: Controller (host) sends a start bit. Controller (host) sends the write address D4 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + -1) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit. Controller (host) sends the write address D4 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (h) ICS clock will acknowledge ICS clock will send the data byte count = ICS clock sends Byte N + -1 ICS clock sends Byte 0 through byte (if (h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Write Operation Controller (Host) T start bit Slave Address D4 (h) WR WRite Beginning Byte = N Data Byte Count = Beginning Byte N Byte N P stop bit Byte ICS (Slave/Receiver) Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T start bit Slave Address D4 (h) WR WRite Beginning Byte = N RT Repeat start Slave Address D5 (h) RD ReaD Data Byte Count = Beginning Byte N Byte N P Not acknowledge stop bit Byte N IDT TM /ICS TM ICS9DB106 REV F 12/14/07 9

10 SMBusTable: Device Control Register, READ/WRITE ADDRESS (D4/D5) Byte 0 Pin # Name Control Function Type 0 1 PWD Bit 7 - SW_EN Enables SMBus Control RW PLL controlled by PLL controlled by SMBus registers device pins 1 Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - PLL BW #adjust Selects PLL Bandwidth RW Low BW High BW 1 Bit 0 - PLL Enable Bypasses PLL for PLL bypassed (fan PLL enabled (ZDB RW board test out mode) mode) 1 SMBusTable: Output Enable Register Byte 1 Pin # Name Control Function Type 0 1 PWD Bit 7 - RESERVED RW - Bit 6 - Bit 5 24,23 PCIE5 Output Control RW Disable Enable 1 Bit 4 - Bit 3 18,17 PCIE3 Output Control RW Disable Enable 1 Bit 2 11,12 PCIE2 Output Control RW Disable Enable 1 Bit 1 - Bit 0 5,6 PCIE0 Output Control RW Disable Enable 1 SMBusTable: Function Select Register Byte 2 Pin # Name Control Function Type 0 1 PWD Bit 7 Bit 6 Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 - RESERVED RW - IDT TM /ICS TM ICS9DB106 REV F 12/14/07 10

11 SMBusTable: Vendor & Revision ID Register Byte 3 Pin # Name Control Function Type 0 1 PWD Bit 7 - RID3 - Bit 6 - RID2 - REVISION ID Bit 5 - RID1 - Bit 4 - RID0 - Bit 3 - VID3-0 Bit 2 - VID2-0 VENDOR ID Bit 1 - VID1-0 Bit 0 - VID0-1 SMBusTable: DEVICE ID Byte 4 Pin # Name Control Function Type 0 1 PWD Bit 7-0 Bit 6-0 Bit 5-0 Bit 4 - Device ID 0 Bit 3 - = 06 Hex 0 Bit 2-1 Bit 1-1 Bit 0-0 SMBusTable: Byte Count Register Byte 5 Pin # Name Control Function Type 0 1 PWD Bit 7 - BC7 RW Bit 6 - BC6 RW Writing to this Bit 5 - BC5 RW register will configure Bit 4 - BC4 RW how many bytes will Bit 3 - BC3 RW be read back, default Bit 2 - BC2 RW is 06 = 6 bytes. Bit 1 - BC1 RW Bit 0 - BC0 RW IDT TM /ICS TM ICS9DB106 REV F 12/14/07 11

12 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A A A b c D E E e 0.65 BASIC BASIC L N a VARIATIONS D mm. D (inch) N MIN MA MIN MA mil SSOP Reference Doc.: JEDEC Publication 95, MO-150 Ordering Information ICS 9DB106yFLFT Example: ICS y F LF-T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) IDT TM /ICS TM ICS9DB106 REV F 12/14/07 12

13 INDE AREA A2 e N 1 2 D b E1 E A A1 c -C- - SEATING PLANE aaa C α L In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MA MIN MA A A A b c D E 6.40 BASIC BASIC E e 0.65 BASIC BASIC L N a aaa VARIATIONS D mm. D (inch) N MIN MA MIN MA mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) Reference Doc.: JEDEC Publication 95, MO-153 Ordering Information Example: ICS 9DB106yGLFT ICS y G LF-T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) IDT TM /ICS TM ICS9DB106 REV F 12/14/07 13

14 Revision History Rev. Issue Date Description Page # B 09/12/05 1. Changed Output to Output skew from 30ps to 45ps. 2. Changed PLL mode jitter from 40ps to 35ps. 3. Changed Bypass mode additive jitter from 25ps to 35ps. 4. Updated LF Ordering Information. 5, 8-9 C 08/17/06 Corrected Typo of SMBus Read/Write Address. D 03/12/07 Added SMBus Read/Write Table. 6 E 08/06/07 1. Added Phase Noise Parameters, Updated input to output delay values. 2. PLL BW moved to PLL parameters table. 3. Added terminations tables. 6-8 F 12/14/07 Updated SMBus serial Interface Information. 9 7 Innovate with IDT and accelerate your future networks. Contact: For Sales Fax: For Tech Support pcclockhelp@idt.com Corporate Headquarters Integrated Device Technology, Inc Silver Creek Valley Road San Jose, CA United States (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No G 435 Orchard Road #20-03 Wisma Atria Singapore Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE TM 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA