Introduction to GPU Computing. Design and Analysis of Parallel Algorithms

Transcription

1 Introduction to GPU Computing Design and Analysis of Parallel Algorithms

2 Sources CUDA Programming Guide (3.2) CUDA Best Practices Guide (3.2) CUDA Toolkit Reference Manual (3.2) CUDA SDK Examples

3 Part I Introduction

4 Multi-core versus many-core Multi-core (CPU) Many-core (GPU) Control ALU Control ALU Cache Many-core processors: 1. More and simpler cores 2. Massive parallelism

5 The evolution of CPUs and GPUs CPUs: General purpose Sequential Advanced core features Recent growth in number of cores GPUs: Special purpose (graphics) Massively parallel Large memory bandwidth Simple core features Recent move toward general purpose programming

6 Part II Overview of the CUDA programming model

7 hello.cu 1. Source code: #include <stdio.h> #include <stdlib.h> #include <cuda.h> global void hello(void) {} int main(int argc, char *argv[]) { hello<<<1,1>>>(); printf("%s\n", cudageterrorstring(cudagetlasterror())); return 0; } 2. Output: > no error

8 Get started 1. Log in to hamrinsberget 2. Load the CUDA module: module load cudatoolkit/ Type in the code on the previous slide in a file called hello.cu 4. Compile and link by typing nvcc -o hello hello.cu 5. Run the program by typing./hello

9 Kernels, grids, and thread blocks Kernel Grid Block Block Block Block Block Block Block Block Block Older GPU Newer GPU Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Time Block Time

10 Kernel A function written in CUDA C Run by multiple threads in parallel on the device Each thread is given a unique ID Number of threads set when the kernel is launched

11 Kernel Example Kernel code: global void kernel(void) { return; } Host code that launches the kernel with 8 4 = 32 threads: kernel<<<8,4>>>();

12 Thread Sequential scalar thread of execution Very very cheap (almost free) Managed in hardware by the device

13 Thread block A (small) group of threads Typically around 128 or 256 threads per block Size of the thread block determined at kernel launch Threads within a thread block share a fast memory

14 Grid A group of thread blocks Size of grid determined at kernel launch Threads in different thread blocks cannot synchronize

15 Warp A (small) subset of a thread block Typically 32 threads per warp Size determined by the hardware Threads within a warp execute in SIMD fashion

16 Part III Overview of the CUDA architecture

17 Memory hierarchy Host mem Accessible by the host (and also by the GPU via mapped memory). GPU mem Accessible by the GPU directly and by the CPU via an API. Shared mem Private memory associated with each thread block. Registers Private memory associated with each thread. There are also other types of memories which we don t go into.

18 SIMT architecture SIMT Single Instruction Multiple Thread Device A collection of streaming multiprocessors. Streaming multiprocessor A collection of streaming processors with a shared memory and shared control logic. Streaming processor A sequential scalar core. Hundreds or thousands of streaming processors per device.

19 Problems associated with SIMT Global memory accesses Threads within a warp can access memory independently How do we minimize the number of memory transactions? Shared memory accesses Shared memory divided into separate banks for increased bandwidth How do we exploit this parallelism? Branches Threads within a warp can take different branches Warps execute in SIMD fashion How do we exploit the SIMD parallelism?

20 Coalescing of global memory accesses Accesses to nearby data are coalesced into a single memory transaction If all accesses are nearby, then only one memory transaction is issued If all accesses are scattered, then roughly one memory transaction per thread is issued

21 Shared memory bank conflicts Shared memory divided into separate (e.g., 16) banks for increased bandwidth Successive 32B chunks are interleaved across the banks Simultaneous accesses to the same bank are serialized

22 SIMT/warp scheduler With re-convergence A B C D F E G

23 SIMT/warp scheduler Without re-convergence: serialization A B C D F E E G G G

24 SIMT/warp scheduler Stack One way to support re-convergence in hardware is via a stack Each stack entry consists of three fields: 1. Next program counter 2. Active threads mask 3. Re-convergence program counter At a branch, the following actions are taken: 1. Update the next program counter of the top entry to the re-convergence point of the branch 2. Add a new stack entry for the branch not taken threads 3. Add a new stack entry for the branch taken threads

25 SIMT/warp scheduler Stack A 1111 Initial configuration

26 SIMT/warp scheduler Stack After branch at A G 1111 F 0001 G B 1110 G

27 SIMT/warp scheduler Stack After branch at B G 1111 F 0001 G E 1110 G D 0110 E C 1000 E

28 SIMT/warp scheduler Stack G 1111 F 0001 G E 1110 G D 0110 E E 1000 E After C

29 SIMT/warp scheduler Stack G 1111 F 0001 G E 1110 G E 0110 E After D

30 SIMT/warp scheduler Stack G 1111 F 0001 G G 1110 G After E

31 SIMT/warp scheduler Stack G 1111 G 0001 G After F

32 SIMT/warp scheduler Stack G 1111 After complete re-convergence

33 Occupancy Need many warps per streaming multi-processor to hide latencies However, warps consume resources such as registers and shared memory Occupancy measures the percentage of the maximum number of warps that can be assigned to a streaming multi-processor Heuristics: # threads per block should be a multiple of the warp size At least 64 threads per block should be used Between 128 and 256 threads per block is a good starting point Better to have several small blocks than only one large block per multi-processor if latency is a problem

34 Summary of optimization hints Coalesce global memory accesses Resolve shared memory bank conflicts Avoid branch divergence within warps

35 Part IV Overview of the CUDA C/C++ extensions

36 Function type qualifiers device Compiles function for the device. Callable only from the device. global Compiles function for the device. Callable only from the device. host Compiles function for the host. Callable only from the host. Default if nothing else specified. Used mainly together with device in order to compile the function for both the device and the host. Some restrictions: 1. Neither device nor global support recursion, static variables, variable number of arguments. 2. global functions must have void return type. 3. A call to a global function is asynchronous (returns before it is completed).

37 Variable type qualifiers device Places the variable in the device s global memory. shared Places the variable in a thread block s shared memory. Can also be dynamically allocated at kernel invocation time with some restrictions.

38 Vector types charx shortx intx longx longlongy floatx doubley X is 1 4 and Y is 1 2

39 Vector types Access of elements:.x (1st),.y (2nd),.z (3rd),.w (4th) Construction of vectors: make_<type>(x,..., w) Example: float4 f4 = make_float4(0.f,1.f,2.f,3.f);

40 Execution configuration 1. General syntax: kernel<<<g,b,n,s>>>(...) 2. G: Size of the grid (type dim3 or int) 3. B: Size of thread block (type dim3 or int) 4. N: Size of dynamically allocated shared memory (in bytes/block) 5. S: Stream associated with the kernel invocation 6. N and S default to 0 if omitted

41 Execution configuration Example dim3 block(16,16); dim3 grid(columns/block.x,rows/block.y); kernel<<<grid,block,sizeof(float)*block.x>>>(); Launches a grid with thread blocks of size Allocates sizeof(float)*block.x bytes of shared memory per thread block

42 Dynamically allocated shared memory Often, the amount of shared memory requires depends on the size of a thread block Therefore, CUDA allows shared memory to be allocated dynamically as follows A declaration of the form extern shared sh[]; indicates a dynamically allocated array in shared memory The size of the array is specified when the kernel is launched

43 Built-in variables in global functions threadidx (type uint3) Thread ID within thread block blockdim (type dim3) Thread block size blockidx (type uint3) Thread block ID within grid griddim (type dim3) Grid size warpsize (type int) Number of threads in a warp

44 Part V Examples

45 Vector addition Add two n-vectors A and B One thread for each component n-way parallelism Kernel code: global void vectoradd(float *A, float *B, int n) { int i = blockidx.x*blockdim.x + threadidx.x; if (i < n) A[i] += B[i]; } Execution configuration: vectoradd<<<(n+127)/128,128>>>(a, B, n);

46 Fractal image generation Mandelbrot set centered at (0.4, 0.2) with width 0.05

47 Fractal image generation Sequential algorithm for each point c C do z 0 C iter 0 while iter < maxiter z 2 < 4 do z z 2 + c iter iter + 1 end while Determine the color of c as a function of iter. end for

48 Fractal image generation 1. Source code: global void mandelbrot_gpu_kernel(...) { int y = blockidx.y*blockdim.y+threadidx.y; int x = blockidx.x*blockdim.x+threadidx.x; float X0 = xmin + ((xmax-xmin)/(xres-1))*x; float Y0 = ymin + ((ymax-ymin)/(yres-1))*y; int iter; float X=0, Y=0; for (iter = 0; iter < maxiter && X*X + Y*Y <= 4; iter++) { float Z = X*X - Y*Y + X0; Y = 2*X*Y + Y0; X = Z; } image[y*xres+x] = (1.f) - iter / (float) maxiter; } 2. Result: 80 times speedup over (unoptimized) CPU version.

49 Edge detection Using the Sobel operator

50 Edge detection Sequential algorithm for each pixel, A(y, x), of the input image do A s A(y 1 : y + 1, x 1 : x + 1) X A s Y A s L x = i j X (i, j) L y = i j Y (i, j) B(y, x) L 2 x + L 2 Y end for ( denotes element-wise multiplication)

51 Edge detection 1. Source code: global void edge_kernel(float *A, float *B, int width, int height) { int y = blockidx.y*blockdim.y + threadidx.y; int x = blockidx.x*blockdim.x + threadidx.x; if (y >= 1 && y < height-1 && x >= 1 && x < width-1) { float a00 = A[(y-1)*width+(x-1)]; //... snip... float a22 = A[(y+1)*width+(x+1)]; float Lx, Ly; Lx = -a00-2*a10 - a20 + a02 + 2*a12 + a22; Ly = -a00-2*a01 - a02 + a20 + 2*a21 + a22; float res = sqrtf(lx*lx + Ly*Ly); if (res < 0.4f) res = 0.0f; else res = 1.0f; B[y*width+x] = res; } }

52 Matrix addition Add two n n-matrices A and B One thread for each component n 2 -way parallelism Kernel code: global void matrixadd(float *A, float *B, int n) { int row = blockidx.y*blockdim.y + threadidx.y; int column = blockidx.x*blockdim.x + threadidx.x; if (row < n && column < n) A[row*n+column] += B[row*n+column]; } Execution configuration: dim3 block(16,16); dim3 grid((n+block.x-1)/block.x,(n+block.y-1)/block.y); vectoradd<<<grid,block>>>(a, B, n);

53 Effect of non-coalesced memory accesses Matrix addition Good Warps across the rows of the matrix. Bad Warps across the columns of the matrix Effect of non coalesced memory accesses 10 1 Time/speedup Good Bad Bad/Good (speedup) n

54 Matrix multiplication: C = AB B jb A ib C 1. Recall: C(i, j) = K k=1 A(i, k)b(k, j) 2. Partition C into blocks. 3. One thread block computes one block of C 4. One thread computes one entry of C

55 Matrix multiplication Simple global void gemm_kernel(matrix A, Matrix B, Matrix C) { int row = blockidx.y * blockdim.y + threadidx.y; int col = blockidx.x * blockdim.x + threadidx.x; float Cval = 0; for (int j = 0; j < A.n; j++) Cval += A.mtx[row*A.n+j] * B.mtx[j*B.n+col]; C.mtx[row*C.n+col] = Cval; } 1. Compute the thread s row and col indices. 2. Initialize the accumulator Cval to zero. 3. Compute a dot product using a loop. 4. Store the dot product in C.

56 Matrix multiplication Using shared memory global void gemm_kernel(matrix A, Matrix B, Matrix C) { int ib = blockidx.y, jb = blockidx.x; int i = threadidx.y, j = threadidx.x; shared float As[BLOCK_SIZE][BLOCK_SIZE]; shared float Bs[BLOCK_SIZE][BLOCK_SIZE]; float Cval = 0; for (int kb = 0; kb < A.n/BLOCK_SIZE; kb++) { As[i][j] = A.mtx[(ib*BLOCK_SIZE+i)*A.n+(kb*BLOCK_SIZE+j)]; Bs[i][j] = B.mtx[(kb*BLOCK_SIZE+i)*B.n+(jb*BLOCK_SIZE+j)]; syncthreads(); for (int k = 0; k < BLOCK_SIZE; k++) Cval = Cval + As[i][k] * Bs[k][j]; syncthreads(); } C.mtx[(ib*BLOCK_SIZE+i)*C.n+(jb*BLOCK_SIZE+j)] = Cval; } 1. Load submatrices of A and B into shared memory. 2. Compute dot product using cached submatrices. 3. Store in C.

57 Effect of bank conflicts Matrix multiplication Good Warps across the rows of cached B. Bad Warps across the columns of cached B. 250 Effect of bank conflicts 200 Gflops/s Good Bad n

58 Part VI CUDA runtime API overview

59 Memory management API (Host-side) Functions: cudahostalloc(ptr, sz, flags) cudamallochost(ptr, sz) cudamallochost(ptr, sz) cudafreehost(ptr) (and more)

60 Memory management API (Device-side) Functions: cudamalloc(ptr, sz) cudamallocpitch(ptr, pitch, width, height) cudamalloc3d(pitched, extent) cudafree(ptr) (and more)

61 Data transfers API Functions: cudamemcpy(dst, src, cnt, kind) cudamemcpyasync(dst, src, cnt, kind, str) cudamemcpy2d(d, dp, s, sp, w, h, kind) cudamemcpy2dasync(d, dp, s, sp, w, h, kind, str) cudamemcpy3d(p) cudamemcpy3dasync(p, str) (and more)

62 Thread management API Functions: cudathreadsynchronize() (and more)

63 Error handling API Most CUDA functions return a cudaerror_t object No error is signaled by returning cudasuccess Data type: cudaerror_t Functions: err = cudagetlasterror() cudageterrorstring(err) (and more)

64 Streams CUDA manages parallelism using streams Each command is assigned to a stream (default: 0) Commands within a stream execute sequentially Commands from different streams may execute in parallel

65 Streams API Data type: cudastream_t Functions: cudastreamcreate(str) cudastreamquery(str) cudastreamsynchronize(str) cudastreamwaitevent(str, ev, flags) cudastreamdestroy(str) (and more)

66 Streams Example cudastream_t str1, str2; cudaevent_t ev1, ev2; cudastreamcreate(&str1); cudastreamcreate(&str2); cudaeventcreate(&ev1); cudaeventcreate(&ev2); for (int i = 0; i < 2; i++) //... asynchronous transfer on stream i... for (int i = 0; i < 2; i++) //... kernel launch on stream i... cudaeventrecord(ev1, str1); cudaeventrecord(ev2, str2); cudastreamwaitevent(null, ev1, 0); cudastreamwaitevent(null, ev2, 0); //... transfer from device to host... cudastreamdestroy(str1); cudastreamdestroy(str2); cudaeventdestroy(ev1); cudaeventdestroy(ev2);

67 Events Record events on the device Query elapsed time between two events Allows one to measure transfer times and kernel times Allows one to get progress informatio from the device

68 Events API Data type: cudaevent_t Functions: cudaeventcreate(ev) cudaeventrecord(ev, str) cudaeventquery(ev) cudaeventsynchronize(ev) cudaeventelapsedtime(ms, start, end) cudaeventdestroy(ev) (and more)

69 Events Example cudaevent_t ev1, ev2; cudaeventcreate(&ev1); cudaeventcreate(&ev2); cudaeventrecord(ev1, 0); //... memcpy and/or kernels... cudaeventrecord(ev2, 0); cudaeventsynchronize(ev2); float ms; cudaeventelapsedtime(&ms, ev1, ev2); cudaeventdestroy(ev1); cudaeventdestroy(ev2);